void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
u32 pm1_cnt;
u16 pm1_sts;
if (MCHBAR16(SSKPD) == 0xCAFE) {
outb(0x6, 0xcf9);
hlt ();
}
struct pei_data pei_data = {
pei_version: PEI_VERSION,
mchbar: DEFAULT_MCHBAR,
dmibar: DEFAULT_DMIBAR,
epbar: DEFAULT_EPBAR,
pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
smbusbar: SMBUS_IO_BASE,
wdbbar: 0x4000000,
wdbsize: 0x1000,
hpet_address: CONFIG_HPET_ADDRESS,
rcba: DEFAULT_RCBABASE,
pmbase: DEFAULT_PMBASE,
gpiobase: DEFAULT_GPIOBASE,
thermalbase: 0xfed08000,
system_type: 0, // 0 Mobile, 1 Desktop/Server
tseg_size: CONFIG_SMM_TSEG_SIZE,
spd_addresses: { 0xA0, 0x00,0xA2,0x00 },
void main(unsigned long bist)
{
int s3resume = 0;
if (bist == 0)
enable_lapic();
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
ich7_enable_lpc();
early_superio_config();
/* Set up the console */
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
outb(0x6, 0xcf9);
halt();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i945_early_initialization();
/* This has to happen after i945_early_initialization() */
init_artec_dongle();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
sdram_initialize(s3resume ? 2 : 0, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
}
static void disable_igd(const sysinfo_t *const sysinfo)
{
const device_t mch_dev = PCI_DEV(0, 0, 0);
printk(BIOS_DEBUG, "Disabling IGD.\n");
u16 reg16;
reg16 = pci_read_config16(mch_dev, D0F0_GGC);
reg16 &= 0xff0f; /* Disable Graphics Stolen Memory. */
reg16 |= 0x0002; /* Disable IGD. */
pci_write_config16(mch_dev, D0F0_GGC, reg16);
MCHBAR8(0xf10) |= (1 << 0);
if (!(pci_read_config8(mch_dev, D0F0_CAPID0 + 4) & (1 << (33 - 32)))) {
MCHBAR16(0x1190) |= (1 << 14);
MCHBAR16(0x119e) = (MCHBAR16(0x119e) & ~(7 << 13)) | (4 << 13);
MCHBAR16(0x119e) |= (1 << 12);
}
}
void main(unsigned long bist)
{
int s3resume = 0, boot_mode = 0;
if (bist == 0)
enable_lapic();
ich7_enable_lpc();
/* Enable SuperIO PM */
lpc47m15x_enable_serial(PME_DEV, 0x680);
lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
/* Set up the console */
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1;
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
}
void main(unsigned long bist)
{
int s3resume = 0;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 };
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
ich7_enable_lpc();
/* Set up the console */
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG,
"Soft reset detected, rebooting properly.\n");
outb(0x6, 0xcf9);
halt();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
timestamp_add_now(TS_END_ROMSTAGE);
}
static void pineview_setup_bars(void)
{
u8 reg8;
u16 reg16;
u32 reg32;
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */
pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(LPC, 0x4c /* GC */ , 0x10); /* Enable GPIOs */
pci_write_config32(LPC, 0x88, 0x007c0291);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
printk(BIOS_DEBUG, " done.\n");
/* Enable upper 128bytes of CMOS */
RCBA32(0x3400) = (1 << 2);
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
pci_write_config8(D0F0, 0x8, 0x69);
/* Set up all hardcoded northbridge BARs */
pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1);
reg32 = MCHBAR32(0x30);
MCHBAR32(0x30) = 0x21800;
DMIBAR32(0x2c) = 0x86000040;
pci_write_config8(D0F0, DEVEN, 0x09);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000);
reg8 = pci_read_config8(D0F0, 0xe5); // 0x10
reg16 = pci_read_config16(PCI_DEV(0, 0x02, 0), 0x0); // 0x8086
reg16 = pci_read_config16(D0F0, GGC);
pci_write_config16(D0F0, GGC, 0x130);
reg16 = pci_read_config16(D0F0, GGC);
pci_write_config16(D0F0, GGC, 0x130);
MCHBAR8(0xb08) = 0x20;
reg8 = pci_read_config8(D0F0, 0xe6); // 0x11
reg16 = MCHBAR16(0xc8c);
MCHBAR16(0xc8c) = reg16 | 0x0200;
reg8 = MCHBAR8(0xc8c);
MCHBAR8(0xc8c) = reg8;
MCHBAR8(0xc8c) = 0x12;
pci_write_config8(PCI_DEV(0, 0x02, 0), 0x62, 0x02);
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe8, 0x8000);
MCHBAR32(0x3004) = 0x48000000;
MCHBAR32(0x3008) = 0xfffffe00;
MCHBAR32(0xb08) = 0x06028220;
MCHBAR32(0xff4) = 0xc6db8b5f;
MCHBAR16(0xff8) = 0x024f;
// PLL Voltage controlled oscillator
//MCHBAR8(0xc38) = 0x04;
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xcc, 0x014d);
reg32 = MCHBAR32(0x40);
MCHBAR32(0x40) = 0x0;
reg32 = MCHBAR32(0x40);
MCHBAR32(0x40) = 0x8;
pci_write_config8(LPC, 0x8, 0x1d);
pci_write_config8(LPC, 0x8, 0x0);
RCBA32(0x3410) = 0x00020465;
RCBA32(0x88) = 0x0011d000;
RCBA32(0x1fc) = 0x60f;
RCBA32(0x1f4) = 0x86000040;
RCBA32(0x214) = 0x10030509;
RCBA32(0x218) = 0x00020504;
RCBA32(0x220) = 0xc5;
RCBA32(0x3430) = 0x1;
RCBA32(0x2027) = 0x38f6a70d;
RCBA16(0x3e08) = 0x0080;
RCBA16(0x3e48) = 0x0080;
RCBA32(0x3e0e) = 0x00000080;
RCBA32(0x3e4e) = 0x00000080;
RCBA32(0x2034) = 0xb24577cc;
RCBA32(0x1c) = 0x03128010;
RCBA32(0x2010) = 0x400;
RCBA32(0x3400) = 0x4;
RCBA32(0x2080) = 0x18006007;
RCBA32(0x20a0) = 0x18006007;
RCBA32(0x20c0) = 0x18006007;
RCBA32(0x20e0) = 0x18006007;
pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1);
RCBA32(0x3100) = 0x42210;
RCBA32(0x3108) = 0x10004321;
RCBA32(0x310c) = 0x00214321;
RCBA32(0x3110) = 0x1;
RCBA32(0x3140) = 0x01460132;
RCBA32(0x3142) = 0x02370146;
RCBA32(0x3144) = 0x32010237;
RCBA32(0x3146) = 0x01463201;
RCBA32(0x3148) = 0x146;
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(D0F0, PAM0, 0x30);
pci_write_config8(D0F0, PAM1, 0x33);
pci_write_config8(D0F0, PAM2, 0x33);
pci_write_config8(D0F0, PAM3, 0x33);
pci_write_config8(D0F0, PAM4, 0x33);
pci_write_config8(D0F0, PAM5, 0x33);
pci_write_config8(D0F0, PAM6, 0x33);
pci_write_config32(D0F0, SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
printk(BIOS_DEBUG, " done.\n");
}
void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 0, // 0 Mobile, 1 Desktop/Server
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00,0xa4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2,
.max_ddr3_freq = 1333,
.usb_port_config = {
{ 1, 0, 0x0080 }, /* P0: Front port (OC0) */
{ 1, 1, 0x0040 }, /* P1: Back port (OC1) */
{ 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */
{ 1, 0, 0x0040 }, /* P3: MMC (no OC) */
{ 1, 2, 0x0080 }, /* P4: Front port (OC2) */
{ 0, 0, 0x0000 }, /* P5: Empty */
{ 0, 0, 0x0000 }, /* P6: Empty */
{ 0, 0, 0x0000 }, /* P7: Empty */
{ 1, 4, 0x0040 }, /* P8: Back port (OC4) */
{ 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */
{ 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */
{ 0, 4, 0x0000 }, /* P11: Empty */
{ 1, 6, 0x0040 }, /* P12: Back port (OC6) */
{ 1, 5, 0x0040 }, /* P13: Back port (OC5) */
},
};
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
pch_enable_lpc();
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&stumpy_gpio_map);
setup_sio_gpios();
/* Early SuperIO setup */
it8772f_ac_resume_southbridge(DUMMY_DEV);
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
init_bootmode_straps();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected\n");
boot_mode = 1;
/* System is not happy after keyboard reset... */
printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
outb(0x6, 0xcf9);
halt();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
/* Prepare USB controller early in S3 resume */
if (boot_mode == 2) {
/*
* For Stumpy the back USB ports are reset on resume
* so default to resetting the controller to make the
* kernel happy. There is a CMOS flag to disable the
* controller reset in case the kernel can tolerate
* the device power loss better in the future.
*/
u8 magic = cmos_read(CMOS_USB_RESET_DISABLE);
if (magic == USB_RESET_DISABLE_MAGIC) {
printk(BIOS_DEBUG, "USB Controller Reset Disabled\n");
enable_usb_bar();
} else {
printk(BIOS_DEBUG, "USB Controller Reset Enabled\n");
}
} else {
/* Ensure USB reset on resume is enabled at boot */
cmos_write(0, CMOS_USB_RESET_DISABLE);
}
post_code(0x39);
pei_data.boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3a);
/* Perform some initialization that must run before stage2 */
early_pch_init();
post_code(0x3b);
rcba_config();
post_code(0x3c);
quick_ram_check();
post_code(0x3e);
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
if (boot_mode!=2)
save_mrc_data(&pei_data);
if (boot_mode==2 && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
halt();
}
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
}
void main(unsigned long bist)
{
int s3resume = 0;
spd_raw_data spd[4];
if (MCHBAR16(SSKPD) == 0xCAFE) {
outb(0x6, 0xcf9);
halt ();
}
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
pch_enable_lpc();
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
early_usb_init(mainboard_usb_ports);
/* Initialize console device(s) */
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
s3resume = southbridge_detect_s3_resume();
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
post_code(0x39);
post_code(0x3a);
memset (spd, 0, sizeof (spd));
mainboard_get_spd(spd);
timestamp_add_now(TS_BEFORE_INITRAM);
init_dram_ddr3(spd, 1, get_mem_min_tck(), s3resume);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3c);
southbridge_configure_default_intmap();
rcba_config();
post_code(0x3d);
northbridge_romstage_finalize(s3resume);
#if CONFIG_LPC_TPM
init_tpm(s3resume);
#endif
post_code(0x3f);
timestamp_add_now(TS_END_ROMSTAGE);
}
/* Platform has no romstage entry point under mainboard directory,
* so this one is named with prefix mainboard.
*/
void mainboard_romstage_entry(unsigned long bist)
{
sysinfo_t sysinfo;
int s3resume = 0;
int cbmem_initted;
u16 reg16;
/* basic northbridge setup, including MMCONF BAR */
gm45_early_init();
if (bist == 0)
enable_lapic();
/* First, run everything needed for console output. */
i82801ix_early_init();
setup_pch_gpios(&mainboard_gpio_map);
mb_setup_lpc();
mb_setup_superio();
console_init();
report_bist_failure(bist);
reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
gm45_early_reset();
}
/* ASPM related setting, set early by original BIOS. */
DMIBAR16(0x204) &= ~(3 << 10);
/* Check for S3 resume. */
s3resume = southbridge_detect_s3_resume();
/* RAM initialization */
enter_raminit_or_reset();
memset(&sysinfo, 0, sizeof(sysinfo));
get_mb_spd_addrmap(sysinfo.spd_map);
const struct device *dev;
dev = pcidev_on_root(2, 0);
if (dev)
sysinfo.enable_igd = dev->enabled;
dev = pcidev_on_root(1, 0);
if (dev)
sysinfo.enable_peg = dev->enabled;
get_gmch_info(&sysinfo);
mb_pre_raminit_setup(&sysinfo);
raminit(&sysinfo, s3resume);
mb_post_raminit_setup();
const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
/* Disable D4F0 (unknown signal controller). */
pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
init_pm(&sysinfo, 0);
i82801ix_dmi_setup();
gm45_late_init(sysinfo.stepping);
i82801ix_dmi_poll_vc1();
MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
init_iommu();
cbmem_initted = !cbmem_recovery(s3resume);
romstage_handoff_init(cbmem_initted && s3resume);
printk(BIOS_SPEW, "exit main()\n");
}
void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 0, // 0 Mobile, 1 Desktop/Server
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2,
.max_ddr3_freq = 1600,
.usb_port_config = {
{ 1, 0, 0x0040 }, /* P0: Front port (OC0) */
{ 1, 1, 0x0040 }, /* P1: Back port (OC1) */
{ 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */
{ 1, 0, 0x0040 }, /* P3: MMC (no OC) */
{ 1, 2, 0x0040 }, /* P4: Front port (OC2) */
{ 0, 0, 0x0000 }, /* P5: Empty */
{ 0, 0, 0x0000 }, /* P6: Empty */
{ 0, 0, 0x0000 }, /* P7: Empty */
{ 1, 4, 0x0040 }, /* P8: Back port (OC4) */
{ 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */
{ 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */
{ 0, 4, 0x0000 }, /* P11: Empty */
{ 1, 6, 0x0040 }, /* P12: Back port (OC6) */
{ 1, 5, 0x0040 }, /* P13: Back port (OC5) */
},
};
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
pch_enable_lpc();
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&emeraldlake2_gpio_map);
setup_sio_gpios();
/* Early SuperIO setup */
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected\n");
boot_mode = 1;
/* System is not happy after keyboard reset... */
printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
outb(0x6, 0xcf9);
halt();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
/* Prepare USB controller early in S3 resume */
if (boot_mode == 2)
enable_usb_bar();
post_code(0x3a);
pei_data.boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3b);
/* Perform some initialization that must run before stage2 */
early_pch_init();
post_code(0x3c);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
post_code(0x3d);
quick_ram_check();
post_code(0x3e);
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
if (boot_mode!=2)
save_mrc_data(&pei_data);
if (boot_mode==2 && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
halt();
}
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
}
static void init_freq_scaling(const gmch_gfx_t sku, const int low_power_mode)
{
int i;
MCHBAR32(0x11cc) = (MCHBAR32(0x11cc) & ~(0x1f)) | 0x17;
switch (sku) {
case GMCH_GM45:
case GMCH_GE45:
case GMCH_GS45:
case GMCH_GM47:
case GMCH_GM49:
break;
default:
/* No more to be done for the others. */
return;
}
static const u32 voltage_mask =
(0x1f << 24) | (0x1f << 16) | (0x1f << 8) | 0x1f;
MCHBAR32(0x1120) = (MCHBAR32(0x1120) & ~voltage_mask) | 0x10111213;
MCHBAR32(0x1124) = (MCHBAR32(0x1124) & ~voltage_mask) | 0x14151617;
MCHBAR32(0x1128) = (MCHBAR32(0x1128) & ~voltage_mask) | 0x18191a1b;
MCHBAR32(0x112c) = (MCHBAR32(0x112c) & ~voltage_mask) | 0x1c1d1e1f;
MCHBAR32(0x1130) = (MCHBAR32(0x1130) & ~voltage_mask) | 0x00010203;
MCHBAR32(0x1134) = (MCHBAR32(0x1134) & ~voltage_mask) | 0x04050607;
MCHBAR32(0x1138) = (MCHBAR32(0x1138) & ~voltage_mask) | 0x08090a0b;
MCHBAR32(0x113c) = (MCHBAR32(0x113c) & ~voltage_mask) | 0x0c0d0e0f;
/* Program frequencies. */
static const u32 frequencies_from_sku_vco[][4][8] = {
/* GM45/GE45/GS45_perf */ {
/* VCO 2666 */ { 0xcd, 0xbc, 0x9b, 0x8a, 0x79, 0x78, 0x67, 0x56 },
/* VCO 3200 */ { 0xcd, 0xac, 0x9b, 0x8a, 0x89, 0x78, 0x67, 0x56 },
/* VCO 4000 */ { 0xac, 0x9b, 0x9a, 0x89, 0x89, 0x68, 0x56, 0x45 },
/* VCO 5333 */ { 0xab, 0x9a, 0x79, 0x68, 0x57, 0x56, 0x45, 0x34 },
},
/* GS45_low_power */ {
/* VCO 2666 */ { 0xcd, 0x8a },
/* VCO 3200 */ { 0xcd, 0x89 },
/* VCO 4000 */ { 0xac, 0x89 },
/* VCO 5333 */ { 0xab, 0x68 },
},
/* GM47 */ {
/* VCO 2666 */ { 0xcd, 0xcd, 0xbc, 0x9b, 0x79, 0x78, 0x67, 0x56 },
/* VCO 3200 */ { 0xde, 0xcd, 0xac, 0x9b, 0x89, 0x78, 0x67, 0x56 },
/* VCO 4000 */ { 0xcd, 0xac, 0x9b, 0x9a, 0x89, 0x68, 0x56, 0x45 },
/* VCO 5333 */ { 0xac, 0xab, 0x9a, 0x79, 0x68, 0x56, 0x45, 0x34 },
},
/* GM49 */ {
/* VCO 2666 */ { },
/* VCO 3200 */ { 0xef, 0xde, 0xcd, 0xac, 0x89, 0x78, 0x67, 0x56 },
/* VCO 4000 */ { 0xef, 0xde, 0xac, 0x9b, 0x89, 0x68, 0x56, 0x45 },
/* VCO 5333 */ { 0xce, 0xbd, 0xab, 0x9a, 0x68, 0x57, 0x45, 0x34 },
}};
const int sku_index = sku_freq_index(sku, low_power_mode);
const int vco_index = raminit_read_vco_index();
const int reg_limit = low_power_mode ? 1 : 4;
if (sku == GMCH_GM49)
MCHBAR8(0x1110+3) = 0x1b;
else
MCHBAR8(0x1110+3) = 0x17;
MCHBAR8(0x1110+1) = 0x17;
if (!low_power_mode) {
MCHBAR8(0x1114+3) = 0x17;
MCHBAR8(0x1114+1) = 0x17;
MCHBAR8(0x1118+3) = 0x17;
MCHBAR8(0x1118+1) = 0x17;
MCHBAR8(0x111c+3) = 0x17;
MCHBAR8(0x111c+1) = 0x17;
}
for (i = 0; i < reg_limit; ++i) {
const int mchbar = 0x1110 + (i * 4);
MCHBAR8(mchbar + 2) = frequencies_from_sku_vco
[sku_index][vco_index][i * 2 + 0];
MCHBAR8(mchbar + 0) = frequencies_from_sku_vco
[sku_index][vco_index][i * 2 + 1];
}
if (low_power_mode) {
MCHBAR16(0x1190) =
(MCHBAR16(0x1190) & ~((7 << 8) | (7 << 4) | 7)) |
(1 << 8) | (1 << 4) | 1;
} else {
MCHBAR16(0x1190) =
(MCHBAR16(0x1190) & ~((7 << 8) | (7 << 4))) | 7;
if (sku == GMCH_GS45) /* performance mode */
MCHBAR32(0x0ffc) &= ~(1 << 31);
}
MCHBAR16(0x0fc0) |= (1 << 11);
MCHBAR16(0x11b8) = 0x333c;
MCHBAR16(0x11c0 + 2) = 0x0303;
MCHBAR32(0x11c4) = 0x0a030a03;
MCHBAR16(0x1100) = (MCHBAR16(0x1100) & ~(0x1f << 8)) | (3 << 8);
MCHBAR16(0x11b8 + 2) = 0x4000;
}
void init_pm(const sysinfo_t *const sysinfo)
{
const stepping_t stepping = sysinfo->stepping;
const fsb_clock_t fsb = sysinfo->selected_timings.fsb_clock;
const mem_clock_t memclk = sysinfo->selected_timings.mem_clock;
MCHBAR16(0xc14) = 0;
MCHBAR16(0xc20) = 0;
MCHBAR32(0xfc0) = 0x001f00fd;
MCHBAR32(0xfc0) |= 3 << 25;
MCHBAR32(0xfc0) |= 1 << 11;
MCHBAR8(0xfb0) = 3;
MCHBAR8(0xf10) |= 1 << 1;
if (fsb == FSB_CLOCK_667MHz) {
MCHBAR16(0xc3a) = 0xea6;
MCHBAR8(0xc16) = (MCHBAR8(0xc16) & 0x80) | 0x0e;
} else if (fsb == FSB_CLOCK_800MHz) {
MCHBAR16(0xc3a) = 0x1194;
MCHBAR8(0xc16) = (MCHBAR8(0xc16) & 0x80) | 0x10;
} else if (fsb == FSB_CLOCK_1067MHz) {
MCHBAR16(0xc3a) = 0x1777;
MCHBAR8(0xc16) = (MCHBAR8(0xc16) & 0x80) | 0x15;
}
MCHBAR8(0xfb8) = 3;
if (fsb == FSB_CLOCK_667MHz)
MCHBAR16(0xc38) = 0x0ea6;
else if (fsb == FSB_CLOCK_800MHz)
MCHBAR16(0xc38) = 0x1194;
else if (fsb == FSB_CLOCK_1067MHz)
MCHBAR16(0xc38) = 0x1777;
MCHBAR8(0xf10) |= 1 << 5;
MCHBAR16(0xc16) |= 3 << 12;
MCHBAR32(0xf60) = 0x01030419;
if (fsb == FSB_CLOCK_667MHz) {
MCHBAR32(0xf00) = 0x00000600;
MCHBAR32(0xf04) = 0x00001d80;
} else if (fsb == FSB_CLOCK_800MHz) {
MCHBAR32(0xf00) = 0x00000700;
MCHBAR32(0xf04) = 0x00002380;
} else if (fsb == FSB_CLOCK_1067MHz) {
MCHBAR32(0xf00) = 0x00000900;
MCHBAR32(0xf04) = 0x00002e80;
}
MCHBAR16(0xf08) = 0x730f;
if (fsb == FSB_CLOCK_667MHz)
MCHBAR16(0xf0c) = 0x0b96;
else if (fsb == FSB_CLOCK_800MHz)
MCHBAR16(0xf0c) = 0x0c99;
else if (fsb == FSB_CLOCK_1067MHz)
MCHBAR16(0xf0c) = 0x10a4;
MCHBAR32(0xf80) |= 1 << 31;
MCHBAR32(0x40) = (MCHBAR32(0x40) & ~(0x3f << 24)) |
(sysinfo->cores == 4) ? (1 << 24) : 0;
MCHBAR32(0x40) &= ~(1 << 19);
MCHBAR32(0x40) |= 1 << 13;
MCHBAR32(0x40) |= 1 << 21;
MCHBAR32(0x40) |= 1 << 9;
if (stepping > STEPPING_B1) {
if (fsb != FSB_CLOCK_1067MHz) {
MCHBAR32(0x70) |= 1 << 30;
} else {
MCHBAR32(0x70) &= ~(1 << 30);
}
}
if (stepping < STEPPING_B1)
MCHBAR32(0x70) |= 1 << 29;
else
MCHBAR32(0x70) &= ~(1 << 29);
if (stepping > STEPPING_B1) {
MCHBAR32(0x70) |= 1 << 28;
MCHBAR32(0x70) |= 1 << 25;
}
if (stepping > STEPPING_B0) {
if (fsb != FSB_CLOCK_667MHz)
MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3<<21)) | (1 << 21);
else
MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3<<21));
}
if (stepping > STEPPING_B2)
MCHBAR32(0x44) |= 1 << 30;
MCHBAR32(0x44) |= 1 << 31;
if (sysinfo->cores == 2)
MCHBAR32(0x44) |= 1 << 26;
MCHBAR32(0x44) |= 1 << 21;
MCHBAR32(0x44) = (MCHBAR32(0x44) & ~(3 << 24)) | (2 << 24);
MCHBAR32(0x44) |= 1 << 5;
MCHBAR32(0x44) |= 1 << 4;
MCHBAR32(0x90) = (MCHBAR32(0x90) & ~7) | 4;
MCHBAR32(0x94) |= 1 << 29;
MCHBAR32(0x94) |= 1 << 11;
if (stepping < STEPPING_B0)
MCHBAR32(0x94) = (MCHBAR32(0x94) & ~(3 << 19)) | (2 << 19);
if (stepping > STEPPING_B2)
MCHBAR32(0x94) |= 1 << 21;
MCHBAR8(0xb00) &= ~1;
MCHBAR8(0xb00) |= 1 << 7;
if (fsb != FSB_CLOCK_1067MHz)
MCHBAR8(0x75) |= 1 << 6;
else
MCHBAR8(0x75) &= 1 << 1;
MCHBAR8(0x77) |= 3;
if (stepping >= STEPPING_B1)
MCHBAR8(0x77) |= 1 << 2;
if (stepping > STEPPING_B2)
MCHBAR8(0x77) |= 1 << 4;
if (MCHBAR16(0x90) & 0x100)
MCHBAR8(0x90) &= ~(7 << 4);
if (stepping >= STEPPING_B0)
MCHBAR8(0xd0) |= 1 << 1;
MCHBAR8(0xbd8) |= 3 << 2;
if (stepping >= STEPPING_B3)
MCHBAR32(0x70) |= 1 << 0;
MCHBAR32(0x70) |= 1 << 3;
if (stepping >= STEPPING_B0)
MCHBAR32(0x70) &= ~(1 << 16);
else
MCHBAR32(0x70) |= 1 << 16;
if (stepping >= STEPPING_B3)
MCHBAR8(0xc14) |= 1 << 1;
if (stepping >= STEPPING_B1)
MCHBAR16(0xffc) = (MCHBAR16(0xffc) & ~0x7ff) | 0x7c0;
MCHBAR16(0x48) = (MCHBAR16(0x48) & ~(0xff << 2)) | (0xaa << 2);
if (stepping == STEPPING_CONVERSION_A1) {
MCHBAR16(0x40) |= 1 << 12;
MCHBAR32(0x94) |= 3 << 22;
}
const int cpu_supports_super_lfm = rdmsr(0xee).lo & (1 << 27);
if ((stepping >= STEPPING_B0) && cpu_supports_super_lfm) {
MCHBAR16(CLKCFG_MCHBAR) &= ~(1 << 7);
MCHBAR16(CLKCFG_MCHBAR) |= 1 << 14;
} else {
MCHBAR16(CLKCFG_MCHBAR) &= ~(1 << 14);
MCHBAR16(CLKCFG_MCHBAR) |= 1 << 7;
MCHBAR32(0x44) &= ~(1 << 31); /* Was set above. */
}
if ((sysinfo->gfx_type != GMCH_PM45) &&
(sysinfo->gfx_type != GMCH_UNKNOWN))
init_freq_scaling(sysinfo->gfx_type,
sysinfo->gs45_low_power_mode);
/* This has to be the last write to CLKCFG. */
if ((fsb == FSB_CLOCK_1067MHz) && (memclk == MEM_CLOCK_667MT))
MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 17);
}
void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 0, // 0 Mobile, 1 Desktop/Server
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2,
.max_ddr3_freq = 1600,
.usb_port_config = {
/* Empty and onboard Ports 0-7, set to un-used pin OC3 */
{ 0, 3, 0x0000 }, /* P0: Empty */
{ 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */
{ 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */
{ 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */
{ 0, 3, 0x0000 }, /* P4: Empty */
{ 0, 3, 0x0000 }, /* P5: Empty */
{ 0, 3, 0x0000 }, /* P6: Empty */
{ 0, 3, 0x0000 }, /* P7: Empty */
/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
{ 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */
{ 0, 4, 0x0000 }, /* P9: Empty */
{ 1, 4, 0x0040 }, /* P10: Camera (no OC) */
{ 0, 4, 0x0000 }, /* P11: Empty */
{ 0, 4, 0x0000 }, /* P12: Empty */
{ 0, 4, 0x0000 }, /* P13: Empty */
},
};
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
pch_enable_lpc();
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&parrot_gpio_map);
/* Initialize console device(s) */
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected\n");
boot_mode = 1;
/* System is not happy after keyboard reset... */
printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
outb(0x6, 0xcf9);
halt();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
/* Prepare USB controller early in S3 resume */
if (boot_mode == 2)
enable_usb_bar();
post_code(0x39);
post_code(0x3a);
pei_data.boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3c);
rcba_config();
post_code(0x3d);
quick_ram_check();
post_code(0x3e);
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
if (boot_mode!=2)
save_mrc_data(&pei_data);
if (boot_mode==2 && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
halt();
}
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
#if CONFIG_CHROMEOS
init_chromeos(boot_mode);
#endif
timestamp_add_now(TS_END_ROMSTAGE);
}
