static void mdss_vbif_setup()
{
int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS);
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
if (!access_secure) {
dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n");
/* Force VBIF Clocks on, not needed for 8084 */
if ((mdp_hw_rev < MDSS_MDP_HW_REV_103) ||
(mdp_hw_rev == MDSS_MDP_HW_REV_106))
writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON);
/*
* Following configuration is needed because on some versions,
* recommended reset values are not stored.
*/
if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_100)) {
writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL );
writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN);
writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO);
writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0);
writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1);
} else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_101) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_106)) {
writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
}
}
}
void mdss_qos_remapper_setup(void)
{
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
uint32_t map;
if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_102))
map = 0xE9;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_101))
map = 0xA5;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_106) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_108))
map = 0xE4;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_105) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_109) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_110))
map = 0xA4;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
MDSS_MDP_HW_REV_103))
map = 0xFA;
else
return;
writel(map, MDP_QOS_REMAPPER_CLASS_0);
}
void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo)
{
uint32_t mask, reg_val, i;
uint32_t left_pipe_xin_id, right_pipe_xin_id;
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
uint32_t vbif_qos[4] = {0, 0, 0, 0};
uint32_t vbif_offset;
mdp_select_pipe_xin_id(pinfo,
&left_pipe_xin_id, &right_pipe_xin_id);
if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108)) {
vbif_qos[0] = 2;
vbif_qos[1] = 2;
vbif_qos[2] = 2;
vbif_qos[3] = 2;
} else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) {
vbif_qos[0] = 1;
vbif_qos[1] = 2;
vbif_qos[2] = 2;
vbif_qos[3] = 2;
} else {
return;
}
vbif_offset = mdss_mdp_vbif_qos_remap_get_offset();
for (i = 0; i < 4; i++) {
/* VBIF_VBIF_QOS_REMAP_00 */
reg_val = readl(REG_MDP(vbif_offset) + i*4);
mask = 0x3 << (left_pipe_xin_id * 2);
reg_val &= ~(mask);
reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2);
if (pinfo->lcdc.dual_pipe) {
mask = 0x3 << (right_pipe_xin_id * 2);
reg_val &= ~(mask);
reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2);
}
writel(reg_val, REG_MDP(vbif_offset) + i*4);
}
}
static uint32_t mdss_mdp_vbif_qos_remap_get_offset()
{
uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
if (mdss_mdp_rev == MDSS_MDP_HW_REV_110)
return 0xB0020;
else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107))
return 0xB0000;
else
return 0xC8020;
}
static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo,
uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id)
{
uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_112)) {
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
*left_sspp_client_id = 0x7; /* 7 */
*right_sspp_client_id = 0x11; /* 17 */
break;
case MDSS_MDP_PIPE_TYPE_DMA:
*left_sspp_client_id = 0x4; /* 4 */
*right_sspp_client_id = 0xD; /* 13 */
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
*left_sspp_client_id = 0x1; /* 1 */
*right_sspp_client_id = 0x4; /* 4 */
break;
}
} else {
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
*left_sspp_client_id = 0x10; /* 16 */
*right_sspp_client_id = 0x11; /* 17 */
break;
case MDSS_MDP_PIPE_TYPE_DMA:
*left_sspp_client_id = 0xA; /* 10 */
*right_sspp_client_id = 0xD; /* 13 */
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
*left_sspp_client_id = 0x1; /* 1 */
*right_sspp_client_id = 0x4; /* 4 */
break;
}
}
}
void mdp_clk_gating_ctrl(void)
{
uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107))
return;
writel(0x40000000, MDP_CLK_CTRL0);
udelay(20);
writel(0x40000040, MDP_CLK_CTRL0);
writel(0x40000000, MDP_CLK_CTRL1);
writel(0x00400000, MDP_CLK_CTRL3);
udelay(20);
writel(0x00404000, MDP_CLK_CTRL3);
writel(0x40000000, MDP_CLK_CTRL4);
}
static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe,
uint32_t right_pipe)
{
uint32_t left_sspp_client_id, right_sspp_client_id;
uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH;
uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0;
uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
if (mdss_mdp_rev == MDSS_MDP_HW_REV_106) {
/* 8Kb per SMP on 8916 */
smp_size = 8192;
} else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) {
/* 10Kb per SMP on 8939 */
smp_size = 10240;
} else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) &&
(mdss_mdp_rev < MDSS_MDP_HW_REV_200)) {
smp_size = 8192;
free_smp_offset = 0xC;
if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB)
fixed_smp_cnt = 2;
else
fixed_smp_cnt = 0;
}
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
right_sspp_client_id = 0x11; /* 17 */
break;
case MDSS_MDP_PIPE_TYPE_DMA:
right_sspp_client_id = 0xD; /* 13 */
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
right_sspp_client_id = 0x4; /* 4 */
break;
}
if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108)) {
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
left_sspp_client_id = 0x7; /* 7 */
break;
case MDSS_MDP_PIPE_TYPE_DMA:
left_sspp_client_id = 0x4; /* 4 */
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
left_sspp_client_id = 0x1; /* 1 */
break;
}
} else {
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
left_sspp_client_id = 0x10; /* 16 */
break;
case MDSS_MDP_PIPE_TYPE_DMA:
left_sspp_client_id = 0xA; /* 10 */
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
left_sspp_client_id = 0x1; /* 1 */
break;
}
}
/* Each pipe driving half the screen */
if (pinfo->lcdc.dual_pipe)
xres /= 2;
/* bpp = bytes per pixel of input image */
smp_cnt = (xres * bpp * 2) + smp_size - 1;
smp_cnt /= smp_size;
if (smp_cnt > 4) {
dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__,
smp_cnt);
ASSERT(0); /* Max 4 SMPs can be allocated per client */
}
writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0);
writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1);
writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2);
if (pinfo->lcdc.dual_pipe) {
writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0);
writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1);
writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2);
}
free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt,
fixed_smp_cnt, free_smp_offset);
if (pinfo->lcdc.dual_pipe)
mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt,
free_smp_offset);
}
static inline bool has_fixed_size_smp()
{
return MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV),
MDSS_MDP_HW_REV_107);
}
static inline bool is_software_pixel_ext_config_needed()
{
return MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV),
MDSS_MDP_HW_REV_107);
}
static void mdss_mdp_set_flush(struct msm_panel_info *pinfo,
uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val)
{
uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe &&
!pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display;
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
if (dual_pipe_single_ctl)
*ctl0_reg_val = 0x220D8;
else
*ctl0_reg_val = 0x22048;
*ctl1_reg_val = 0x24090;
if (pinfo->lcdc.dst_split)
*ctl0_reg_val |= BIT(4);
break;
case MDSS_MDP_PIPE_TYPE_DMA:
if (dual_pipe_single_ctl)
*ctl0_reg_val = 0x238C0;
else
*ctl0_reg_val = 0x22840;
*ctl1_reg_val = 0x25080;
if (pinfo->lcdc.dst_split)
*ctl0_reg_val |= BIT(12);
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
if (dual_pipe_single_ctl)
*ctl0_reg_val = 0x220C3;
else
*ctl0_reg_val = 0x22041;
*ctl1_reg_val = 0x24082;
if (pinfo->lcdc.dst_split)
*ctl0_reg_val |= BIT(1);
break;
}
/* For targets from MDP v1.5, MDP INTF registers are double buffered */
if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
(mdss_mdp_rev == MDSS_MDP_HW_REV_108) ||
(mdss_mdp_rev == MDSS_MDP_HW_REV_112)) {
if (pinfo->dest == DISPLAY_2) {
*ctl0_reg_val |= BIT(31);
*ctl1_reg_val |= BIT(30);
} else {
*ctl0_reg_val |= BIT(30);
*ctl1_reg_val |= BIT(31);
}
} else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) ||
(mdss_mdp_rev == MDSS_MDP_HW_REV_109) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev,
MDSS_MDP_HW_REV_107) ||
(mdss_mdp_rev == MDSS_MDP_HW_REV_110)) {
if (pinfo->dest == DISPLAY_2) {
*ctl0_reg_val |= BIT(29);
*ctl1_reg_val |= BIT(30);
} else {
*ctl0_reg_val |= BIT(30);
*ctl1_reg_val |= BIT(29);
}
}
}
