void pwr_set_clk(w99702_clk_t *cfg) { unsigned int reg,bak,bak_audio, bak_mp4dec; unsigned int clkcon, clksel, clkdiv0; volatile int delay; MEMCLEAN(); MEMPRINT(1); /* if UPLL is enabled, switch the PLL to APLL first */ bak = 0; bak_audio = 0; bak_mp4dec = 0; reg = inpw(REG_CLKSEL); /* Set the audio clock */ clkcon = (cfg->clkcon & ((1UL<<30))) | (inpw(REG_CLKCON)&(~(1<<30))); clksel = (cfg->clksel&(0x30UL)) | (inpw(REG_CLKSEL)&(~0x30UL)); clkdiv0 = (cfg->clkdiv0 & 0x00F00000UL) | (inpw(REG_CLKDIV0) & 0xFF0FFFFFUL); outpw(REG_CLKCON, inpw(REG_CLKCON) & (~(1UL<<30)) ); DELAY(DELAY_LOOPS); outpw(REG_CLKSEL, clksel); outpw(REG_CLKDIV0, clkdiv0); outpw(REG_APLLCON, cfg->apllcon); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); /* Reserve the audio clock */ if(inpw(REG_APLLCON)!=0xE220) { cfg->apllcon = inpw(REG_APLLCON); cfg->clkdiv0 = (cfg->clkdiv0 & 0xFF0FFFFFUL) | (inpw(REG_CLKDIV0) & 0x00F00000UL); } MEMPRINT(2); /* Set the USB clock */ clkcon = (cfg->clkcon & ((1UL<<26))) | (inpw(REG_CLKCON)&(~(1<<26))); clksel = (cfg->clksel&(0x3UL)) | (inpw(REG_CLKSEL)&(~0x3UL)); clkdiv0 = (cfg->clkdiv0 & 0x000F0000UL) | (inpw(REG_CLKDIV0) & 0xFFF0FFFFUL); outpw(REG_CLKCON, inpw(REG_CLKCON) & (~(1UL<<26)) ); DELAY(DELAY_LOOPS); outpw(REG_CLKSEL, clksel); outpw(REG_CLKDIV0, clkdiv0); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); MEMPRINT(2); /* Reserve the USB clock */ cfg->clkcon = (cfg->clkcon & (~(1UL<<26))) | (inpw(REG_CLKCON)&(1<<26)); cfg->clksel = (cfg->clksel&(~0x3UL)) | (inpw(REG_CLKSEL)&0x3); cfg->clkdiv0 = (cfg->clkdiv0 & 0xFFF0FFFFUL) | (inpw(REG_CLKDIV0) & 0x000F0000UL); MEMPRINT(3); if( inpw(REG_UPLLCON) == cfg->upllcon && (inpw(REG_CLKDIV0)&0xF0000000UL) == (cfg->clkdiv0&0xF0000000UL) && (inpw(REG_CLKDIV1)&0xF0000000UL) == (cfg->clkdiv1&0xF0000000UL) ) { /* Just change dividor when UPLL & HCLK is not changed */ MEMPRINT(4); /* select the clock source */ if(inpw(REG_CLKSEL) != cfg->clksel) { outpw(REG_CLKSEL, cfg->clksel); DELAY(DELAY_LOOPS); } MEMPRINT(5); clkcon = inpw(REG_CLKCON); if(clkcon != cfg->clkcon) { /* Enable IP's step by step */ clkcon |= (cfg->clkcon&0xF0000000); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); clkcon |= (cfg->clkcon&0x00F00000); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); clkcon |= (cfg->clkcon&0x000F0000); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); clkcon |= (cfg->clkcon&0x00000F00); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); clkcon |= (cfg->clkcon&0x000000F0); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); clkcon |= (cfg->clkcon&0x0000000F); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); } MEMPRINT(6); /* setting the dividor */ if(inpw(REG_CLKDIV0) != cfg->clkdiv0) { outpw(REG_CLKDIV0, cfg->clkdiv0); DELAY(DELAY_LOOPS); } MEMPRINT(7); if(inpw(REG_CLKDIV1) != cfg->clkdiv1) { outpw(REG_CLKDIV1, cfg->clkdiv1); DELAY(DELAY_LOOPS); } MEMPRINT(8); /* setting SDRAM control */ if(inpw(REG_SDICON) != cfg->sdcon) { outpw(REG_SDICON, cfg->sdcon); DELAY(DELAY_LOOPS); } MEMPRINT(9); /* setting SDRAM timing */ if(inpw(REG_SDTIME0) != cfg->sdtime0) { outpw(REG_SDTIME0, cfg->sdtime0); DELAY(DELAY_LOOPS); } MEMPRINT(10); } else if( inpw(REG_UPLLCON) == cfg->upllcon ) { /* change dividor and SDRAM timing when only UPLL fixed */ /* Force the SDRAM timing to slowest */ #if CONFIG_MEMORY_SIZE == 16 outpw(REG_SDTIME0, 0xC0006948); #elif CONFIG_MEMORY_SIZE == 8 outpw(REG_SDTIME0, 0xF8006948); #else # error "No memory size defined" #endif DELAY(DELAY_LOOPS); MEMPRINT(11); /* select the clock source */ if(inpw(REG_CLKSEL) != cfg->clksel) { outpw(REG_CLKSEL, cfg->clksel); DELAY(DELAY_LOOPS); } MEMPRINT(12); clkcon = inpw(REG_CLKCON); if( clkcon != cfg->clkcon) { /* Enable IP's step by step */ clkcon |= (cfg->clkcon&0xF0000000); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); clkcon |= (cfg->clkcon&0x00F00000); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); clkcon |= (cfg->clkcon&0x000F0000); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); clkcon |= (cfg->clkcon&0x00000F00); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); clkcon |= (cfg->clkcon&0x000000F0); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); clkcon |= (cfg->clkcon&0x0000000F); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); } MEMPRINT(13); /* setting the dividor */ if(inpw(REG_CLKDIV0) != cfg->clkdiv0) { outpw(REG_CLKDIV0, cfg->clkdiv0); DELAY(DELAY_LOOPS); } MEMPRINT(14); if(inpw(REG_CLKDIV1) != cfg->clkdiv1) { outpw(REG_CLKDIV1, cfg->clkdiv1); DELAY(DELAY_LOOPS); } MEMPRINT(15); /* setting SDRAM control */ if(inpw(REG_SDICON) != cfg->sdcon) { outpw(REG_SDICON, cfg->sdcon); DELAY(DELAY_LOOPS); } MEMPRINT(16); /* setting SDRAM timing */ if(inpw(REG_SDTIME0) != cfg->sdtime0) { outpw(REG_SDTIME0, cfg->sdtime0); DELAY(DELAY_LOOPS); } MEMPRINT(17); } else { /* Force the SDRAM timing to slowest */ #if CONFIG_MEMORY_SIZE == 16 outpw(REG_SDTIME0, 0xC0006948); #elif CONFIG_MEMORY_SIZE == 8 outpw(REG_SDTIME0, 0xF8006948); #else # error "No memory size defined" #endif DELAY(DELAY_LOOPS); MEMPRINT(18); /* close some IP to make system stable */ clkcon = cfg->clkcon & 0x1F07F0FF; outpw(REG_CLKCON , clkcon); MEMPRINT(19); /* Reserve the audio clock */ if(inpw(REG_APLLCON)==0xE220) { outpw(REG_APLLCON, cfg->apllcon); DELAY(DELAY_LOOPS); } /* force the clock source to crystal for futur clock change */ outpw(REG_CLKSEL , 0x0000022C); /* Keep Video clock & system clock as high as possible (clkdiv = 0) */ //outpw(REG_CLKDIV0, inpw(REG_CLKDIV0)&0xFFFF00FF); //outpw(REG_CLKDIV1, inpw(REG_CLKDIV1)&0x0000FFFF); /* change the UPLL first, and wait for stable */ outpw(REG_UPLLCON, cfg->upllcon); DELAY(DELAY_LOOPS); MEMPRINT(25); /* setting the dividor */ outpw(REG_CLKDIV0, cfg->clkdiv0); outpw(REG_CLKDIV1, cfg->clkdiv1); MEMPRINT(20); /* select the clock source to UPLL */ outpw(REG_CLKSEL, cfg->clksel); DELAY(DELAY_LOOPS); MEMPRINT(21); /* Enable IP's step by step */ clkcon |= (cfg->clkcon&0xE0000000); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); MEMPRINT(22); clkcon |= (cfg->clkcon&0x00F00000); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); MEMPRINT(23); clkcon |= (cfg->clkcon&0x000F0000); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); MEMPRINT(24); clkcon |= (cfg->clkcon&0x00000F00); outpw(REG_CLKCON, clkcon); DELAY(DELAY_LOOPS); MEMPRINT(26); /* setting SDRAM control */ outpw(REG_SDICON, cfg->sdcon); DELAY(DELAY_LOOPS); MEMPRINT(27); /* setting SDRAM timing */ outpw(REG_SDTIME0, cfg->sdtime0); DELAY(DELAY_LOOPS); MEMPRINT(28); } }
void CGameState::SetState(const CState& aState) { DEBUG2("CGameState::SetState: %d %d\n",aState.iMainState,aState.iSubState); SELFTEST; // Let's cut out the illegal state changes ASSERT( aState.iMainState >= CState::EMainStateLogo1 ); ASSERT( aState.iMainState < CState::EMainStateAmount ); ASSERT( aState.iMainState == CState::EMainStateGame || aState.iSubState == 0 ); if ( aState.iMainState == CState::EMainStateGame) { ASSERT( aState.iSubState > EGameStateNone ); ASSERT( aState.iSubState < EGameStateAmount ); if ( iState.iMainState != CState::EMainStateGame ) // main state changes also { ASSERT( aState.iSubState == EGameStateNextLevel ); } else // substate change only { if ( aState.iSubState != EGameStateQuit ) // let's skip checking in case of QUIT { // We should have some UML diagrams of these... ASSERT( iState.iSubState != EGameStateNextLevel || aState.iSubState == EGameStateLevelInfo || aState.iSubState == EGameStateOnGoing ); ASSERT( iState.iSubState != EGameStateLevelInfo || aState.iSubState == EGameStateShop || aState.iSubState == EGameStateOnGoing ); ASSERT( iState.iSubState != EGameStateShop || aState.iSubState == EGameStateShop || aState.iSubState == EGameStateOnGoing ); ASSERT( iState.iSubState != EGameStateOnGoing || aState.iSubState == EGameStateStatistics ); ASSERT( iState.iSubState != EGameStateStatistics || aState.iSubState == EGameStateNextLevel || aState.iSubState == EGameStateVictory || aState.iSubState == EGameStateStatistics ); } } } // if (iState==aState) return; bool iMainChange=iState.iMainState!=aState.iMainState; MEMCLEAN(); if (iGUIStates[MainState()]) iGUIStates[MainState()]->ExitSubState(); if (iMainChange) { MEMCLEAN(); if (iGUIStates[MainState()]) iGUIStates[MainState()]->ExitState(); } MEMCLEAN(); iState=aState; iStateChanged=true; if (iMainChange) { MEMCLEAN(); if (iGUIStates[MainState()]) iGUIStates[MainState()]->EnterState(); } MEMCLEAN(); if (iGUIStates[MainState()]) iGUIStates[MainState()]->EnterSubState(); MEMCLEAN(); SELFTEST; }