void bios0x1c(void) {
UINT8 buf[6];
switch(CPU_AH) {
case 0x00: // get system timer
calendar_get(buf);
MEMR_WRITES(CPU_ES, CPU_BX, buf, 6);
break;
case 0x01: // put system timer
MEMR_READS(CPU_ES, CPU_BX, buf, 6);
mem[MEMB_MSW8] = buf[0];
calendar_set(buf);
break;
case 0x02: // set interval timer (single)
SETBIOSMEM16(0x0001c, CPU_BX);
SETBIOSMEM16(0x0001e, CPU_ES);
SETBIOSMEM16(0x0058a, CPU_CX);
iocore_out8(0x77, 0x36);
/* through */
case 0x03: // continue interval timer
iocore_out8(0x71, 0x00);
if (pccore.cpumode & CPUMODE_8MHZ) {
iocore_out8(0x71, 0x4e); // 4MHz
}
else {
iocore_out8(0x71, 0x60); // 5MHz
}
pic.pi[0].imr &= ~(PIC_SYSTEMTIMER);
break;
}
}
static void store_sft(INTRST is, SFTREC sft) {
REG16 off;
REG16 seg;
off = LOADINTELWORD(is->r.w.di);
seg = LOADINTELWORD(is->r.w.es);
MEMR_WRITES(seg, off, sft, sizeof(_SFTREC));
}
static void store_sda_currcds(SDACDS sc) {
REG16 off;
REG16 seg;
if (hostdrv.stat.dosver_major == 3) {
MEMR_WRITES(hostdrv.stat.sda_seg, hostdrv.stat.sda_off,
&sc->ver3.sda, sizeof(sc->ver3.sda));
off = LOADINTELWORD(sc->ver3.sda.cdsptr.off);
seg = LOADINTELWORD(sc->ver3.sda.cdsptr.seg);
MEMR_WRITES(seg, off, &sc->ver3.cds, sizeof(sc->ver3.cds));
}
else {
MEMR_WRITES(hostdrv.stat.sda_seg, hostdrv.stat.sda_off,
&sc->ver4.sda, sizeof(sc->ver4.sda));
off = LOADINTELWORD(sc->ver4.sda.cdsptr.off);
seg = LOADINTELWORD(sc->ver4.sda.cdsptr.seg);
MEMR_WRITES(seg, off, &sc->ver4.cds, sizeof(sc->ver4.cds));
}
}
static REG8 bios1bc_seltrans(REG8 id) {
UINT8 cdb[16];
REG8 ret;
MEMR_READS(CPU_DS, CPU_DX, cdb, 16);
scsiio.reg[SCSICTR_TARGETLUN] = cdb[0];
if ((cdb[1] & 0x0c) == 0x08) { // OUT
MEMR_READS(CPU_ES, CPU_BX, scsiio.data, CPU_CX);
}
ret = scsicmd_transfer(id, cdb + 4);
if ((cdb[1] & 0x0c) == 0x04) { // IN
MEMR_WRITES(CPU_ES, CPU_BX, scsiio.data, CPU_CX);
}
return(ret);
}
static void store_intr_regs(INTRST is) {
MEMR_WRITES(CPU_SS, CPU_BP, &is->r, sizeof(is->r));
}
