static void mhl_msm_connection(struct mhl_tx_ctrl *mhl_ctrl)
{
uint8_t val;
struct i2c_client *client = mhl_ctrl->i2c_handle;
pr_debug("%s: cur st [0x%x]\n", __func__,
mhl_ctrl->cur_state);
if (mhl_ctrl->cur_state == POWER_STATE_D0_MHL) {
/* Already in D0 - MHL power state */
pr_err("%s: cur st not D0\n", __func__);
return;
}
/* spin_lock_irqsave(&mhl_state_lock, flags); */
switch_mode(mhl_ctrl, POWER_STATE_D0_MHL);
/* spin_unlock_irqrestore(&mhl_state_lock, flags); */
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10);
MHL_SII_CBUS_WR(0x07, 0xF2);
/*
* Keep the discovery enabled. Need RGND interrupt
* Possibly chip disables discovery after MHL_EST??
* Need to re-enable here
*/
val = MHL_SII_PAGE3_RD(0x10);
MHL_SII_PAGE3_WR(0x10, val | BIT0);
return;
}
static void mhl_msm_connection(struct mhl_tx_ctrl *mhl_ctrl)
{
uint8_t val;
struct i2c_client *client = mhl_ctrl->i2c_handle;
pr_debug("%s: cur st [0x%x]\n", __func__,
mhl_ctrl->cur_state);
if (mhl_ctrl->cur_state == POWER_STATE_D0_MHL) {
/* Already in D0 - MHL power state */
pr_err("%s: cur st not D0\n", __func__);
return;
}
switch_mode(mhl_ctrl, POWER_STATE_D0_MHL, true);
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10);
MHL_SII_CBUS_WR(0x07, 0xF2);
/*
* Keep the discovery enabled. Need RGND interrupt
* Possibly chip disables discovery after MHL_EST??
* Need to re-enable here
*/
val = MHL_SII_PAGE3_RD(0x10);
MHL_SII_PAGE3_WR(0x10, val | BIT0);
/*
* indicate DCAP_RDY and DCAP_CHG
* to the peer only after
* msm conn has been established
*/
mhl_msc_send_write_stat(mhl_ctrl,
MHL_STATUS_REG_CONNECTED_RDY,
MHL_STATUS_DCAP_RDY);
mhl_msc_send_set_int(mhl_ctrl,
MHL_RCHANGE_INT,
MHL_INT_DCAP_CHG,
MSC_PRIORITY_SEND);
}
static void scdt_st_chg(struct i2c_client *client)
{
uint8_t tmds_cstat;
uint8_t mhl_fifo_status;
/* tmds cstat */
tmds_cstat = MHL_SII_PAGE3_RD(0x0040);
pr_debug("%s: tmds cstat: 0x%02x\n", __func__,
tmds_cstat);
if (!(tmds_cstat & BIT1))
return;
mhl_fifo_status = MHL_SII_REG_NAME_RD(REG_INTR5);
pr_debug("%s: mhl fifo st: 0x%02x\n", __func__,
mhl_fifo_status);
if (mhl_fifo_status & 0x0C) {
MHL_SII_REG_NAME_WR(REG_INTR5, 0x0C);
pr_debug("%s: mhl fifo rst\n", __func__);
MHL_SII_REG_NAME_WR(REG_SRST, 0x94);
MHL_SII_REG_NAME_WR(REG_SRST, 0x84);
}
}