static int i2c_mcux_configure(struct device *dev, u32_t dev_config_raw)
{
I2C_Type *base = DEV_BASE(dev);
const struct i2c_mcux_config *config = DEV_CFG(dev);
union dev_config dev_config = (union dev_config)dev_config_raw;
u32_t clock_freq;
u32_t baudrate;
if (!dev_config.bits.is_master_device) {
return -EINVAL;
}
if (dev_config.bits.use_10_bit_addr) {
return -EINVAL;
}
switch (dev_config.bits.speed) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(100);
break;
case I2C_SPEED_FAST:
baudrate = MHZ(1);
break;
default:
return -EINVAL;
}
clock_freq = CLOCK_GetFreq(config->clock_source);
I2C_MasterSetBaudRate(base, baudrate, clock_freq);
return 0;
}
static int i2c_mcux_configure(struct device *dev, u32_t dev_config_raw)
{
I2C_Type *base = DEV_BASE(dev);
const struct i2c_mcux_config *config = DEV_CFG(dev);
u32_t clock_freq;
u32_t baudrate;
if (!(I2C_MODE_MASTER & dev_config_raw)) {
return -EINVAL;
}
if (I2C_ADDR_10_BITS & dev_config_raw) {
return -EINVAL;
}
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(100);
break;
case I2C_SPEED_FAST:
baudrate = MHZ(1);
break;
default:
return -EINVAL;
}
clock_freq = CLOCK_GetFreq(config->clock_source);
I2C_MasterSetBaudRate(base, baudrate, clock_freq);
return 0;
}
/*
* This function is used to configure various GPT parameters like
* Ctrl : SLPMODE, PEDMODE,
* Mode : Oneshot/Periodic
* Clk : Frequency in at which timer need to run (26Mhz, 1Mhz, 32Khz)
* Callback : Interrupts are enabled for the GPT if callback is provided.
* Arg : Argument to receive when callback is called.
*
* This API should be called after requesting a GPT and could be called any number
* of times before calling gpt_free.
*
* Return:
* GPT_SUCCESS : On success
* GPT_ERR_INVALID_INDEX : If the gpt index provided is invalid
* GPT_ERR_NOT_CONFIGURED : If the GPT is not requested before
*/
int gpt_config(int index, struct gpt_cfg *gc,
gpt_callback gcallback, void *arg)
{
int ret = GPT_SUCCESS;
uint32_t ctrl_reg;
unsigned long flags;
spin_lock_irqsave(&gpt_lock, flags);
if ((index < 0) || (index >= BCM_NUM_GPT)) {
pr_err("Invalid index %d\n", index);
ret = GPT_ERR_INVALID_INDEX;
goto err;
}
if (!(gpt.gpt_desc[index].flag & GPT_ASSIGNED)) {
pr_err("Trying to configure the gpt before request\n");
ret = GPT_ERR_NOT_CONFIGURED;
goto err;
}
ctrl_reg = readl(gpt.base_config.base_addr + GPT_CSR(index));
ctrl_reg |= GPT_CSR_TIMER_PWRON;
if (gc->gclk >= MHZ(26)) {
ctrl_reg |= GPT_CSR_CLKSEL;
ctrl_reg &= ~GPT_CSR_CLKSEL1;
} else if (gc->gclk >= MHZ(1)) {
ctrl_reg &= ~GPT_CSR_CLKSEL;
ctrl_reg |= GPT_CSR_CLKSEL1;
} else {
ctrl_reg &= ~(GPT_CSR_CLKSEL1 | GPT_CSR_CLKSEL);
}
ctrl_reg |= gc->gctrl;
if ((gpt.gpt_desc[index].gcallback = gcallback) != NULL)
ctrl_reg |= GPT_CSR_INT_EN | GPT_CSR_INT_FLAG;
writel(ctrl_reg, gpt.base_config.base_addr + GPT_CSR(index));
gpt.gpt_desc[index].arg = arg;
gpt.gpt_desc[index].gmode = gc->gmode;
gpt.gpt_desc[index].flag |= GPT_CONFIGURED;
err:
spin_unlock_irqrestore(&gpt_lock, flags);
return ret;
}
/**
* \brief Receive data from an EEPROM chip
*
* This receives data from an EEPROM using SPI BUS protocol
* \param[out] sg_serial Sansgrid data received
* \param[out] size Size of data received
* \param[in] ts Stub configuration to use
*/
int eepromReceive(SansgridSerial **sg_serial, uint32_t *size, TalkStub *ts) {
// Read from an EEPROM chip over SPI
int fd;
uint8_t buffer[sizeof(SansgridSerial)];
uint8_t newbuffer[sizeof(SansgridSerial)+3];
int i;
mark_point();
if (!ts->valid_read)
return 1;
mark_point();
if (!eeprom_lock_initd) {
pthread_mutex_init(&eeprom_lock, NULL);
eeprom_lock_initd = 1;
}
mark_point();
mark_point();
*size = sizeof(SansgridSerial);
mark_point();
sem_wait(&ts->writelock);
if (ts->eeprom_address == -1) {
return -1;
}
mark_point();
pthread_mutex_lock(&eeprom_lock);
// Set up reading from EEPROM
mark_point();
if ((fd = wiringPiSPISetup (0, MHZ(SPI_SPEED_MHZ))) < 0)
fprintf(stderr, "SPI Setup failed: %s\n", strerror (errno));
// Prepend command and address to buffer
newbuffer[0] = READ;
newbuffer[1] = ts->eeprom_address >> 8;
newbuffer[2] = ts->eeprom_address & 0xff;
// Send command/address, read data
wiringPiSPIDataRW(0, newbuffer, (*size)+3);
// shift the command and address out of buffer
for (i=0; i<*size; i++)
buffer[i] = newbuffer[i+3];
*sg_serial = (SansgridSerial*)malloc(sizeof(SansgridSerial));
memcpy(*sg_serial, buffer, sizeof(SansgridSerial));
// finish up
close(fd);
pthread_mutex_unlock(&eeprom_lock);
sem_post(&ts->readlock);
return 0;
}
static int i2c_imx_configure(struct device *dev, u32_t dev_config_raw)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_imx_data *data = DEV_DATA(dev);
struct i2c_master_transfer *transfer = &data->transfer;
u32_t baudrate;
if (!(I2C_MODE_MASTER & dev_config_raw)) {
return -EINVAL;
}
if (I2C_ADDR_10_BITS & dev_config_raw) {
return -EINVAL;
}
/* Initialize I2C state structure content. */
transfer->txBuff = 0;
transfer->rxBuff = 0;
transfer->cmdSize = 0U;
transfer->txSize = 0U;
transfer->rxSize = 0U;
transfer->isBusy = false;
transfer->currentDir = i2cDirectionReceive;
transfer->currentMode = i2cModeSlave;
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(100);
break;
case I2C_SPEED_FAST:
baudrate = MHZ(1);
break;
default:
return -EINVAL;
}
/* Setup I2C init structure. */
i2c_init_config_t i2cInitConfig = {
.baudRate = baudrate,
.slaveAddress = 0x00
};
i2cInitConfig.clockRate = get_i2c_clock_freq(base);
I2C_Init(base, &i2cInitConfig);
I2C_Enable(base);
return 0;
}
static int i2c_imx_send_addr(struct device *dev, u16_t addr, u8_t flags)
{
u8_t byte0 = addr << 1;
byte0 |= (flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
return i2c_imx_write(dev, &byte0, 1);
}
void dt_fixup_cpu_clocks(u32 cpu, u32 tb, u32 bus)
{
void *devp = NULL;
printf("CPU clock-frequency <- 0x%x (%dMHz)\n\r", cpu, MHZ(cpu));
printf("CPU timebase-frequency <- 0x%x (%dMHz)\n\r", tb, MHZ(tb));
if (bus > 0)
printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus));
while ((devp = find_node_by_devtype(devp, "cpu"))) {
setprop_val(devp, "clock-frequency", cpu);
setprop_val(devp, "timebase-frequency", tb);
if (bus > 0)
setprop_val(devp, "bus-frequency", bus);
}
timebase_period_ns = 1000000000 / tb;
}
void dt_fixup_clock(const char *path, u32 freq)
{
void *devp = finddevice(path);
if (devp) {
printf("%s: clock-frequency <- %x (%dMHz)\n\r", path, freq, MHZ(freq));
setprop_val(devp, "clock-frequency", freq);
}
}
void TFT_ILI9325::assign(SPI_PORT_T port, PIN_NAME_T CS, PIN_NAME_T BL) {
pinBL.assign(BL);
pinBL.output(NOT_OPEN);
spi.assign(port, CS);
spi.format(SPI_DATABIT_8, SPI_MODE_3);
spi.frequency(MHZ(12));
spi.begin();
}
void
cpu_startup()
{
platid_t cpu;
int cpuclock, pclock;
cpuclock = sh_clock_get_cpuclock();
pclock = sh_clock_get_pclock();
sh_startup();
memcpy(&cpu, &platid, sizeof(platid_t));
cpu.dw.dw1 = 0; /* clear platform */
sprintf(cpu_model, "[%s] %s", platid_name(&platid), platid_name(&cpu));
#define MHZ(x) ((x) / 1000000), (((x) % 1000000) / 1000)
printf("%s %d.%02d MHz PCLOCK %d.%02d MHz\n", cpu_model,
MHZ(cpuclock), MHZ(pclock));
}
static void setupHardware(void) {
// Se configuran los perifericos por defecto
SystemInit();
// Se inicializa las task de comunicaciones
// taskPcCommunicationInit();
semSdCardAccess = xSemaphoreCreateMutex();
xSemaphoreGive(semSdCardAccess);
// SD Card
LPC_GPIO0->FIODIR |= 1<<22;
LPC_GPIO0->FIOCLR |= 1<<22;
LPC_SC->PCLKSEL0 &= ~(3<<2);
LPC_SC->PCLKSEL0 |= 1<<2;
/*
* Default values for the SPI clock
* Use 400 kHz during init and 1 MHz during data transfer
*
* These values are believed to be reasonably safe values.
*/
SetSPIClocks(KHZ(400), MHZ(1));
f_mount(0, &fs);
LPC_GPIO2->FIODIR |= (1<<0); // red
LPC_GPIO2->FIODIR |= (1<<1); // green
LPC_GPIO2->FIOCLR = (1<<0); // red
LPC_GPIO2->FIOCLR = (1<<1); // green
RTC_Init(LPC_RTC);
/* Enable rtc (starts increase the tick counter and second counter register) */
RTC_ResetClockTickCounter(LPC_RTC);
RTC_Cmd(LPC_RTC, ENABLE);
RTC_CalibCounterCmd(LPC_RTC, DISABLE);
/* Set current time for RTC */
// Current time is 8:00:00PM, 2009-04-24
RTC_SetTime (LPC_RTC, RTC_TIMETYPE_SECOND, 0);
RTC_SetTime (LPC_RTC, RTC_TIMETYPE_MINUTE, 0);
RTC_SetTime (LPC_RTC, RTC_TIMETYPE_HOUR, 0);
RTC_SetTime (LPC_RTC, RTC_TIMETYPE_MONTH, 12);
RTC_SetTime (LPC_RTC, RTC_TIMETYPE_YEAR, 2012);
RTC_SetTime (LPC_RTC, RTC_TIMETYPE_DAYOFMONTH, 19);
/* Set ALARM time for second */
RTC_SetAlarmTime (LPC_RTC, RTC_TIMETYPE_SECOND, 10);
}
/**
* \brief Send data to an EEPROM chip
*
* This sends data to an EEPROM using SPI BUS protocol
* \param[in] buffer Data to send
* \param[in] address EEPROM address to write to
* \param[in] size Number of bytes to write
* \returns
* On error, returns -1. \n
* Otherwise returns 0
*/
static int eepromSendData(uint8_t *buffer, uint16_t address, int size) {
// Set up SPI
int i;
int fd;
// only 32 bytes can be written at a time; see below
int bounded_size = (size > 32 ? 32 : size);
// prepend the command and address to the data
uint8_t newbuffer[bounded_size+3];
struct timespec required, remaining;
int excode;
if ((fd = wiringPiSPISetup (0, MHZ(SPI_SPEED_MHZ))) < 0)
fprintf(stderr, "SPI Setup failed: %s\n", strerror (errno));
// Have to make room for command and address
for (i=3; i<bounded_size+3; i++)
newbuffer[i] = buffer[i-3];
// Allow writes to the EEPROM
// Has to be done before every write cycle
newbuffer[0] = WRITE_ENABLE;
write(fd, newbuffer, 1);
// Write to specified address
newbuffer[0] = WRITE;
newbuffer[1] = address >> 8;
newbuffer[2] = address & 0xff;
//printf("Writing to %x\n", address);
write(fd, newbuffer, bounded_size+3);
close(fd);
// Wait for the write to cycle
required.tv_sec = 0;
required.tv_nsec = 1000L*WRITE_CYCLE;
do {
if ((excode = nanosleep(&required, &remaining)) == -1) {
if (errno == EINTR)
required.tv_nsec = remaining.tv_nsec;
else
return -1;
}
} while (excode);
if (size > 32) {
// Only one page (of 32 bytes) can be written
// at a time. If more than 32 bytes are being written,
// break the line into multiple pages
return eepromSendData(&buffer[32], address+0x0020, size-32);
}
return 0;
}
/*
* Charge Pump : Computed based on Ptotal
* See datasheet for more info.
*/
STATIC uint8
cy22150_charge_pump(int val)
{
uint8 tmp;
/* Convert from MHz if required */
if (val > MHZ(1)) {
val /= MHZ(1);
}
if (val >= 16 && val <= 44) {
tmp = 0;
} else if (val >= 45 && val <= 479) {
tmp = 1;
} else if (val >= 480 && val <= 639) {
tmp = 2;
} else if (val >= 640 && val <= 799) {
tmp = 3;
} else if (val >= 800 && val <= 1023) {
tmp = 4;
} else {
tmp = 0;
}
return tmp;
}
static void platform_fixups(void)
{
void *node;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_addresses(bd.bi_enetaddr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 16, bd.bi_busfreq);
node = finddevice("/soc/cpm/brg");
if (node) {
printf("BRG clock-frequency <- 0x%x (%dMHz)\r\n",
bd.bi_busfreq, MHZ(bd.bi_busfreq));
setprop(node, "clock-frequency", &bd.bi_busfreq, 4);
}
}
static void init(struct output *o, int default_spl)
{
struct context *ctx;
struct probe *probe;
GSList *l;
uint64_t samplerate;
int num_probes;
ctx = malloc(sizeof(struct context));
o->internal = ctx;
ctx->num_enabled_probes = 0;
for(l = o->device->probes; l; l = l->next) {
probe = l->data;
if(probe->enabled)
ctx->probelist[ctx->num_enabled_probes++] = probe->name;
}
ctx->probelist[ctx->num_enabled_probes] = 0;
ctx->unitsize = (ctx->num_enabled_probes + 7) / 8;
ctx->spl_cnt = 0;
if(o->param && o->param[0])
ctx->samples_per_line = strtoul(o->param, NULL, 10);
else
ctx->samples_per_line = default_spl;
ctx->header = malloc(512);
num_probes = g_slist_length(o->device->probes);
samplerate = *((uint64_t *) o->device->plugin->get_device_info(o->device->plugin_index, DI_CUR_SAMPLE_RATE));
snprintf(ctx->header, 512, "Acquisition with %d/%d probes at ", ctx->num_enabled_probes, num_probes);
if(samplerate >= GHZ(1))
snprintf(ctx->header + strlen(ctx->header), 512, "%"PRId64" GHz", samplerate / 1000000000);
else if(samplerate >= MHZ(1))
snprintf(ctx->header + strlen(ctx->header), 512, "%"PRId64" MHz", samplerate / 1000000);
else if(samplerate >= KHZ(1))
snprintf(ctx->header + strlen(ctx->header), 512, "%"PRId64" KHz", samplerate / 1000);
else
snprintf(ctx->header + strlen(ctx->header), 512, "%"PRId64" Hz", samplerate);
snprintf(ctx->header + strlen(ctx->header), 512, "\n");
ctx->linebuf_len = ctx->samples_per_line * 2;
ctx->linebuf = calloc(1, num_probes * ctx->linebuf_len);
ctx->linevalues = calloc(1, num_probes);
}
STATIC int
cy22150_ioctl(int unit, int devno,
int opcode, void *data, int len)
{
#ifdef COMPILER_HAS_DOUBLE
double clk, qt;
#else
int qt;
#endif
int iclk, P0, ip, iq;
uint8 tmp, lf, saddr = soc_i2c_addr(unit, devno);
if ( I2C_XPLL_SET_PCI == opcode ) {
/* Not implemented, but report success */
} else if ( I2C_XPLL_GET_PCI == opcode ) {
/* Not implemented, but report success */
} else if ( I2C_XPLL_SET_CORE == opcode ) {
#ifdef COMPILER_HAS_DOUBLE
clk = *((double *)data);
/* Convert from MHz if required */
if( clk < MHZ(1))
clk *= MHZ(1);
/* Setup new core clock */
iclk = (int) clk;
#else
iclk = *((int *)data);
#endif
/* Compute actual frequency in MHz */
iclk = (CY22150_DIV_CORE * iclk) / MHZ(1);
/* This is set only on an odd clock freq */
P0 = iclk % 2;
/* Compute Qt and convert to byte value (in MHz)*/
qt = CY22150_REF_CLK - MHZ(2);
qt = qt / MHZ(1);
/* Compute P/Q (integer format) */
ip = ((iclk - P0) / 2) - 4;
iq = (int) qt;
/* Bit 8 of Q (0x42) is PNot */
iq |= (P0 << 8);
/* Compute Charge Pump setting */
lf = cy22150_charge_pump(iclk);
/* Bits 7-5 fixed at 110b */
tmp = 0xC0;
/* Add upper P bits */
tmp |= (ip >> 8);
/* Add Charge Pump bits */
tmp |= (lf << 2);
/* Configure new clock setting */
soc_i2c_write_byte_data(unit, saddr, 0x40, tmp);
soc_i2c_write_byte_data(unit, saddr, 0x41, (uint8)ip);
soc_i2c_write_byte_data(unit, saddr, 0x42, (uint8)iq);
} else if ( I2C_XPLL_GET_CORE == opcode) {
/* simple configuration and streaming */
int main (int argc, char **argv){
int child=fork();
if (child==-1) {DieWithError("socket() failed");}
//Father code
else if (child==0){
pause();
// sleep(5); //Child run first
// Streaming devices
struct iio_device *rx;
// Stream configurations
struct stream_cfg rxcfg;
// Listen to ctrl+c and assert
signal(SIGINT, shutdowniio);
// RX stream config
rxcfg.bw_hz = MHZ(28); // 2 MHz rf bandwidth //200KHz-56MHz Channel bandwidths
rxcfg.fs_hz = MHZ(61.44); // 2 MS/s rx sample rate // 61.44
rxcfg.lo_hz = GHZ(2.5); // 2.5 GHz rf frequency //70MHz -6 GHz Local-oscilator
rxcfg.rfport = "A_BALANCED"; // port A (select for rf freq.)
if(verbose==1) printf("* Acquiring IIO context\n");
assert((ctx = iio_create_default_context()) && "No context");
assert(iio_context_get_devices_count(ctx) > 0 && "No devices");
if(verbose==1) printf("* Acquiring AD9361 streaming devices\n");
assert(get_ad9361_stream_dev(ctx, RX, &rx) && "No rx dev found");
if(verbose==1) printf("* Configuring AD9361 for streaming\n");
assert(cfg_ad9361_streaming_ch(ctx, &rxcfg, RX, 0) && "RX port 0 not found");
if(verbose==1) printf("* Init AD9361 IIO streaming channels\n");
assert(get_ad9361_stream_ch(ctx, RX, rx, 0, &rx0_i) && "RX chan i not found");
assert(get_ad9361_stream_ch(ctx, RX, rx, 1, &rx0_q) && "RX chan q not found");
if(verbose==1) printf("* Enabling IIO streaming channels\n");
iio_channel_enable(rx0_i);
iio_channel_enable(rx0_q);
if(verbose==1) printf("* Creating non-cyclic buff with 1 MiS\n");
rxbuf = iio_device_create_buffer(rx, BUFF_SIZE/4, false);
struct sockaddr_in serv,serv2; /* Echo server address */
printf("* Server conection(192.168.0.229:50705)*");
/* Construct the server address structure */
memset(&serv, 0, sizeof(serv)); /* Zero out structure */
serv.sin_family = AF_INET; /* Internet addr family */
serv.sin_addr.s_addr = inet_addr("192.168.0.229"); /* Server IP address */
serv.sin_port = htons(50705); /* Server port */
memset(&serv2, 0, sizeof(serv2)); /* Zero out structure */
serv2.sin_family = AF_INET; /* Internet addr family */
serv2.sin_addr.s_addr = inet_addr("192.168.0.229"); /* Server IP address */
serv2.sin_port = htons(50705); /* Server port */
/* Create a datagram/UDP socket */
if ((sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0)
DieWithError("socket() failed");
if ((sock2 = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0)
DieWithError("socket2() failed");
/* Connecting to the server */
if (connect(sock,(struct sockaddr *)&serv, sizeof(serv)) < 0) DieWithError("socket() failed");
if (connect(sock2,(struct sockaddr *)&serv2, sizeof(serv2)) < 0) DieWithError("socket() failed");
/* Sincronization */
printf("\n* Sended AK *");
if (sendto(sock, "AK", 2, 0, (struct sockaddr *)&serv, sizeof(serv)) != 2)
DieWithError("sendto() sent a different number of bytes than expected");
fromSize = sizeof(fromAddr);
rsplen = recvfrom(sock, buff_from_n, 1024*32, 0,(struct sockaddr *) &fromAddr, &fromSize);
if(rsplen!= 2){ DieWithError("recvfrom() failed");}
if (serv.sin_addr.s_addr != fromAddr.sin_addr.s_addr) {printf("Unknown client.\n"); exit(1);}
buff_from_n[rsplen] = '\0';
printf("\n* Received %s *\n", (char*)buff_from_n);
if(verbose==1) printf("* Starting IO streaming ");
int status;
ssize_t nbytes_rx=0;
void *p_dat ,*p_end;
pthread_t tid,tid2;
//Fill buffer from antena
nbytes_rx = iio_buffer_refill(rxbuf);
if (nbytes_rx < 0) { printf("Error refilling buf %d\n",(int) nbytes_rx); shutdowniio(0); }
p_end = iio_buffer_end(rxbuf);
p_dat = iio_buffer_first(rxbuf, rx0_i);
memcpy (buff_from_a, p_dat, (&p_end-&p_dat));
printf("\n* Ready for fast transfer *");
sec_begin= time(NULL);
while(sec_elapsed<10)
{
sec_end=time(NULL);
sec_elapsed=sec_end-sec_begin;
//Send data to network
memcpy (buff_from_a, p_dat, (&p_end-&p_dat));
if(pthread_create(&tid, NULL, send_msg1,(int*)sock)!=0){
printf ("\nPthread_create");exit(1);}
// if(pthread_create(&tid2, NULL, send_msg2,(int*)sock)!=0){
// printf ("\nPthread_create");exit(1);}
//Fill buffer from antena
nbytes_rx = iio_buffer_refill(rxbuf);
if (nbytes_rx < 0) { printf("Error refilling buf %d\n",(int) nbytes_rx); shutdowniio(0); }
p_end = iio_buffer_end(rxbuf);
p_dat = iio_buffer_first(rxbuf, rx0_i);
count=count+nbytes_rx;
//Syncronizing
if(pthread_join(tid ,(void**)&status)!=0){printf ("Pthread_join");exit(1);}
// if(pthread_join(tid2,(void**)&status)!=0){printf ("Pthread_join");exit(1);}
}
printf("\n\tTime elapsed: %lus \n\tAntena recived %llu MB\tDebit %llu Mb/sec ",
sec_elapsed, count/1024/1024, count/sec_elapsed/1024/1024);
printf("\n\tSocket sended %lld Mb \n",sendcount/1024/1024);
//printf("\nBytes sendeded %llu ",summ);
close(sock);
close(tcpsock);
return 0;
}//End Parent
//Child programm
else if (child!=0){
//pause();
// Listen to ctrl+c and assert
signal(SIGINT, shutdowniio);
struct iio_device *tx; // Streaming devices
struct stream_cfg txcfg; // Stream configurations
// TX stream config
txcfg.bw_hz = MHZ(28); // 1.5 MHz rf bandwidth
txcfg.fs_hz = MHZ(61.44); // 2 MS/s tx sample rate
txcfg.lo_hz = GHZ(2.5); // 2.5 GHz rf frequency
txcfg.rfport = "A"; // port A (select for rf freq.)
if(verbose==1) printf("\t\t\t\t\t* Acquiring IIO context\n");
assert((ctx = iio_create_default_context()) && "No context");
assert(iio_context_get_devices_count(ctx) > 0 && "No devices");
if(verbose==1) printf("\t\t\t\t\t* Acquiring AD9361 streaming devices\n");
assert(get_ad9361_stream_dev(ctx, TX, &tx) && "No tx dev found");
if(verbose==1) printf("\t\t\t\t\t* Configuring AD9361 for streaming\n");
assert(cfg_ad9361_streaming_ch(ctx, &txcfg, TX, 0) && "TX port 0 not found");
if(verbose==1) printf("\t\t\t\t\t* Initializing AD9361 IIO streaming channels\n");
assert(get_ad9361_stream_ch(ctx, TX, tx, 0, &tx0_i) && "TX chan i not found");
assert(get_ad9361_stream_ch(ctx, TX, tx, 1, &tx0_q) && "TX chan q not found");
if(verbose==1) printf("\t\t\t\t\t* Enabling IIO streaming channels\n");
iio_channel_enable(tx0_i);
iio_channel_enable(tx0_q);
if(verbose==1) printf("\t\t\t\t\t* Creating non-cyclic IIO buffers with 1 MiS\n");
txbuf = iio_device_create_buffer(tx, BUFF_SIZE/4, false);
printf("\t\t\t\t\t* Server conection*\n");
struct sockaddr_in serv; /* Echo server address */
/* Construct the server address structure */
memset(&serv, 0, sizeof(serv)); /* Zero out structure */
serv.sin_family = AF_INET; /* Internet addr family */
serv.sin_addr.s_addr = inet_addr("192.168.0.229"); /* Server IP address */
serv.sin_port = htons(50707); /* Server port */
/* Create a datagram/UDP socket */
if ((sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0) DieWithError("socket() failed");
/* Connecting to the server */
//if (connect(sock,(struct sockaddr *)&serv, sizeof(serv)) < 0) DieWithError("socket() failed");
//pause();
/* Sincronization */
printf("\t\t\t\t\t* Sended AK *\n");
if (sendto(sock, "AK", 2, 0, (struct sockaddr *)&serv, sizeof(serv)) != 2)
DieWithError("sendto() sent a different number of bytes than expected");
fromSize = sizeof(fromAddr);
rsplen = recvfrom(sock, buff_from_n, 1024*32, 0,(struct sockaddr *) &fromAddr, &fromSize);
if(rsplen!= 2){ DieWithError("recvfrom() failed");}
if (serv.sin_addr.s_addr != fromAddr.sin_addr.s_addr) {printf("Unknown client.\n"); exit(1); }
buff_from_n[rsplen] = '\0';
printf("\t\t\t\t\t* Received %s *", (char*)buff_from_n);
int status;
ssize_t nbytes_tx=0;
void *t_dat,*t_end;
pthread_t tid3;
setpriority(PRIO_PROCESS, 0, -20);
//Fill buff_from_n from network
if(pthread_create(&tid3, NULL, recv_msg,(int*)sock)!=0){
printf ("\nPthread_create\n");exit(1);}
if(pthread_join(tid3,(void**)&status)!=0){printf ("Pthread_join");exit(1);}
//Bug push after in the third try
nbytes_tx = iio_buffer_push(txbuf);
nbytes_tx = iio_buffer_push(txbuf);
printf("\n\t\t\t\t\tReciving........ ");
while(1)
{
//Fill TXbuffer
t_end = iio_buffer_end(txbuf);
t_dat = iio_buffer_first(txbuf, tx0_i);
memcpy(t_dat,buff_from_n, (1024*1024));
nbytes_tx = iio_buffer_push(txbuf);
//Fill buff_from_n from network
if(pthread_create(&tid3, NULL, recv_msg,(int*)sock)!=0){printf ("\nPthread_create\n");exit(1);}
// Send buffer to antena
if (nbytes_tx < 0) { printf("Error pushing buf %d\n", (int) nbytes_tx); shutdowniio(0); }
count2=count2+nbytes_tx;
if(pthread_join(tid3,(void**)&status)!=0){printf ("Pthread_join");exit(1);}
if(status==1){ break; }
}
t_end = iio_buffer_end(txbuf);
t_dat = iio_buffer_first(txbuf, tx0_i);
memcpy(t_dat,buff_from_n, (&t_end-&t_dat));
nbytes_tx = iio_buffer_push(txbuf);
if (nbytes_tx < 0) { printf("Error pushing buf %d\n", (int) nbytes_tx); shutdowniio(0); }
count2=count2+nbytes_tx;
printf("\n\t\t\t\t\tRecived from net %llu MB",recvcount/1024/1024);
printf("\tSended to antena %lld Mb \n",count2/1024/1024);
}
return 0;
}//End of the life
static int new_pc_clk_set_rate(unsigned id, unsigned rate)
{
// Cotulla: I am too lazy...
#define MHZ(x) ((x) * 1000 * 1000)
#define KHZ(x) ((x) * 1000)
unsigned clk = -1;
unsigned speed = 0;
switch (id)
{
case UART1DM_CLK:
if (rate > 58982400) speed = 14;
else if (rate > 56000000) speed = 13;
else if (rate > 54613300) speed = 12;
else if (rate > 51200000) speed = 11;
else if (rate > 46400000) speed = 10;
else if (rate > 48000000) speed = 9;
else if (rate > 40000000) speed = 8;
else if (rate > 32000000) speed = 7;
else if (rate > 24000000) speed = 6;
else if (rate > 19200000) speed = 5;
else if (rate > 16000000) speed = 4;
else if (rate > 14745600) speed = 3;
else if (rate > 7372800) speed = 2;
else if (rate > 3686400) speed = 1;
else speed = 0;
clk = 112;
break;
case UART2DM_CLK:
if (rate > 58982400) speed = 14;
else if (rate > 56000000) speed = 13;
else if (rate > 54613300) speed = 12;
else if (rate > 51200000) speed = 11;
else if (rate > 46400000) speed = 10;
else if (rate > 48000000) speed = 9;
else if (rate > 40000000) speed = 8;
else if (rate > 32000000) speed = 7;
else if (rate > 24000000) speed = 6;
else if (rate > 19200000) speed = 5;
else if (rate > 16000000) speed = 4;
else if (rate > 14745600) speed = 3;
else if (rate > 7372800) speed = 2;
else if (rate > 3686400) speed = 1;
else speed = 0;
clk = 114;
break;
/*
case VFE_MDC_CLK:
if (rate == 96000000) speed = 37;
else if (rate == 48000000) speed = 32;
else if (rate == 24000000) speed = 22;
else if (rate == 12000000) speed = 14;
else if (rate == 6000000) speed = 6;
else if (rate == 3000000) speed = 1;
else
{
printk("wrong MDC clock %d\n", rate);
return 0;
}
clk = 40;
break;
case VFE_CLK:
if (rate == 36000000) speed = 1;
else if (rate == 48000000) speed = 2;
else if (rate == 64000000) speed = 3;
else if (rate == 78000000) speed = 4;
else if (rate == 96000000) speed = 5;
else
{
printk("wrong clock %d\n", rate);
return 0;
}
clk = 41;
break;
case SPI_CLK:
if (rate > 15360000) speed = 5;
else if (rate > 9600000) speed = 4;
else if (rate > 4800000) speed = 3;
else if (rate > 960000) speed = 2;
else speed = 1;
clk = 95;
break;
*/
case SDC1_CLK:
if (rate > MHZ(40)) speed = 7;
else if (rate > MHZ(25)) speed = 6;
else if (rate > MHZ(20)) speed = 5;
else if (rate > MHZ(17)) speed = 4;
else if (rate > MHZ(16)) speed = 3;
else if (rate > KHZ(400))speed = 2;
else if (rate > KHZ(144))speed = 1;
else speed = 0;
clk = 93;
break;
case SDC2_CLK:
if (rate > MHZ(40)) speed = 7;
else if (rate > MHZ(25)) speed = 6;
else if (rate > MHZ(20)) speed = 5;
else if (rate > MHZ(17)) speed = 4;
else if (rate > MHZ(16)) speed = 3;
else if (rate > KHZ(400))speed = 2;
else if (rate > KHZ(144))speed = 1;
else speed = 0;
clk = 94;
break;
#undef MHZ
#undef KHZ
// both none
case SDC1_PCLK:
case SDC2_PCLK:
return 0;
break;
default:
return -1;
}
#ifdef ENABLE_CLOCK_INFO
printk("clk_rate %d : %d\n", clk, speed);
#endif
// msm_proc_comm(PCOM_CLK_REGIME_SEC_SEL_SPEED, &clk, &speed);
return 0;
}
GSList *usb_devices = NULL;
/* since we can't keep track of a Saleae Logic device after upgrading the
* firmware -- it re-enumerates into a different device address after the
* upgrade -- this is like a global lock. No device will open until a proper
* delay after the last device was upgraded.
*/
GTimeVal firmware_updated = {0};
libusb_context *usb_context = NULL;
uint64_t supported_sample_rates[] = {
KHZ(200),
KHZ(250),
KHZ(500),
MHZ(1),
MHZ(2),
MHZ(4),
MHZ(8),
MHZ(12),
MHZ(16),
MHZ(24),
0
};
/* TODO: all of these should go in a device-specific struct */
uint64_t cur_sample_rate = 0;
uint64_t limit_samples = 0;
uint8_t probe_mask = 0, \
trigger_mask[NUM_TRIGGER_STAGES] = {0}, \
trigger_value[NUM_TRIGGER_STAGES] = {0}, \
/*
* Hardware initialization of the I2C controller
* @param c controller data structure
* @returns 0->success, <0->error code
*/
static int i2c_stm32_hw_init(struct i2c_stm32 *c)
{
unsigned int v;
int ret = 0;
/*
* First, figure out if we are able to configure the clocks
* If not, we want to bail out without enabling enything.
*/
if (c->i2c_clk != 100000) {
dev_err(&c->dev->dev, "bus clock %d not supported\n",
c->i2c_clk);
ret = -ENXIO;
goto Done;
}
/*
* Reset the I2C controller and then bring it out of reset.
* Enable the I2C controller clock.
*/
if (c->bus == 0) { /* I2C1 */
v = readl(&STM32_RCC->apb1rstr);
writel(v | RCC_APB1RSTR_I2C1, &STM32_RCC->apb1rstr);
writel(v & ~RCC_APB1RSTR_I2C1, &STM32_RCC->apb1rstr);
v = readl(&STM32_RCC->apb1enr);
writel(v | RCC_APB1ENR_I2C1, &STM32_RCC->apb1enr);
}
else if (c->bus == 1) { /* I2C2 */
v = readl(&STM32_RCC->apb1rstr);
writel(v | RCC_APB1RSTR_I2C2, &STM32_RCC->apb1rstr);
writel(v & ~RCC_APB1RSTR_I2C2, &STM32_RCC->apb1rstr);
v = readl(&STM32_RCC->apb1enr);
writel(v | RCC_APB1ENR_I2C2, &STM32_RCC->apb1enr);
}
else if (c->bus == 2) { /* I2C3 */
v = readl(&STM32_RCC->apb1rstr);
writel(v | RCC_APB1RSTR_I2C3, &STM32_RCC->apb1rstr);
writel(v & ~RCC_APB1RSTR_I2C3, &STM32_RCC->apb1rstr);
v = readl(&STM32_RCC->apb1enr);
writel(v | RCC_APB1ENR_I2C3, &STM32_RCC->apb1enr);
}
/*
* Reset the controller to clear possible errors or locks
*/
writel(v | I2C_STM32_CR1_SWRST, &I2C_STM32(c)->cr1);
writel(v & ~I2C_STM32_CR1_SWRST, &I2C_STM32(c)->cr1);
/*
* Set the clocks.
* The following is valid only for Standard Mode (100Khz).
*/
v = c->ref_clk / MHZ(1);
writel(I2C_STM32_CR2_FREQ(v), &I2C_STM32(c)->cr2);
writel(I2C_STM32_TRISE_TRISE(v + 1), &I2C_STM32(c)->trise);
v = c->ref_clk / (c->i2c_clk << 1);
v = v < 0x04 ? 0x04 : v;
writel(I2C_STM32_CCR_CCR(v), &I2C_STM32(c)->ccr);
/*
* Enable hardware interrupts, including for error conditions
*/
v = readl(&I2C_STM32(c)->cr2);
writel(v |
I2C_STM32_CR2_ITBUFEN |
I2C_STM32_CR2_ITEVTEN |
I2C_STM32_CR2_ITERREN, &I2C_STM32(c)->cr2);
/*
* Enable the I2C controller
*/
v = 0;
writel(v | I2C_STM32_CR1_PE, &I2C_STM32(c)->cr1);
Done:
d_printk(2, "bus=%d,"
"cr1=0x%x,cr2=0x%x,sr1=0x%x,ccr=0x%x,trise=0x%x,ret=%d\n",
c->bus,
!ret ? readl(&I2C_STM32(c)->cr1) : 0,
!ret ? readl(&I2C_STM32(c)->cr2) : 0,
!ret ? readl(&I2C_STM32(c)->sr1) : 0,
!ret ? readl(&I2C_STM32(c)->ccr) : 0,
!ret ? readl(&I2C_STM32(c)->trise) : 0, ret);
return ret;
}
void e4k_benchmark(void)
{
uint32_t freq, gap_start = 0, gap_end = 0;
uint32_t range_start = 0, range_end = 0;
fprintf(stderr, "Benchmarking E4000 PLL...\n");
/* find tuner range start */
for (freq = MHZ(70); freq > MHZ(1); freq -= MHZ(1)) {
if (rtlsdr_set_center_freq(dev, freq) < 0) {
range_start = freq;
break;
}
}
/* find tuner range end */
for (freq = MHZ(2000); freq < MHZ(2300UL); freq += MHZ(1)) {
if (rtlsdr_set_center_freq(dev, freq) < 0) {
range_end = freq;
break;
}
}
/* find start of L-band gap */
for (freq = MHZ(1000); freq < MHZ(1300); freq += MHZ(1)) {
if (rtlsdr_set_center_freq(dev, freq) < 0) {
gap_start = freq;
break;
}
}
/* find end of L-band gap */
for (freq = MHZ(1300); freq > MHZ(1000); freq -= MHZ(1)) {
if (rtlsdr_set_center_freq(dev, freq) < 0) {
gap_end = freq;
break;
}
}
fprintf(stderr, "E4K range: %i to %i MHz\n",
range_start/MHZ(1) + 1, range_end/MHZ(1) - 1);
fprintf(stderr, "E4K L-band gap: %i to %i MHz\n",
gap_start/MHZ(1), gap_end/MHZ(1));
}
/* simple configuration and streaming */
int main (int argc, char **argv)
{
// Streaming devices
struct iio_device *tx;
struct iio_device *rx;
// RX and TX sample counters
size_t nrx = 0;
size_t ntx = 0;
// Stream configurations
struct stream_cfg rxcfg;
struct stream_cfg txcfg;
// Listen to ctrl+c and assert
signal(SIGINT, handle_sig);
// RX stream config
rxcfg.bw_hz = MHZ(2); // 2 MHz rf bandwidth
rxcfg.fs_hz = MHZ(2.5); // 2.5 MS/s rx sample rate
rxcfg.lo_hz = GHZ(2.5); // 2.5 GHz rf frequency
rxcfg.rfport = "A_BALANCED"; // port A (select for rf freq.)
// TX stream config
txcfg.bw_hz = MHZ(1.5); // 1.5 MHz rf bandwidth
txcfg.fs_hz = MHZ(2.5); // 2.5 MS/s tx sample rate
txcfg.lo_hz = GHZ(2.5); // 2.5 GHz rf frequency
txcfg.rfport = "A"; // port A (select for rf freq.)
printf("* Acquiring IIO context\n");
assert((ctx = iio_create_default_context()) && "No context");
assert(iio_context_get_devices_count(ctx) > 0 && "No devices");
printf("* Acquiring AD9361 streaming devices\n");
assert(get_ad9361_stream_dev(ctx, TX, &tx) && "No tx dev found");
assert(get_ad9361_stream_dev(ctx, RX, &rx) && "No rx dev found");
printf("* Configuring AD9361 for streaming\n");
assert(cfg_ad9361_streaming_ch(ctx, &rxcfg, RX, 0) && "RX port 0 not found");
assert(cfg_ad9361_streaming_ch(ctx, &txcfg, TX, 0) && "TX port 0 not found");
printf("* Initializing AD9361 IIO streaming channels\n");
assert(get_ad9361_stream_ch(ctx, RX, rx, 0, &rx0_i) && "RX chan i not found");
assert(get_ad9361_stream_ch(ctx, RX, rx, 1, &rx0_q) && "RX chan q not found");
assert(get_ad9361_stream_ch(ctx, TX, tx, 0, &tx0_i) && "TX chan i not found");
assert(get_ad9361_stream_ch(ctx, TX, tx, 1, &tx0_q) && "TX chan q not found");
printf("* Enabling IIO streaming channels\n");
iio_channel_enable(rx0_i);
iio_channel_enable(rx0_q);
iio_channel_enable(tx0_i);
iio_channel_enable(tx0_q);
printf("* Creating non-cyclic IIO buffers with 1 MiS\n");
rxbuf = iio_device_create_buffer(rx, 1024*1024, false);
if (!rxbuf) {
perror("Could not create RX buffer");
shutdown();
}
txbuf = iio_device_create_buffer(tx, 1024*1024, false);
if (!txbuf) {
perror("Could not create TX buffer");
shutdown();
}
printf("* Starting IO streaming (press CTRL+C to cancel)\n");
while (!stop)
{
ssize_t nbytes_rx, nbytes_tx;
void *p_dat, *p_end;
ptrdiff_t p_inc;
// Schedule TX buffer
nbytes_tx = iio_buffer_push(txbuf);
if (nbytes_tx < 0) { printf("Error pushing buf %d\n", (int) nbytes_tx); shutdown(); }
// Refill RX buffer
nbytes_rx = iio_buffer_refill(rxbuf);
if (nbytes_rx < 0) { printf("Error refilling buf %d\n",(int) nbytes_rx); shutdown(); }
// READ: Get pointers to RX buf and read IQ from RX buf port 0
p_inc = iio_buffer_step(rxbuf);
p_end = iio_buffer_end(rxbuf);
for (p_dat = iio_buffer_first(rxbuf, rx0_i); p_dat < p_end; p_dat += p_inc) {
// Example: swap I and Q
const int16_t i = ((int16_t*)p_dat)[0]; // Real (I)
const int16_t q = ((int16_t*)p_dat)[1]; // Imag (Q)
((int16_t*)p_dat)[0] = q;
((int16_t*)p_dat)[1] = i;
}
// WRITE: Get pointers to TX buf and write IQ to TX buf port 0
p_inc = iio_buffer_step(txbuf);
p_end = iio_buffer_end(txbuf);
for (p_dat = iio_buffer_first(txbuf, tx0_i); p_dat < p_end; p_dat += p_inc) {
// Example: fill with zeros
((int16_t*)p_dat)[0] = 0; // Real (I)
((int16_t*)p_dat)[1] = 0; // Imag (Q)
}
// Sample counter increment and status output
nrx += nbytes_rx / iio_device_get_sample_size(rx);
ntx += nbytes_tx / iio_device_get_sample_size(tx);
printf("\tRX %8.2f MSmp, TX %8.2f MSmp\n", nrx/1e6, ntx/1e6);
}
shutdown();
return 0;
}