/*
* We utilize chipcommon configuration register SBFlagSt to implement a
* smart shared IRQ handling machenism through which only ISRs registered
* for the SB cores that raised the interrupt are invoked. This machenism
* relies on the SBFlagSt register's reliable recording of the SB cores
* that raised the interrupt.
*/
void __init
arch_init_irq(void)
{
int i;
uint32 coreidx, mips_core_id;
void *regs;
if (BCM330X(current_cpu_data.processor_id))
mips_core_id = MIPS33_CORE_ID;
else if (MIPS74K(current_cpu_data.processor_id))
mips_core_id = MIPS74K_CORE_ID;
else {
printk(KERN_ERR "MIPS CPU type %x unknown", current_cpu_data.processor_id);
return;
}
/* Cache chipc and mips33 config registers */
ASSERT(bcm947xx_sih);
coreidx = si_coreidx(bcm947xx_sih);
regs = si_setcore(bcm947xx_sih, mips_core_id, 0);
mipsirq = si_irq(bcm947xx_sih);
if (bcm947xx_sih->socitype == SOCI_SB) {
if (regs)
mipssbr = (sbconfig_t *)((ulong)regs + SBCONFIGOFF);
if ((regs = si_setcore(bcm947xx_sih, CC_CORE_ID, 0)))
ccsbr = (sbconfig_t *)((ulong)regs + SBCONFIGOFF);
}
si_setcoreidx(bcm947xx_sih, coreidx);
if (BCM330X(current_cpu_data.processor_id)) {
/* Cache mips33 sbintvec register */
if (mipssbr)
shints = R_REG(NULL, &mipssbr->sbintvec);
} else {
uint32 *intmask;
/* Use intmask5 register to route the timer interrupt */
intmask = (uint32 *) &((mips74kregs_t *)regs)->intmask[5];
W_REG(NULL, intmask, 1 << 31);
intmask = (uint32 *) &((mips74kregs_t *)regs)->intmask[0];
shints = R_REG(NULL, intmask);
/* Save the pointer to mips core registers */
mips_corereg = regs;
}
/* Install interrupt controllers */
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, (i < SBMIPS_NUMIRQS ? &brcm_irq_type : &brcm_irq2_type));
}
}
void __init memory_setup(void)
{
#if defined(CONFIG_HIGHMEM)
unsigned long extmem = 0, off, data;
unsigned long off1, data1;
off = (unsigned long)prom_init;
data = *(unsigned long *)prom_init;
off1 = off + 4;
data1 = *(unsigned long *)off1;
extmem = 128 MB;
int highmemsupport=0;
uint boardnum;
/* Get global SB handle */
bcm947xx_sih = si_kattach(SI_OSH);
boardnum = bcm_strtoul( nvram_safe_get( "boardnum" ), NULL, 0 );
if (boardnum == 0 && nvram_match("boardtype", "0xF5B2")
&& nvram_match("boardrev", "0x1100")
&& !nvram_match("pci/2/1/sb20in80and160hr5ghpo", "0"))
highmemsupport = 1;
if (boardnum == 00 && nvram_match("boardtype", "0xF5B2")
&& nvram_match("boardrev", "0x1100")
&& nvram_match("pci/2/1/sb20in80and160hr5ghpo", "0"))
highmemsupport = 1;
if (extmem && detectmem == 128 MB && highmemsupport) {
/* We should deduct 0x1000 from the second memory
* region, because of the fact that processor does prefetch.
* Now that we are deducting a page from second memory
* region, we could add the earlier deducted 4KB (from first bank)
* to the second region (the fact that 0x80000000 -> 0x88000000
* shadows 0x0 -> 0x8000000)
*/
if (MIPS74K(current_cpu_data.processor_id) && (detectmem == (128 MB)))
extmem -= 0x1000;
extended_ram = extmem;
add_memory_region(SI_SDRAM_R2 + (128 MB) - 0x1000, extmem, BOOT_MEM_RAM);
}
#endif /* CONFIG_HIGHMEM */
}
void __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
{
unsigned long mem, before, offset;
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BCM947XX;
/* Figure out memory size by finding aliases.
*
* We assume that there will be no more than 128 MB of memory,
* and that the memory size will be a multiple of 1 MB.
*
* We set 'before' to be the amount of memory (in MB) before this
* function, i.e. one MB less than the number of MB of memory that we
* *know* we have. And we set 'offset' to be the address of 'prominit'
* minus 'before', so that KSEG0 or KSEG1 base + offset < 1 MB.
* This prevents us from overrunning 128 MB and causing a bus error.
*/
before = ((unsigned long) &prom_init) & (127 << 20);
offset = ((unsigned long) &prom_init) - before;
for (mem = before + (1 << 20); mem < (128 << 20); mem += (1 << 20))
if (*(unsigned long *)(offset + mem) ==
*(unsigned long *)(prom_init)) {
/*
* We may already be well past the end of memory at
* this point, so we'll have to compensate for it.
*/
mem -= before;
break;
}
/* Ignoring the last page when ddr size is 128M. Cached
* accesses to last page is causing the processor to prefetch
* using address above 128M stepping out of the ddr address
* space.
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == 0x8000000))
mem -= 0x1000;
add_memory_region(0, mem, BOOT_MEM_RAM);
}
void __init
prom_init(void)
{
unsigned long extmem = 0, off, data;
static unsigned long mem;
unsigned long off1, data1;
struct nvram_header *header;
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
/* These are not really being used anywhere - LR */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BCM947XX;
#endif
off = (unsigned long)prom_init;
data = *(unsigned long *)prom_init;
off1 = off + 4;
data1 = *(unsigned long *)off1;
/* Figure out memory size by finding aliases */
for (mem = (1 MB); mem < (128 MB); mem <<= 1) {
if ((*(unsigned long *)(off + mem) == data) &&
(*(unsigned long *)(off1 + mem) == data1))
break;
}
detectmem = mem;
#if 0// defined(CONFIG_HIGHMEM) && !defined(CONFIG_BCM80211AC)
if (mem == 128 MB) {
early_tlb_init();
/* Add one temporary TLB entries to map SDRAM Region 2.
* Physical Virtual
* 0x80000000 0xc0000000 (1st: 256MB)
* 0x90000000 0xd0000000 (2nd: 256MB)
*/
add_tmptlb_entry(ENTRYLO(SI_SDRAM_R2),
ENTRYLO(SI_SDRAM_R2 + (256 MB)),
EXTVBASE, PM_256M);
off = EXTVBASE + __pa(off);
for (extmem = (128 MB); extmem < (512 MB); extmem <<= 1) {
if (*(unsigned long *)(off + extmem) == data)
break;
}
extmem -= mem;
/* Keep tlb entries back in consistent state */
early_tlb_init();
}
#endif /* CONFIG_HIGHMEM */
/* Ignoring the last page when ddr size is 128M. Cached
* accesses to last page is causing the processor to prefetch
* using address above 128M stepping out of the ddr address
* space.
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
mem -= 0x1000;
/* CFE could have loaded nvram during netboot
* to top 32KB of RAM, Just check for nvram signature
* and copy it to nvram space embedded in linux
* image for later use by nvram driver.
*/
header = (struct nvram_header *)(KSEG0ADDR(mem - NVRAM_SPACE));
if (ltoh32(header->magic) == NVRAM_MAGIC) {
uint32 *src = (uint32 *)header;
uint32 *dst = (uint32 *)ram_nvram_buf;
uint32 i;
printk("Copying NVRAM bytes: %d from: 0x%p To: 0x%p\n", ltoh32(header->len),
src, dst);
for (i = 0; i < ltoh32(header->len) && i < NVRAM_SPACE; i += 4)
*dst++ = ltoh32(*src++);
}
add_memory_region(SI_SDRAM_BASE, mem, BOOT_MEM_RAM);
#if 0// defined(CONFIG_HIGHMEM) && !defined(CONFIG_BCM80211AC)
if (extmem) {
/* We should deduct 0x1000 from the second memory
* region, because of the fact that processor does prefetch.
* Now that we are deducting a page from second memory
* region, we could add the earlier deducted 4KB (from first bank)
* to the second region (the fact that 0x80000000 -> 0x88000000
* shadows 0x0 -> 0x8000000)
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
extmem -= 0x1000;
add_memory_region(SI_SDRAM_R2 + (128 MB) - 0x1000, extmem, BOOT_MEM_RAM);
}
#endif /* CONFIG_HIGHMEM */
}
void __init
prom_init(void)
{
unsigned long mem, extmem = 0, off, data;
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BCM947XX;
off = (unsigned long)prom_init;
data = *(unsigned long *)prom_init;
/* Figure out memory size by finding aliases */
for (mem = (1 MB); mem < (128 MB); mem <<= 1) {
if (*(unsigned long *)(off + mem) == data)
break;
}
#if CONFIG_RAM_SIZE
{
unsigned long config_mem;
config_mem = CONFIG_RAM_SIZE * 0x100000;
if (config_mem < mem)
mem = config_mem;
}
#endif
#ifdef CONFIG_HIGHMEM
if (mem == 128 MB) {
early_tlb_init();
/* Add one temporary TLB entries to map SDRAM Region 2.
* Physical Virtual
* 0x80000000 0xc0000000 (1st: 256MB)
* 0x90000000 0xd0000000 (2nd: 256MB)
*/
add_tmptlb_entry(ENTRYLO(SI_SDRAM_R2),
ENTRYLO(SI_SDRAM_R2 + (256 MB)),
EXTVBASE, PM_256M);
off = EXTVBASE + __pa(off);
for (extmem = (128 MB); extmem < (512 MB); extmem <<= 1) {
if (*(unsigned long *)(off + extmem) == data)
break;
}
extmem -= mem;
/* Keep tlb entries back in consistent state */
early_tlb_init();
}
#endif /* CONFIG_HIGHMEM */
/* Ignoring the last page when ddr size is 128M. Cached
* accesses to last page is causing the processor to prefetch
* using address above 128M stepping out of the ddr address
* space.
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
mem -= 0x1000;
add_memory_region(SI_SDRAM_BASE, mem, BOOT_MEM_RAM);
#ifdef CONFIG_HIGHMEM
if (extmem) {
/* We should deduct 0x1000 from the second memory
* region, because of the fact that processor does prefetch.
* Now that we are deducting a page from second memory
* region, we could add the earlier deducted 4KB (from first bank)
* to the second region (the fact that 0x80000000 -> 0x88000000
* shadows 0x0 -> 0x8000000)
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
extmem -= 0x1000;
add_memory_region(SI_SDRAM_R2 + (128 MB) - 0x1000, extmem, BOOT_MEM_RAM);
}
#endif /* CONFIG_HIGHMEM */
}
