/**
* Attach network filter driver from bandwidth group.
*
* @returns VBox status code.
* @param pUVM The user mode VM structure.
* @param pDrvIns The driver instance.
* @param pszBwGroup Name of the bandwidth group to attach to.
* @param pFilter Pointer to the filter we attach.
*/
VMMR3_INT_DECL(int) PDMR3NsAttach(PUVM pUVM, PPDMDRVINS pDrvIns, const char *pszBwGroup, PPDMNSFILTER pFilter)
{
VM_ASSERT_EMT(pUVM->pVM);
AssertPtrReturn(pFilter, VERR_INVALID_POINTER);
AssertReturn(pFilter->pBwGroupR3 == NULL, VERR_ALREADY_EXISTS);
RT_NOREF_PV(pDrvIns);
PPDMNETSHAPER pShaper = pUVM->pdm.s.pNetShaper;
LOCK_NETSHAPER_RETURN(pShaper);
int rc = VINF_SUCCESS;
PPDMNSBWGROUP pBwGroupNew = NULL;
if (pszBwGroup)
{
pBwGroupNew = pdmNsBwGroupFindById(pShaper, pszBwGroup);
if (pBwGroupNew)
pdmNsBwGroupRef(pBwGroupNew);
else
rc = VERR_NOT_FOUND;
}
if (RT_SUCCESS(rc))
{
PPDMNSBWGROUP pBwGroupOld = ASMAtomicXchgPtrT(&pFilter->pBwGroupR3, pBwGroupNew, PPDMNSBWGROUP);
ASMAtomicWritePtr(&pFilter->pBwGroupR0, MMHyperR3ToR0(pUVM->pVM, pBwGroupNew));
if (pBwGroupOld)
pdmNsBwGroupUnref(pBwGroupOld);
pdmNsFilterLink(pFilter);
}
UNLOCK_NETSHAPER(pShaper);
return rc;
}
/**
* Ensures that there is space for at least @a cNewRanges in the table,
* reallocating the table if necessary.
*
* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
* @a *ppaMsrRanges is freed and set to NULL.
* @param pVM The cross context VM structure. If NULL,
* use the process heap, otherwise the VM's hyper heap.
* @param ppaMsrRanges The variable pointing to the ranges (input/output).
* @param cMsrRanges The current number of ranges.
* @param cNewRanges The number of ranges to be added.
*/
static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
{
uint32_t cMsrRangesAllocated;
if (!pVM)
cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
else
{
/*
* We're using the hyper heap now, but when the range array was copied over to it from
* the host-context heap, we only copy the exact size and not the ensured size.
* See @bugref{7270}.
*/
cMsrRangesAllocated = cMsrRanges;
}
if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
{
void *pvNew;
uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
if (pVM)
{
Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
size_t cbNew = cNew * sizeof(**ppaMsrRanges);
int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
if (RT_FAILURE(rc))
{
*ppaMsrRanges = NULL;
pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
return NULL;
}
*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
}
else
{
pvNew = RTMemRealloc(*ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
if (!pvNew)
{
RTMemFree(*ppaMsrRanges);
*ppaMsrRanges = NULL;
return NULL;
}
}
*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
}
if (pVM)
{
/* Update R0 and RC pointers. */
Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
}
return *ppaMsrRanges;
}
/**
* Free an item.
*
* @param pQueue The queue.
* @param pItem The item.
*/
DECLINLINE(void) pdmR3QueueFreeItem(PPDMQUEUE pQueue, PPDMQUEUEITEMCORE pItem)
{
VM_ASSERT_EMT(pQueue->pVMR3);
int i = pQueue->iFreeHead;
int iNext = (i + 1) % (pQueue->cItems + PDMQUEUE_FREE_SLACK);
pQueue->aFreeItems[i].pItemR3 = pItem;
if (pQueue->pVMRC)
{
pQueue->aFreeItems[i].pItemRC = MMHyperR3ToRC(pQueue->pVMR3, pItem);
pQueue->aFreeItems[i].pItemR0 = MMHyperR3ToR0(pQueue->pVMR3, pItem);
}
if (!ASMAtomicCmpXchgU32(&pQueue->iFreeHead, iNext, i))
AssertMsgFailed(("huh? i=%d iNext=%d iFreeHead=%d iFreeTail=%d\n", i, iNext, pQueue->iFreeHead, pQueue->iFreeTail));
STAM_STATS({ ASMAtomicDecU32(&pQueue->cStatPending); });
VMMR3DECL(int) PDMR3NsAttach(PVM pVM, PPDMDRVINS pDrvIns, const char *pcszBwGroup,
PPDMNSFILTER pFilter)
{
VM_ASSERT_EMT(pVM);
AssertPtrReturn(pFilter, VERR_INVALID_POINTER);
AssertReturn(pFilter->pBwGroupR3 == NULL, VERR_ALREADY_EXISTS);
PUVM pUVM = pVM->pUVM;
PPDMNETSHAPER pShaper = pUVM->pdm.s.pNetShaper;
PPDMNSBWGROUP pBwGroupOld = NULL;
PPDMNSBWGROUP pBwGroupNew = NULL;
int rc = RTCritSectEnter(&pShaper->cs); AssertRC(rc);
if (RT_SUCCESS(rc))
{
if (pcszBwGroup)
{
pBwGroupNew = pdmNsBwGroupFindById(pShaper, pcszBwGroup);
if (pBwGroupNew)
pdmNsBwGroupRef(pBwGroupNew);
else
rc = VERR_NOT_FOUND;
}
if (RT_SUCCESS(rc))
{
pBwGroupOld = ASMAtomicXchgPtrT(&pFilter->pBwGroupR3, pBwGroupNew, PPDMNSBWGROUP);
ASMAtomicWritePtr(&pFilter->pBwGroupR0, MMHyperR3ToR0(pVM, pBwGroupNew));
if (pBwGroupOld)
pdmNsBwGroupUnref(pBwGroupOld);
pdmNsFilterLink(pFilter);
}
int rc2 = RTCritSectLeave(&pShaper->cs); AssertRC(rc2);
}
return rc;
}
/**
* Internal worker for the queue creation apis.
*
* @returns VBox status.
* @param pVM Pointer to the VM.
* @param cbItem Item size.
* @param cItems Number of items.
* @param cMilliesInterval Number of milliseconds between polling the queue.
* If 0 then the emulation thread will be notified whenever an item arrives.
* @param fRZEnabled Set if the queue will be used from RC/R0 and need to be allocated from the hyper heap.
* @param pszName The queue name. Unique. Not copied.
* @param ppQueue Where to store the queue handle.
*/
static int pdmR3QueueCreate(PVM pVM, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval, bool fRZEnabled,
const char *pszName, PPDMQUEUE *ppQueue)
{
PUVM pUVM = pVM->pUVM;
/*
* Validate input.
*/
AssertMsgReturn(cbItem >= sizeof(PDMQUEUEITEMCORE) && cbItem < _1M, ("cbItem=%zu\n", cbItem), VERR_OUT_OF_RANGE);
AssertMsgReturn(cItems >= 1 && cItems <= _64K, ("cItems=%u\n", cItems), VERR_OUT_OF_RANGE);
/*
* Align the item size and calculate the structure size.
*/
cbItem = RT_ALIGN(cbItem, sizeof(RTUINTPTR));
size_t cb = cbItem * cItems + RT_ALIGN_Z(RT_OFFSETOF(PDMQUEUE, aFreeItems[cItems + PDMQUEUE_FREE_SLACK]), 16);
PPDMQUEUE pQueue;
int rc;
if (fRZEnabled)
rc = MMHyperAlloc(pVM, cb, 0, MM_TAG_PDM_QUEUE, (void **)&pQueue );
else
rc = MMR3HeapAllocZEx(pVM, MM_TAG_PDM_QUEUE, cb, (void **)&pQueue);
if (RT_FAILURE(rc))
return rc;
/*
* Initialize the data fields.
*/
pQueue->pVMR3 = pVM;
pQueue->pVMR0 = fRZEnabled ? pVM->pVMR0 : NIL_RTR0PTR;
pQueue->pVMRC = fRZEnabled ? pVM->pVMRC : NIL_RTRCPTR;
pQueue->pszName = pszName;
pQueue->cMilliesInterval = cMilliesInterval;
//pQueue->pTimer = NULL;
pQueue->cbItem = (uint32_t)cbItem;
pQueue->cItems = cItems;
//pQueue->pPendingR3 = NULL;
//pQueue->pPendingR0 = NULL;
//pQueue->pPendingRC = NULL;
pQueue->iFreeHead = cItems;
//pQueue->iFreeTail = 0;
PPDMQUEUEITEMCORE pItem = (PPDMQUEUEITEMCORE)((char *)pQueue + RT_ALIGN_Z(RT_OFFSETOF(PDMQUEUE, aFreeItems[cItems + PDMQUEUE_FREE_SLACK]), 16));
for (unsigned i = 0; i < cItems; i++, pItem = (PPDMQUEUEITEMCORE)((char *)pItem + cbItem))
{
pQueue->aFreeItems[i].pItemR3 = pItem;
if (fRZEnabled)
{
pQueue->aFreeItems[i].pItemR0 = MMHyperR3ToR0(pVM, pItem);
pQueue->aFreeItems[i].pItemRC = MMHyperR3ToRC(pVM, pItem);
}
}
/*
* Create timer?
*/
if (cMilliesInterval)
{
rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, pdmR3QueueTimer, pQueue, "Queue timer", &pQueue->pTimer);
if (RT_SUCCESS(rc))
{
rc = TMTimerSetMillies(pQueue->pTimer, cMilliesInterval);
if (RT_FAILURE(rc))
{
AssertMsgFailed(("TMTimerSetMillies failed rc=%Rrc\n", rc));
int rc2 = TMR3TimerDestroy(pQueue->pTimer);
AssertRC(rc2);
}
}
else
AssertMsgFailed(("TMR3TimerCreateInternal failed rc=%Rrc\n", rc));
if (RT_FAILURE(rc))
{
if (fRZEnabled)
MMHyperFree(pVM, pQueue);
else
MMR3HeapFree(pQueue);
return rc;
}
/*
* Insert into the queue list for timer driven queues.
*/
pdmLock(pVM);
pQueue->pNext = pUVM->pdm.s.pQueuesTimer;
pUVM->pdm.s.pQueuesTimer = pQueue;
pdmUnlock(pVM);
}
else
{
/*
* Insert into the queue list for forced action driven queues.
* This is a FIFO, so insert at the end.
*/
/** @todo we should add a priority to the queues so we don't have to rely on
* the initialization order to deal with problems like @bugref{1605} (pgm/pcnet
* deadlock caused by the critsect queue to be last in the chain).
* - Update, the critical sections are no longer using queues, so this isn't a real
* problem any longer. The priority might be a nice feature for later though.
*/
pdmLock(pVM);
if (!pUVM->pdm.s.pQueuesForced)
pUVM->pdm.s.pQueuesForced = pQueue;
else
{
PPDMQUEUE pPrev = pUVM->pdm.s.pQueuesForced;
while (pPrev->pNext)
pPrev = pPrev->pNext;
pPrev->pNext = pQueue;
}
pdmUnlock(pVM);
}
/*
* Register the statistics.
*/
STAMR3RegisterF(pVM, &pQueue->cbItem, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Item size.", "/PDM/Queue/%s/cbItem", pQueue->pszName);
STAMR3RegisterF(pVM, &pQueue->cItems, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Queue size.", "/PDM/Queue/%s/cItems", pQueue->pszName);
STAMR3RegisterF(pVM, &pQueue->StatAllocFailures, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "PDMQueueAlloc failures.", "/PDM/Queue/%s/AllocFailures", pQueue->pszName);
STAMR3RegisterF(pVM, &pQueue->StatInsert, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS, "Calls to PDMQueueInsert.", "/PDM/Queue/%s/Insert", pQueue->pszName);
STAMR3RegisterF(pVM, &pQueue->StatFlush, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS, "Calls to pdmR3QueueFlush.", "/PDM/Queue/%s/Flush", pQueue->pszName);
STAMR3RegisterF(pVM, &pQueue->StatFlushLeftovers, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Left over items after flush.", "/PDM/Queue/%s/FlushLeftovers", pQueue->pszName);
#ifdef VBOX_WITH_STATISTICS
STAMR3RegisterF(pVM, &pQueue->StatFlushPrf, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS, "Profiling pdmR3QueueFlush.", "/PDM/Queue/%s/FlushPrf", pQueue->pszName);
STAMR3RegisterF(pVM, (void *)&pQueue->cStatPending, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Pending items.", "/PDM/Queue/%s/Pending", pQueue->pszName);
#endif
*ppQueue = pQueue;
return VINF_SUCCESS;
}
int MsixInit(PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, PPDMMSIREG pMsiReg)
{
if (pMsiReg->cMsixVectors == 0)
return VINF_SUCCESS;
/* We cannot init MSI-X on raw devices yet. */
Assert(!pciDevIsPassthrough(pDev));
uint16_t cVectors = pMsiReg->cMsixVectors;
uint8_t iCapOffset = pMsiReg->iMsixCapOffset;
uint8_t iNextOffset = pMsiReg->iMsixNextOffset;
uint8_t iBar = pMsiReg->iMsixBar;
if (cVectors > VBOX_MSIX_MAX_ENTRIES)
{
AssertMsgFailed(("Too many MSI-X vectors: %d\n", cVectors));
return VERR_TOO_MUCH_DATA;
}
if (iBar > 5)
{
AssertMsgFailed(("Using wrong BAR for MSI-X: %d\n", iBar));
return VERR_INVALID_PARAMETER;
}
Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
int rc = VINF_SUCCESS;
/* If device is passthrough, BAR is registered using common mechanism. */
if (!pciDevIsPassthrough(pDev))
{
rc = PDMDevHlpPCIIORegionRegister (pDev->pDevIns, iBar, 0x1000, PCI_ADDRESS_SPACE_MEM, msixMap);
if (RT_FAILURE (rc))
return rc;
}
pDev->Int.s.u8MsixCapOffset = iCapOffset;
pDev->Int.s.u8MsixCapSize = VBOX_MSIX_CAP_SIZE;
PVM pVM = PDMDevHlpGetVM(pDev->pDevIns);
pDev->Int.s.pMsixPageR3 = NULL;
rc = MMHyperAlloc(pVM, 0x1000, 1, MM_TAG_PDM_DEVICE_USER, (void **)&pDev->Int.s.pMsixPageR3);
if (RT_FAILURE(rc) || (pDev->Int.s.pMsixPageR3 == NULL))
return VERR_NO_VM_MEMORY;
RT_BZERO(pDev->Int.s.pMsixPageR3, 0x1000);
pDev->Int.s.pMsixPageR0 = MMHyperR3ToR0(pVM, pDev->Int.s.pMsixPageR3);
pDev->Int.s.pMsixPageRC = MMHyperR3ToRC(pVM, pDev->Int.s.pMsixPageR3);
/* R3 PCI helper */
pDev->Int.s.pPciBusPtrR3 = pPciHlp;
PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSIX);
PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
PCIDevSetWord(pDev, iCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL, cVectors - 1);
uint32_t offTable = 0, offPBA = 0x800;
PCIDevSetDWord(pDev, iCapOffset + VBOX_MSIX_TABLE_BIROFFSET, offTable | iBar);
PCIDevSetDWord(pDev, iCapOffset + VBOX_MSIX_PBA_BIROFFSET, offPBA | iBar);
pciDevSetMsixCapable(pDev);
return VINF_SUCCESS;
}
/**
* Gets the ring-0 address of the NOP critical section.
*
* @returns The ring-0 address of the NOP critical section.
* @param pVM Pointer to the VM.
*/
VMMR3DECL(R0PTRTYPE(PPDMCRITSECT)) PDMR3CritSectGetNopR0(PVM pVM)
{
VM_ASSERT_VALID_EXT_RETURN(pVM, NIL_RTR0PTR);
return MMHyperR3ToR0(pVM, &pVM->pdm.s.NopCritSect);
}
/**
* Initializes the interpreted execution manager.
*
* This must be called after CPUM as we're quering information from CPUM about
* the guest and host CPUs.
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
*/
VMMR3DECL(int) IEMR3Init(PVM pVM)
{
uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
{
PVMCPU pVCpu = &pVM->aCpus[idCpu];
pVCpu->iem.s.pCtxR3 = CPUMQueryGuestCtxPtr(pVCpu);
pVCpu->iem.s.pCtxR0 = VM_R0_ADDR(pVM, pVCpu->iem.s.pCtxR3);
pVCpu->iem.s.pCtxRC = VM_RC_ADDR(pVM, pVCpu->iem.s.pCtxR3);
pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
"Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
"Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
"Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
#ifdef VBOX_WITH_STATISTICS
STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
#endif
STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
"Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
"Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
"Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
"Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
"Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
/* Allocate instruction statistics and register them. */
pVCpu->iem.s.pStatsR3 = (PIEMINSTRSTATS)MMR3HeapAllocZ(pVM, MM_TAG_IEM, sizeof(IEMINSTRSTATS));
AssertLogRelReturn(pVCpu->iem.s.pStatsR3, VERR_NO_MEMORY);
int rc = MMHyperAlloc(pVM, sizeof(IEMINSTRSTATS), sizeof(uint64_t), MM_TAG_IEM, (void **)&pVCpu->iem.s.pStatsCCR3);
AssertLogRelRCReturn(rc, rc);
pVCpu->iem.s.pStatsR0 = MMHyperR3ToR0(pVM, pVCpu->iem.s.pStatsCCR3);
pVCpu->iem.s.pStatsRC = MMHyperR3ToR0(pVM, pVCpu->iem.s.pStatsCCR3);
# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
STAMR3RegisterF(pVM, &pVCpu->iem.s.pStatsCCR3->a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
STAMR3RegisterF(pVM, &pVCpu->iem.s.pStatsR3->a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
# include "IEMInstructionStatisticsTmpl.h"
# undef IEM_DO_INSTR_STAT
#endif
/*
* Host and guest CPU information.
*/
if (idCpu == 0)
{
pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
{
case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
}
LogRel(("IEM: TargetCpu=%s, Microarch=%s\n", iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMR3MicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch)));
#endif
}
else
{
pVCpu->iem.s.enmCpuVendor = pVM->aCpus[0].iem.s.enmCpuVendor;
pVCpu->iem.s.enmHostCpuVendor = pVM->aCpus[0].iem.s.enmHostCpuVendor;
#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
pVCpu->iem.s.uTargetCpu = pVM->aCpus[0].iem.s.uTargetCpu;
#endif
}
/*
* Mark all buffers free.
*/
uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
while (iMemMap-- > 0)
pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
}
return VINF_SUCCESS;
}
