/**************************************************************************************************
* @fn mrfiSpiInit
*
* @brief Initialize SPI.
*
* @param none
*
* @return none
**************************************************************************************************
*/
void mrfiSpiInit(void)
{
#ifdef MRFI_TIMER_ALWAYS_ACTIVE
sActiveSPI = false; // initialize interface status
#endif
/* configure all SPI related pins */
MRFI_SPI_CONFIG_CSN_PIN_AS_OUTPUT();
MRFI_SPI_CONFIG_SCLK_PIN_AS_OUTPUT();
MRFI_SPI_CONFIG_SI_PIN_AS_OUTPUT();
MRFI_SPI_CONFIG_SO_PIN_AS_INPUT();
/* set CSn to default high level */
MRFI_SPI_DRIVE_CSN_HIGH();
/* initialize the SPI registers */
MRFI_SPI_INIT();
}
/**************************************************************************************************
* @fn mrfiSpiInit
*
* @brief Initialize SPI.
*
* @param none
*
* @return none
**************************************************************************************************
*/
void mrfiSpiInit(void)
{
/* configure all SPI related pins */
MRFI_SPI_CONFIG_CSN_PIN_AS_OUTPUT();
MRFI_SPI_CONFIG_SCLK_PIN_AS_OUTPUT();
MRFI_SPI_CONFIG_SI_PIN_AS_OUTPUT();
MRFI_SPI_CONFIG_SO_PIN_AS_INPUT();
/* set CSn to default high level */
MRFI_SPI_DRIVE_CSN_HIGH();
/* initialize the SPI registers */
MRFI_SPI_INIT();
/* USART0 in SPI mode (Port 3) */
/*P3SEL |= ((0x01 << 1) | (0x01 << 3) | (0x01 << 2)); // Select Peripheral functionality (SPI: SIMO, SOI, SCK)
P3DIR |= ((0x01 << 1) | (0x01 << 3)); // Configure as outputs(SIMO,SCK)
P3DIR &= ~(0x01 << 2); // Configure as inputs(SOMI)*/
/* Perform SPI module initialization */
/*U0CTL = CHAR + SYNC + MM + SWRST; // SPI mode, 8-bit transfer, Listen disabled, SPI master, SW reset (c[2]p14-14)
U0TCTL = CKPH + SSEL1 + STC; // Data on Rising Edge, SMCLK, 3-wire SPI mode (c[2]p14-15)
U0BR0 = 0x04; // SPICLK set baud (c[2]p14-17)
U0BR1 = 0; // Dont need baud rate control register 2 - clear it (c[2]p14-15)
U0MCTL = 0; // Dont need modulation control (c[2]p14-15)
ME1 |= USPIE0; // Module 0 enabled (c[2]p14-19)
U0CTL &= ~SWRST; // Remove RESET (c[2]p14-14)
//IE1 &= ~(UTXIE0); // no interrupt on SPI tx, active polling on U0TCTL.TXEPT
//IE1 &= ~(URXIE0); // toverify, active polling on IFG2.URXIFG0
//wait delay
int i,j;
for(j=0; j < 0x100; j++) {
for (i = 0; i < 0xff; i++) {
__no_operation();
__no_operation();
}
}*/
}
