Beispiel #1
0
/*
 * Configure the pin mux for the module
 */
void configure_module_pin_mux(const struct module_pin_mux *mod_pin_mux)
{
	int i;

	if (!mod_pin_mux)
		return;

	for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
		MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
}
static struct platform_device dm646x_mdio_device = {
	.name		= "davinci_mdio",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(dm646x_mdio_resources),
	.resource	= dm646x_mdio_resources,
};

/*
 * Device specific mux setup
 *
 *	soc	description	mux  mode   mode  mux	 dbg
 *				reg  offset mask  mode
 */
static const struct mux_config dm646x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM646X, ATAEN,		0,   0,     5,	  1,	 true)

MUX_CFG(DM646X, AUDCK1,		0,   29,    1,	  0,	 false)

MUX_CFG(DM646X, AUDCK0,		0,   28,    1,	  0,	 false)

MUX_CFG(DM646X, CRGMUX,			0,   24,    7,    5,	 true)

MUX_CFG(DM646X, STSOMUX_DISABLE,	0,   22,    3,    0,	 true)

MUX_CFG(DM646X, STSIMUX_DISABLE,	0,   20,    3,    0,	 true)

MUX_CFG(DM646X, PTSOMUX_DISABLE,	0,   18,    3,    0,	 true)

MUX_CFG(DM646X, PTSIMUX_DISABLE,	0,   16,    3,    0,	 true)
	CLK(NULL,		"clk_usb1",		&clk_usb1),
	CLK(NULL,		"clk_tdm1",		&clk_tdm1),
	CLK(NULL,		"clk_debugss",		&clk_debugss),
	CLK(NULL,		"clk_ethss_rgmii",	&clk_ethss_rgmii),
	CLK(NULL,		"clk_system",		&clk_system),
	CLK(NULL,		"clk_imcop",		&clk_imcop),
	CLK(NULL,		"clk_spare",		&clk_spare),
	CLK("davinci_mmc.1",	NULL,			&clk_sdio1),
	CLK(NULL,		"clk_ddr2_vrst",	&clk_ddr2_vrst),
	CLK(NULL,		"clk_ddr2_vctl_rst",	&clk_ddr2_vctl_rst),
	CLK(NULL,		NULL,			NULL),
};

static const struct mux_config pins[] = {
#ifdef CONFIG_DAVINCI_MUX
	MUX_CFG(TNETV107X, ASR_A00,		0, 0, 0x1f, 0x00, false)
	MUX_CFG(TNETV107X, GPIO32,		0, 0, 0x1f, 0x04, false)
	MUX_CFG(TNETV107X, ASR_A01,		0, 5, 0x1f, 0x00, false)
	MUX_CFG(TNETV107X, GPIO33,		0, 5, 0x1f, 0x04, false)
	MUX_CFG(TNETV107X, ASR_A02,		0, 10, 0x1f, 0x00, false)
	MUX_CFG(TNETV107X, GPIO34,		0, 10, 0x1f, 0x04, false)
	MUX_CFG(TNETV107X, ASR_A03,		0, 15, 0x1f, 0x00, false)
	MUX_CFG(TNETV107X, GPIO35,		0, 15, 0x1f, 0x04, false)
	MUX_CFG(TNETV107X, ASR_A04,		0, 20, 0x1f, 0x00, false)
	MUX_CFG(TNETV107X, GPIO36,		0, 20, 0x1f, 0x04, false)
	MUX_CFG(TNETV107X, ASR_A05,		0, 25, 0x1f, 0x00, false)
	MUX_CFG(TNETV107X, GPIO37,		0, 25, 0x1f, 0x04, false)
	MUX_CFG(TNETV107X, ASR_A06,		1, 0, 0x1f, 0x00, false)
	MUX_CFG(TNETV107X, GPIO38,		1, 0, 0x1f, 0x04, false)
	MUX_CFG(TNETV107X, ASR_A07,		1, 5, 0x1f, 0x00, false)
	MUX_CFG(TNETV107X, GPIO39,		1, 5, 0x1f, 0x04, false)
Beispiel #4
0
static const struct mux_config dm355_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM355,	MMCSD0,		4,   2,     1,	  0,	 false)

MUX_CFG(DM355,	SD1_CLK,	3,   6,     1,	  1,	 false)
MUX_CFG(DM355,	SD1_CMD,	3,   7,     1,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA3,	3,   8,     3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA2,	3,   10,    3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA1,	3,   12,    3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA0,	3,   14,    3,	  1,	 false)

MUX_CFG(DM355,	I2C_SDA,	3,   19,    1,	  1,	 false)
MUX_CFG(DM355,	I2C_SCL,	3,   20,    1,	  1,	 false)

MUX_CFG(DM355,	MCBSP0_BDX,	3,   0,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_X,	3,   1,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BFSX,	3,   2,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BDR,	3,   3,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_R,	3,   4,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BFSR,	3,   5,     1,	  1,	 false)

MUX_CFG(DM355,	SPI0_SDI,	4,   1,     1,    0,	 false)
MUX_CFG(DM355,	SPI0_SDENA0,	4,   0,     1,    0,	 false)
MUX_CFG(DM355,	SPI0_SDENA1,	3,   28,    1,    1,	 false)

INT_CFG(DM355,  INT_EDMA_CC,	      2,    1,    1,     false)
INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)

EVT_CFG(DM355,  EVT8_ASP1_TX,	      0,    1,    0,     false)
EVT_CFG(DM355,  EVT9_ASP1_RX,	      1,    1,    0,     false)
Beispiel #5
0
static struct mux_config rk30_muxs[] = {
/*
 *	 description				mux  mode   mux	  mux  
 *						reg  offset inter mode
 */

//GPIO0C
MUX_CFG(GPIO0C7_FLASHDATA15_NAME, 			GPIO0C,   14,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0C6_FLASHDATA14_NAME, 			GPIO0C,   12,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0C5_FLASHDATA13_NAME,			GPIO0C,   10,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0C4_FLASHDATA12_NAME,			GPIO0C,   8,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0C3_FLASHDATA11_NAME, 			GPIO0C,   6,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0C2_FLASHDATA10_NAME,			GPIO0C,   4,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0C1_FLASHDATA9_NAME,			GPIO0C,   2,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0C0_FLASHDATA8_NAME,			GPIO0C,   0,	 1,   0,	DEFAULT)

//GPIO0D
MUX_CFG(GPIO0D7_SPI1CSN0_NAME,				GPIO0D,   14,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0D6_SPI1CLK_NAME,				GPIO0D,   12,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0D5_SPI1TXD_NAME,				GPIO0D,   10,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0D4_SPI1RXD_NAME,				GPIO0D,   8,	 1,   0,	DEFAULT)
MUX_CFG(GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME, 		GPIO0D,   6,	 2,   0,	DEFAULT)
MUX_CFG(GPIO0D2_FLASHCSN2_EMMCCMD_NAME,			GPIO0D,   4,	 2,   0,	DEFAULT)
MUX_CFG(GPIO0D1_FLASHCSN1_NAME,				GPIO0D,   2,	 2,   0,	DEFAULT)
MUX_CFG(GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME,		GPIO0D,   0,	 2,   0,	DEFAULT)

//GPIO1A
MUX_CFG(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, 		GPIO1A,   14,	 2,   0,	DEFAULT)
MUX_CFG(GPIO1A6_UART1CTSN_SPI0CLK_NAME, 		GPIO1A,   12,	 2,   0,	DEFAULT)
MUX_CFG(GPIO1A5_UART1SOUT_SPI0TXD_NAME, 		GPIO1A,   10,	 2,   0,	DEFAULT)
MUX_CFG(GPIO1A4_UART1SIN_SPI0RXD_NAME, 			GPIO1A,   8,	 2,   0,	DEFAULT)
Beispiel #6
0
static struct platform_device dm644x_mdio_device = {
	.name		= "davinci_mdio",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(dm644x_mdio_resources),
	.resource	= dm644x_mdio_resources,
};

/*
 * Device specific mux setup
 *
 *	soc	description	mux  mode   mode  mux	 dbg
 *				reg  offset mask  mode
 */
static const struct mux_config dm644x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM644X, HDIREN,		0,   16,    1,	  1,	 true)
MUX_CFG(DM644X, ATAEN,		0,   17,    1,	  1,	 true)
MUX_CFG(DM644X, ATAEN_DISABLE,	0,   17,    1,	  0,	 true)

MUX_CFG(DM644X, HPIEN_DISABLE,	0,   29,    1,	  0,	 true)

MUX_CFG(DM644X, AEAW,		0,   0,     31,	  31,	 true)
MUX_CFG(DM644X, AEAW0,		0,   0,     1,	  0,	 true)
MUX_CFG(DM644X, AEAW1,		0,   1,     1,	  0,	 true)
MUX_CFG(DM644X, AEAW2,		0,   2,     1,	  0,	 true)
MUX_CFG(DM644X, AEAW3,		0,   3,     1,	  0,	 true)
MUX_CFG(DM644X, AEAW4,		0,   4,     1,	  0,	 true)

MUX_CFG(DM644X, MSTK,		1,   9,     1,	  0,	 false)

MUX_CFG(DM644X, I2C,		1,   7,     1,	  1,	 false)
	CLK(NULL,		"ecap",		&ecap_clk),
	CLK(NULL,               "usb11",        &usb11_clk),
	CLK(NULL,               "usb20",        &usb20_clk),
	CLK(NULL,		NULL,		NULL),
};

/*
 * Device specific mux setup
 *
 *		soc	description	mux	mode	mode	mux	dbg
 *					reg	offset	mask	mode
 */
static const struct mux_config da850_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
	/* UART0 function */
	MUX_CFG(DA850, NUART0_CTS,	3,	24,	15,	2,	false)
	MUX_CFG(DA850, NUART0_RTS,	3,	28,	15,	2,	false)
	MUX_CFG(DA850, UART0_RXD,	3,	16,	15,	2,	false)
	MUX_CFG(DA850, UART0_TXD,	3,	20,	15,	2,	false)
	/* UART1 function */
	MUX_CFG(DA850, NUART1_CTS,	0,	20,	15,	4,	false)
	MUX_CFG(DA850, NUART1_RTS,	0,	16,	15,	4,	false)
	MUX_CFG(DA850, UART1_RXD,	4,	24,	15,	2,	false)
	MUX_CFG(DA850, UART1_TXD,	4,	28,	15,	2,	false)
	/* UART2 function */
	MUX_CFG(DA850, UART2_RXD,	4,	16,	15,	2,	false)
	MUX_CFG(DA850, UART2_TXD,	4,	20,	15,	2,	false)
	/* I2C1 function */
	MUX_CFG(DA850, I2C1_SCL,	4,	16,	15,	4,	false)
	MUX_CFG(DA850, I2C1_SDA,	4,	20,	15,	4,	false)
	/* I2C0 function */
MUX_CFG_7XX("SPI_7XX_5",           8,   25,    0,   24,   0, 0)
MUX_CFG_7XX("SPI_7XX_6",           9,    5,    0,    4,   0, 0)
};
#define OMAP7XX_PINS_SZ		ARRAY_SIZE(omap7xx_pins)
#else
#define omap7xx_pins		NULL
#define OMAP7XX_PINS_SZ		0
#endif	/* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */

#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static struct pin_config __initdata_or_module omap1xxx_pins[] = {
/*
 *	 description		mux  mode   mux	 pull pull  pull  pu_pd	 pu  dbg
 *				reg  offset mode reg  bit   ena	  reg
 */
MUX_CFG("UART1_TX",		 9,   21,    1,	  2,   3,   0,	 NA,	 0,  0)
MUX_CFG("UART1_RTS",		 9,   12,    1,	  2,   0,   0,	 NA,	 0,  0)

/* UART2 (COM_UART_GATING), conflicts with USB2 */
MUX_CFG("UART2_TX",		 C,   27,    1,	  3,   3,   0,	 NA,	 0,  0)
MUX_CFG("UART2_RX",		 C,   18,    0,	  3,   1,   1,	 NA,	 0,  0)
MUX_CFG("UART2_CTS",		 C,   21,    0,	  3,   1,   1,	 NA,	 0,  0)
MUX_CFG("UART2_RTS",		 C,   24,    1,	  3,   2,   0,	 NA,	 0,  0)

/* UART3 (GIGA_UART_GATING) */
MUX_CFG("UART3_TX",		 6,    0,    1,	  0,  30,   0,	 NA,	 0,  0)
MUX_CFG("UART3_RX",		 6,    3,    0,	  0,  31,   1,	 NA,	 0,  0)
MUX_CFG("UART3_CTS",		 5,   12,    2,	  0,  24,   0,	 NA,	 0,  0)
MUX_CFG("UART3_RTS",		 5,   15,    2,	  0,  25,   0,	 NA,	 0,  0)
MUX_CFG("UART3_CLKREQ",		 9,   27,    0,	  2,   5,   0,	 NA,	 0,  0)
MUX_CFG("UART3_BCLK",		 A,    0,    0,	  2,   6,   0,	 NA,	 0,  0)
	CLK(NULL,		"usb20",	&usb20_clk),
	CLK("spi_davinci.0",	NULL,		&spi0_clk),
	CLK("spi_davinci.1",	NULL,		&spi1_clk),
	CLK(NULL,		NULL,		NULL),
};

/*
 * Device specific mux setup
 *
 *		soc	description	mux	mode	mode	mux	dbg
 *					reg	offset	mask	mode
 */
static const struct mux_config da850_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
	/* UART0 function */
	MUX_CFG(DA850, NUART0_CTS,	3,	24,	15,	2,	false)
	MUX_CFG(DA850, NUART0_RTS,	3,	28,	15,	2,	false)
	MUX_CFG(DA850, UART0_RXD,	3,	16,	15,	2,	false)
	MUX_CFG(DA850, UART0_TXD,	3,	20,	15,	2,	false)
	/* UART1 function */
	MUX_CFG(DA850, UART1_RXD,	4,	24,	15,	2,	false)
	MUX_CFG(DA850, UART1_TXD,	4,	28,	15,	2,	false)
	/* UART2 function */
	MUX_CFG(DA850, UART2_RXD,	4,	16,	15,	2,	false)
	MUX_CFG(DA850, UART2_TXD,	4,	20,	15,	2,	false)
	/* I2C1 function */
	MUX_CFG(DA850, I2C1_SCL,	4,	16,	15,	4,	false)
	MUX_CFG(DA850, I2C1_SDA,	4,	20,	15,	4,	false)
	/* I2C0 function */
	MUX_CFG(DA850, I2C0_SDA,	4,	12,	15,	2,	false)
	MUX_CFG(DA850, I2C0_SCL,	4,	8,	15,	2,	false)
Beispiel #10
0
	CLK("davinci_voicecodec", NULL, &voicecodec_clk),
	CLK("davinci-mcbsp", NULL, &asp0_clk),
	CLK(NULL, "rto", &rto_clk),
	CLK(NULL, "mjcp", &mjcp_clk),
	CLK(NULL, NULL, NULL),
};

/*----------------------------------------------------------------------*/

#define INTMUX		0x18
#define EVTMUX		0x1c


static const struct mux_config dm365_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM365,	MMCSD0,		0,   24,     1,	  0,	 false)

MUX_CFG(DM365,	SD1_CLK,	0,   16,    3,	  1,	 false)
MUX_CFG(DM365,	SD1_CMD,	4,   30,    3,	  1,	 false)
MUX_CFG(DM365,	SD1_DATA3,	4,   28,    3,	  1,	 false)
MUX_CFG(DM365,	SD1_DATA2,	4,   26,    3,	  1,	 false)
MUX_CFG(DM365,	SD1_DATA1,	4,   24,    3,	  1,	 false)
MUX_CFG(DM365,	SD1_DATA0,	4,   22,    3,	  1,	 false)

MUX_CFG(DM365,	I2C_SDA,	3,   23,    3,	  2,	 false)
MUX_CFG(DM365,	I2C_SCL,	3,   21,    3,	  2,	 false)

MUX_CFG(DM365,	AEMIF_AR_A14,	2,   0,     3,	  1,	 false)
MUX_CFG(DM365,	AEMIF_AR_BA0,	2,   0,     3,	  2,	 false)
MUX_CFG(DM365,	AEMIF_A3,	2,   2,     3,	  1,	 false)
MUX_CFG(DM365,	AEMIF_A7,	2,   4,     3,	  1,	 false)
Beispiel #11
0
};

/*----------------------------------------------------------------------*/

#define PINMUX0		0x00
#define PINMUX1		0x04
#define PINMUX2		0x08
#define PINMUX3		0x0c
#define PINMUX4		0x10
#define INTMUX		0x18
#define EVTMUX		0x1c


static const struct mux_config dm365_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM365,	MMCSD0,		0,   24,     1,	  0,	 false)

MUX_CFG(DM365,	SD1_CLK,	0,   16,    3,	  1,	 false)
MUX_CFG(DM365,	SD1_CMD,	4,   30,    3,	  1,	 false)
MUX_CFG(DM365,	SD1_DATA3,	4,   28,    3,	  1,	 false)
MUX_CFG(DM365,	SD1_DATA2,	4,   26,    3,	  1,	 false)
MUX_CFG(DM365,	SD1_DATA1,	4,   24,    3,	  1,	 false)
MUX_CFG(DM365,	SD1_DATA0,	4,   22,    3,	  1,	 false)

MUX_CFG(DM365,	I2C_SDA,	3,   23,    3,	  2,	 false)
MUX_CFG(DM365,	I2C_SCL,	3,   21,    3,	  2,	 false)

MUX_CFG(DM365,	AEMIF_CE0,	2,   7,     1,	  0,	 false)
MUX_CFG(DM365,	AEMIF_CE1,	2,   8,     1,	  0,	 false)

Beispiel #12
0
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/mux.h>

/*
 * DM644x and DM6467 have 2 PinMux registers, DM355 has 5 PinMux registers.
 * Allocate the maximum.
 */
static unsigned long pinmux_in_use[5];

const struct pin_config __initdata_or_module davinci_dm644x_pinmux[] = {
/*
 *	 description		mux  mode   mode  mux	 dbg
 *				reg  offset mask  mode
 */
MUX_CFG("HDIREN",		 0,   16,    1,	  1,	 1)
MUX_CFG("ATAEN",		 0,   17,    1,	  1,	 1)

MUX_CFG("MSTK",			 1,   9,     1,	  0,	 0)

MUX_CFG("I2C",			 1,   7,     1,	  1,	 0)

MUX_CFG("MCBSP",		 1,   10,    1,	  1,	 0)

MUX_CFG("PWM0",			 1,   4,     1,	  1,	 0)

MUX_CFG("PWM1",			 1,   5,     1,	  1,	 0)

MUX_CFG("PWM2",			 1,   6,     1,	  1,	 0)

MUX_CFG("VLINQEN",		 0,   15,    1,	  1,	 0)