void Map42_Write( word wAddr, byte byData )
{
switch ( wAddr & 0xe003 )
{
/* Set ROM Banks */
case 0xe000:
W.SRAMBANK = ROMPAGE( ( byData & 0x0f ) % ( S.NesHeader.ROMSize << 1 ) );
break;
case 0xe001:
if ( byData & 0x08 )
{
NESCore_Mirroring( 0 );
} else {
NESCore_Mirroring( 1 );
}
break;
case 0xe002:
if ( byData & 0x02 )
{
Map42_IRQ_Enable = 1;
} else {
Map42_IRQ_Enable = 0;
Map42_IRQ_Cnt = 0;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map78_Write( word wAddr, byte byData )
{
byte byPrgBank = byData & 0x0f;
byte byChrBank = ( byData & 0xf0 ) >> 4;
/* Set ROM Banks */
byPrgBank <<= 1;
byPrgBank %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK0 = ROMPAGE( byPrgBank );
W.ROMBANK1 = ROMPAGE( byPrgBank + 1);
/* Set PPU Banks */
byChrBank <<= 3;
byChrBank %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[0] = VROMPAGE( byChrBank );
W.PPUBANK[1] = VROMPAGE( byChrBank + 1 );
W.PPUBANK[2] = VROMPAGE( byChrBank + 2 );
W.PPUBANK[3] = VROMPAGE( byChrBank + 3 );
W.PPUBANK[4] = VROMPAGE( byChrBank + 4 );
W.PPUBANK[5] = VROMPAGE( byChrBank + 5 );
W.PPUBANK[6] = VROMPAGE( byChrBank + 6 );
W.PPUBANK[7] = VROMPAGE( byChrBank + 7 );
NESCore_Develop_Character_Data();
/* Set Name Table Mirroring */
if ( ( wAddr & 0xfe00 ) != 0xfe00 )
{
if ( byData & 0x08 )
{
NESCore_Mirroring( 2 );
} else {
NESCore_Mirroring( 3 );
}
}
}
void Map15_Write( word wAddr, byte bData )
{
byte byBank;
switch ( wAddr )
{
case 0x8000:
/* Name Table Mirroring */
NESCore_Mirroring( bData & 0x20 ? 0 : 1);
/* Set ROM Banks */
byBank = bData & 0x1f;
byBank %= ( S.NesHeader.ROMSize << 1 );
byBank <<= 1;
W.ROMBANK0 = ROMPAGE( byBank );
W.ROMBANK1 = ROMPAGE( byBank + 1 );
W.ROMBANK2 = ROMPAGE( byBank + 2 );
W.ROMBANK3 = ROMPAGE( byBank + 3 );
break;
case 0x8001:
/* Set ROM Banks */
bData &= 0x3f;
bData %= ( S.NesHeader.ROMSize << 1 );
bData <<= 1;
W.ROMBANK2 = ROMPAGE( bData );
W.ROMBANK3 = ROMPAGE( bData + 1 );
break;
case 0x8002:
/* Set ROM Banks */
byBank = bData & 0x3f;
byBank %= ( S.NesHeader.ROMSize << 1 );
byBank <<= 1;
byBank += ( bData & 0x80 ? 1 : 0 );
W.ROMBANK0 = ROMPAGE( byBank );
W.ROMBANK1 = ROMPAGE( byBank );
W.ROMBANK2 = ROMPAGE( byBank );
W.ROMBANK3 = ROMPAGE( byBank );
break;
case 0x8003:
/* Name Table Mirroring */
NESCore_Mirroring( bData & 0x20 ? 0 : 1);
/* Set ROM Banks */
bData &= 0x1f;
bData %= ( S.NesHeader.ROMSize << 1 );
bData <<= 1;
W.ROMBANK2 = ROMPAGE( bData );
W.ROMBANK3 = ROMPAGE( bData + 1 );
break;
}
}
/*-------------------------------------------------------------------*/
void Map135_Apu( word wAddr, byte byData )
{
switch( wAddr & 0x4101 ) {
case 0x4100:
Map135_Cmd = byData & 0x07;
break;
case 0x4101:
switch( Map135_Cmd ) {
case 0:
Map135_Chr0l = byData & 0x07;
Map135_Set_PPU_Banks();
break;
case 1:
Map135_Chr0h = byData & 0x07;
Map135_Set_PPU_Banks();
break;
case 2:
Map135_Chr1l = byData & 0x07;
Map135_Set_PPU_Banks();
break;
case 3:
Map135_Chr1h = byData & 0x07;
Map135_Set_PPU_Banks();
break;
case 4:
Map135_Chrch = byData & 0x07;
Map135_Set_PPU_Banks();
break;
case 5:
/* Set ROM Banks */
W.ROMBANK0 = ROMPAGE( (((byData%0x07)<<2) + 0 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK1 = ROMPAGE( (((byData%0x07)<<2) + 1 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK2 = ROMPAGE( (((byData%0x07)<<2) + 2 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK3 = ROMPAGE( (((byData%0x07)<<2) + 3 ) % (S.NesHeader.ROMSize << 1) );
break;
case 6:
break;
case 7:
switch( (byData>>1)&0x03 ) {
case 0: NESCore_Mirroring( 2 ); break;
case 1: NESCore_Mirroring( 0 ); break;
case 2: NESCore_Mirroring( 1 ); break;
case 3: NESCore_Mirroring( 2 ); break;
}
break;
}
break;
}
//Map135_Wram[ wAddr & 0x1fff ] = byData;
}
/*-------------------------------------------------------------------*/
void Map134_Apu( word wAddr, byte byData )
{
switch( wAddr & 0x4101 ) {
case 0x4100:
Map134_Cmd = byData & 0x07;
break;
case 0x4101:
switch( Map134_Cmd ) {
case 0:
Map134_Prg = 0;
Map134_Chr = 3;
break;
case 4:
Map134_Chr &= 0x3;
Map134_Chr |= (byData & 0x07) << 2;
break;
case 5:
Map134_Prg = byData & 0x07;
break;
case 6:
Map134_Chr &= 0x1C;
Map134_Chr |= byData & 0x3;
break;
case 7:
if( byData & 0x01 ) NESCore_Mirroring( 0 );
else NESCore_Mirroring( 1 );
break;
}
break;
}
/* Set ROM Banks */
W.ROMBANK0 = ROMPAGE( ((Map134_Prg<<2) + 0 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK1 = ROMPAGE( ((Map134_Prg<<2) + 1 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK2 = ROMPAGE( ((Map134_Prg<<2) + 2 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK3 = ROMPAGE( ((Map134_Prg<<2) + 3 ) % (S.NesHeader.ROMSize << 1) );
/* Set PPU Banks */
W.PPUBANK[0] = VROMPAGE( ((Map134_Chr<<3) + 0) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[1] = VROMPAGE( ((Map134_Chr<<3) + 1) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[2] = VROMPAGE( ((Map134_Chr<<3) + 2) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[3] = VROMPAGE( ((Map134_Chr<<3) + 3) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[4] = VROMPAGE( ((Map134_Chr<<3) + 4) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[5] = VROMPAGE( ((Map134_Chr<<3) + 5) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[6] = VROMPAGE( ((Map134_Chr<<3) + 6) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[7] = VROMPAGE( ((Map134_Chr<<3) + 7) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
//Map134_Wram[wAddr & 0x1fff] = byData;
}
/*-------------------------------------------------------------------*/
void Map91_Init()
{
/* Initialize Mapper */
MapperInit = Map91_Init;
/* Write to Mapper */
MapperWrite = Map0_Write;
/* Write to SRAM */
MapperSram = Map91_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
W.SRAMBANK = S.SRAM;
/* Set ROM Banks */
W.ROMBANK0 = ROMLASTPAGE( 1 );
W.ROMBANK1 = ROMLASTPAGE( 0 );
W.ROMBANK2 = ROMLASTPAGE( 1 );
W.ROMBANK3 = ROMLASTPAGE( 0 );
/* Set PPU Banks */
if ( S.NesHeader.VROMSize > 0 )
{
int nPage ;
for (nPage = 0; nPage < 8; ++nPage )
W.PPUBANK[ nPage ] = VROMPAGE( nPage );
NESCore_Develop_Character_Data();
}
/* Set Name Table Mirroring */
NESCore_Mirroring( 1 );
}
/*-------------------------------------------------------------------*/
void Map97_Write( word wAddr, byte byData )
{
/* Set ROM Banks */
if ( wAddr < 0xc000 )
{
byte byPrgBank = byData & 0x0f;
byPrgBank <<= 1;
byPrgBank %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK2 = ROMPAGE( byPrgBank );
W.ROMBANK3 = ROMPAGE( byPrgBank + 1 );
if ( ( byData & 0x80 ) == 0 )
{
NESCore_Mirroring( 0 );
} else {
NESCore_Mirroring( 1 );
}
}
}
void Map71_Write( word wAddr, byte byData )
{
switch ( wAddr & 0xf000 )
{
case 0x9000:
if ( byData & 0x10 )
{
NESCore_Mirroring( 2 );
} else {
NESCore_Mirroring( 3 );
}
break;
/* Set ROM Banks */
case 0xc000:
case 0xd000:
case 0xe000:
case 0xf000:
W.ROMBANK0 = ROMPAGE( ( ( byData << 1 ) + 0 ) % ( S.NesHeader.ROMSize << 1 ) );
W.ROMBANK1 = ROMPAGE( ( ( byData << 1 ) + 1 ) % ( S.NesHeader.ROMSize << 1 ) );
break;
}
}
void Map7_Write( word wAddr, byte bData )
{
byte byBank;
/* Set ROM Banks */
byBank = ( bData & 0x07 ) << 2;
byBank %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK0 = ROMPAGE( byBank );
W.ROMBANK1 = ROMPAGE( byBank + 1 );
W.ROMBANK2 = ROMPAGE( byBank + 2 );
W.ROMBANK3 = ROMPAGE( byBank + 3 );
NESCore_Mirroring( bData & 0x10 ? 2 : 3 );
}
void Map46_Init()
{
MapperInit = Map46_Init;
MapperWrite = Map46_Write;
MapperSram = Map46_Sram;
MapperApu = Map0_Apu;
MapperReadApu = Map0_ReadApu;
MapperVSync = Map0_VSync;
MapperHSync = Map0_HSync;
MapperPPU = Map0_PPU;
MapperRenderScreen = Map0_RenderScreen;
W.SRAMBANK = S.SRAM;
Map46_Regs[ 0 ] = Map46_Regs[ 1 ] = Map46_Regs[ 2 ] = Map46_Regs[ 3 ] = 0;
Map46_Set_ROM_Banks();
/* Name Table Mirroring */
NESCore_Mirroring( 1 );
}
void Map68_SyncMirror( void )
{
if ( Map68_Regs[ 0 ] )
{
switch( Map68_Regs[ 1 ] )
{
case 0x00:
W.PPUBANK[ 8 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
W.PPUBANK[ 9 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
W.PPUBANK[ 10 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
W.PPUBANK[ 11 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
break;
case 0x01:
W.PPUBANK[ 8 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
W.PPUBANK[ 9 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
W.PPUBANK[ 10 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
W.PPUBANK[ 11 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
break;
case 0x02:
W.PPUBANK[ 8 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
W.PPUBANK[ 9 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
W.PPUBANK[ 10 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
W.PPUBANK[ 11 ] = VROMPAGE( Map68_Regs[ 2 ] + 0x80 );
break;
case 0x03:
W.PPUBANK[ 8 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
W.PPUBANK[ 9 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
W.PPUBANK[ 10 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
W.PPUBANK[ 11 ] = VROMPAGE( Map68_Regs[ 3 ] + 0x80 );
break;
}
NESCore_Develop_Character_Data();
}
else
{
NESCore_Mirroring( Map68_Regs[ 1 ] );
}
}
void Map32_Write( word wAddr, byte byData )
{
switch ( wAddr & 0xf000 )
{
case 0x8000:
/* Set ROM Banks */
byData %= ( S.NesHeader.ROMSize << 1 );
if ( Map32_Saved & 0x02 )
{
W.ROMBANK2 = ROMPAGE( byData );
} else {
W.ROMBANK0 = ROMPAGE( byData );
}
break;
case 0x9000:
Map32_Saved = byData;
// Name Table Mirroring
NESCore_Mirroring( byData & 0x01 );
break;
case 0xa000:
/* Set ROM Banks */
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK1 = ROMPAGE( byData );
break;
case 0xb000:
/* Set PPU Banks */
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ wAddr & 0x0007 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
default:
break;
}
}
void Map18_Write( word wAddr, byte byData )
{
switch( wAddr )
{
/* Set ROM Banks */
case 0x8000:
Map18_Regs[ 0 ] = ( Map18_Regs[ 0 ] & 0xf0 ) | ( byData & 0x0f );
W.ROMBANK0 = ROMPAGE( Map18_Regs[ 0 ] % ( S.NesHeader.ROMSize << 1 ) );
break;
case 0x8001:
Map18_Regs[ 0 ] = ( Map18_Regs[ 0 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.ROMBANK0 = ROMPAGE( Map18_Regs[ 0 ] % ( S.NesHeader.ROMSize << 1 ) );
break;
case 0x8002:
Map18_Regs[ 1 ] = ( Map18_Regs[ 1 ] & 0xf0 ) | ( byData & 0x0f );
W.ROMBANK1 = ROMPAGE( Map18_Regs[ 1 ] % ( S.NesHeader.ROMSize << 1 ) );
break;
case 0x8003:
Map18_Regs[ 1 ] = ( Map18_Regs[ 1 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.ROMBANK1 = ROMPAGE( Map18_Regs[ 1 ] % ( S.NesHeader.ROMSize << 1 ) );
break;
case 0x9000:
Map18_Regs[ 2 ] = ( Map18_Regs[ 2 ] & 0xf0 ) | ( byData & 0x0f );
W.ROMBANK2 = ROMPAGE( Map18_Regs[ 2 ] % ( S.NesHeader.ROMSize << 1 ) );
break;
case 0x9001:
Map18_Regs[ 2 ] = ( Map18_Regs[ 2 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.ROMBANK2 = ROMPAGE( Map18_Regs[ 2 ] % ( S.NesHeader.ROMSize << 1 ) );
break;
/* Set PPU Banks */
case 0xA000:
Map18_Regs[ 3 ] = ( Map18_Regs[ 3 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 0 ] = VROMPAGE( Map18_Regs[ 3 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xA001:
Map18_Regs[ 3 ] = ( Map18_Regs[ 3 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 0 ] = VROMPAGE( Map18_Regs[ 3 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xA002:
Map18_Regs[ 4 ] = ( Map18_Regs[ 4 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 1 ] = VROMPAGE( Map18_Regs[ 4 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xA003:
Map18_Regs[ 4 ] = ( Map18_Regs[ 4 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 1 ] = VROMPAGE( Map18_Regs[ 4 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xB000:
Map18_Regs[ 5 ] = ( Map18_Regs[ 5 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 2 ] = VROMPAGE( Map18_Regs[ 5 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xB001:
Map18_Regs[ 5 ] = ( Map18_Regs[ 5 ] &0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 2 ] = VROMPAGE( Map18_Regs[ 5 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xB002:
Map18_Regs[ 6 ] = ( Map18_Regs[ 6 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 3 ] = VROMPAGE( Map18_Regs[ 6 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xB003:
Map18_Regs[ 6 ] = ( Map18_Regs[ 6 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 3 ] = VROMPAGE( Map18_Regs[ 6 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xC000:
Map18_Regs[ 7 ] = ( Map18_Regs[ 7 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 4 ] = VROMPAGE( Map18_Regs[ 7 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xC001:
Map18_Regs[ 7 ] = ( Map18_Regs[ 7 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 4 ] = VROMPAGE( Map18_Regs[ 7 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xC002:
Map18_Regs[ 8 ] = ( Map18_Regs[ 8 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 5 ] = VROMPAGE( Map18_Regs[ 8 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xC003:
Map18_Regs[ 8 ] = ( Map18_Regs[ 8 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 5 ] = VROMPAGE( Map18_Regs[ 8 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xD000:
Map18_Regs[ 9 ] = ( Map18_Regs[ 9 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 6 ] = VROMPAGE( Map18_Regs[ 9 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xD001:
Map18_Regs[ 9 ] = ( Map18_Regs[ 9 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 6 ] = VROMPAGE( Map18_Regs[ 9 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xD002:
Map18_Regs[ 10 ] = ( Map18_Regs[ 10 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 7 ] = VROMPAGE( Map18_Regs[ 10 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xD003:
Map18_Regs[ 10 ] = ( Map18_Regs[ 10 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 7 ] = VROMPAGE( Map18_Regs[ 10 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xE000:
Map18_IRQ_Latch = ( Map18_IRQ_Latch & 0xfff0 ) | ( byData & 0x0f );
break;
case 0xE001:
Map18_IRQ_Latch = ( Map18_IRQ_Latch & 0xff0f ) | ( ( byData & 0x0f ) << 4 );
break;
case 0xE002:
Map18_IRQ_Latch = ( Map18_IRQ_Latch & 0xf0ff ) | ( ( byData & 0x0f ) << 8 );
break;
case 0xE003:
Map18_IRQ_Latch = ( Map18_IRQ_Latch & 0x0fff ) | ( ( byData & 0x0f ) << 12 );
break;
case 0xF000:
if ( ( byData & 0x01 ) == 0 )
{
Map18_IRQ_Cnt = 0;
} else {
Map18_IRQ_Cnt = Map18_IRQ_Latch;
}
break;
case 0xF001:
Map18_IRQ_Enable = byData & 0x01;
break;
/* Name Table Mirroring */
case 0xF002:
switch ( byData & 0x03 )
{
case 0:
NESCore_Mirroring( 0 ); /* Horizontal */
break;
case 1:
NESCore_Mirroring( 1 ); /* Vertical */
break;
case 2:
NESCore_Mirroring( 3 ); /* One Screen 0x2000 */
break;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map88_Write( word wAddr, byte byData )
{
switch ( wAddr )
{
case 0x8000:
Map88_Regs[ 0 ] = byData;
break;
case 0x8001:
switch ( Map88_Regs[ 0 ] & 0x07 )
{
case 0x00:
W.PPUBANK[ 0 ] = VROMPAGE( ( ( byData & 0xfe ) + 0 ) % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 1 ] = VROMPAGE( ( ( byData & 0xfe ) + 1 ) % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0x01:
W.PPUBANK[ 2 ] = VROMPAGE( ( ( byData & 0xfe ) + 0 ) % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 3 ] = VROMPAGE( ( ( byData & 0xfe ) + 1 ) % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0x02:
W.PPUBANK[ 4 ] = VROMPAGE( ( byData + 0x40 ) % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0x03:
W.PPUBANK[ 5 ] = VROMPAGE( ( byData + 0x40 ) % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0x04:
W.PPUBANK[ 6 ] = VROMPAGE( ( byData + 0x40 ) % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0x05:
W.PPUBANK[ 7 ] = VROMPAGE( ( byData + 0x40 ) % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0x06:
W.ROMBANK0 = ROMPAGE( byData % ( S.NesHeader.ROMSize << 1 ) );
break;
case 0x07:
W.ROMBANK1 = ROMPAGE( byData % ( S.NesHeader.ROMSize << 1 ) );
break;
}
break;
case 0xc000:
if ( byData )
{
NESCore_Mirroring( 2 );
} else {
NESCore_Mirroring( 3 );
}
break;
}
}
void Map26_Write( word wAddr, byte byData )
{
switch ( wAddr )
{
/* Set ROM Banks */
case 0x8000:
byData <<= 1;
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK0 = ROMPAGE( byData + 0 );
W.ROMBANK1 = ROMPAGE( byData + 1 );
break;
/* Name Table Mirroring */
case 0xb003:
switch ( byData & 0x7f )
{
case 0x08:
case 0x2c:
NESCore_Mirroring( 2 ); /* One Screen 0x2400 */
break;
case 0x20:
NESCore_Mirroring( 1 ); /* Vertical */
break;
case 0x24:
NESCore_Mirroring( 0 ); /* Horizontal */
break;
case 0x28:
NESCore_Mirroring( 3 ); /* One Screen 0x2000 */
break;
}
break;
case 0xc000:
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK2 = ROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xd000:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 0 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xd001:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 2 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xd002:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 1 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xd003:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 3 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xe000:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 4 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xe001:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 6 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xe002:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 5 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xe003:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 7 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
/* Set IRQ Registers */
case 0xf000:
Map26_IRQ_Latch = byData;
break;
case 0xf001:
Map26_IRQ_Enable = byData & 0x01;
break;
case 0xf002:
Map26_IRQ_Enable = byData & 0x03;
if ( Map26_IRQ_Enable & 0x02 )
{
Map26_IRQ_Cnt = Map26_IRQ_Latch;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map112_Write( word wAddr, byte byData )
{
dword dwBankNum;
/* Set ROM Banks */
switch( wAddr & 0xE001 )
{
case 0x8000:
Map112_Regs[0] = byData;
Map112_Set_PPU_Banks();
Map112_Set_CPU_Banks();
break;
case 0xA000:
Map112_Regs[1] = byData;
dwBankNum = Map112_Regs[1];
switch ( Map112_Regs[0] & 0x07 )
{
case 0x02:
if ( S.NesHeader.VROMSize > 0 )
{
dwBankNum &= 0xfe;
Map112_Chr01 = dwBankNum;
Map112_Set_PPU_Banks();
}
break;
case 0x03:
if ( S.NesHeader.VROMSize > 0 )
{
dwBankNum &= 0xfe;
Map112_Chr23 = dwBankNum;
Map112_Set_PPU_Banks();
}
break;
case 0x04:
if ( S.NesHeader.VROMSize > 0 )
{
Map112_Chr4 = dwBankNum;
Map112_Set_PPU_Banks();
}
break;
case 0x05:
if ( S.NesHeader.VROMSize > 0 )
{
Map112_Chr5 = dwBankNum;
Map112_Set_PPU_Banks();
}
break;
case 0x06:
if ( S.NesHeader.VROMSize > 0 )
{
Map112_Chr6 = dwBankNum;
Map112_Set_PPU_Banks();
}
break;
case 0x07:
if ( S.NesHeader.VROMSize > 0 )
{
Map112_Chr7 = dwBankNum;
Map112_Set_PPU_Banks();
}
break;
case 0x00:
Map112_Prg0 = dwBankNum;
Map112_Set_CPU_Banks();
break;
case 0x01:
Map112_Prg1 = dwBankNum;
Map112_Set_CPU_Banks();
break;
}
break;
case 0x8001:
Map112_Regs[2] = byData;
if ( !S.ROM_FourScr )
{
if ( byData & 0x01 )
{
NESCore_Mirroring( 1 ); /* Vertical */
}
else
{
NESCore_Mirroring( 0 ); /* Horizontal */
}
}
break;
case 0xA001:
Map112_Regs[3] = byData;
break;
case 0xC000:
Map112_Regs[4] = byData;
Map112_IRQ_Cnt = Map112_Regs[4];
break;
case 0xC001:
Map112_Regs[5] = byData;
Map112_IRQ_Latch = Map112_Regs[5];
break;
case 0xE000:
Map112_Regs[6] = byData;
Map112_IRQ_Enable = 0;
if ( byData )
{
NESCore_Mirroring( 0 ); /* Horizontal */
}
else
{
NESCore_Mirroring( 1 ); /* Vertical */
}
break;
case 0xE001:
Map112_Regs[7] = byData;
Map112_IRQ_Enable = 1;
break;
}
}
void Map22_Write( word wAddr, byte byData )
{
switch ( wAddr )
{
case 0x8000:
/* Set ROM Banks */
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK0 = ROMPAGE( byData );
break;
case 0x9000:
/* Name Table Mirroring */
switch ( byData & 0x03 )
{
case 0:
NESCore_Mirroring( 1 ); /* Vertical */
break;
case 1:
NESCore_Mirroring( 0 ); /* Horizontal */
break;
case 2:
NESCore_Mirroring( 2 ); /* One Screen 0x2000 */
break;
case 3:
NESCore_Mirroring( 3 ); /* One Screen 0x2400 */
break;
}
break;
case 0xa000:
/* Set ROM Banks */
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK1 = ROMPAGE( byData );
break;
case 0xb000:
/* Set PPU Banks */
byData >>= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 0 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xb001:
/* Set PPU Banks */
byData >>= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 1 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xc000:
/* Set PPU Banks */
byData >>= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 2 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xc001:
/* Set PPU Banks */
byData >>= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 3 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xd000:
/* Set PPU Banks */
byData >>= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 4 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xd001:
/* Set PPU Banks */
byData >>= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 5 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xe000:
/* Set PPU Banks */
byData >>= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 6 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0xe001:
/* Set PPU Banks */
byData >>= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 7 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
}
}
/*-------------------------------------------------------------------*/
void Map248_Write( word wAddr, byte byData )
{
switch( wAddr & 0xE001 ) {
case 0x8000:
Map248_Reg[0] = byData;
Map248_Set_CPU_Banks();
Map248_Set_PPU_Banks();
break;
case 0x8001:
Map248_Reg[1] = byData;
switch( Map248_Reg[0] & 0x07 ) {
case 0x00:
Map248_Chr01 = byData & 0xFE;
Map248_Set_PPU_Banks();
break;
case 0x01:
Map248_Chr23 = byData & 0xFE;
Map248_Set_PPU_Banks();
break;
case 0x02:
Map248_Chr4 = byData;
Map248_Set_PPU_Banks();
break;
case 0x03:
Map248_Chr5 = byData;
Map248_Set_PPU_Banks();
break;
case 0x04:
Map248_Chr6 = byData;
Map248_Set_PPU_Banks();
break;
case 0x05:
Map248_Chr7 = byData;
Map248_Set_PPU_Banks();
break;
case 0x06:
Map248_Prg0 = byData;
Map248_Set_CPU_Banks();
break;
case 0x07:
Map248_Prg1 = byData;
Map248_Set_CPU_Banks();
break;
}
break;
case 0xA000:
Map248_Reg[2] = byData;
if( !S.ROM_FourScr ) {
if( byData & 0x01 ) {
NESCore_Mirroring( 0 );
} else {
NESCore_Mirroring( 1 );
}
}
break;
case 0xC000:
Map248_IRQ_Enable=0;
Map248_IRQ_Latch=0xBE;
Map248_IRQ_Counter =0xBE;
break;
case 0xC001:
Map248_IRQ_Enable=1;
Map248_IRQ_Latch=0xBE;
Map248_IRQ_Counter=0xBE;
break;
}
}
void Map21_Write( word wAddr, byte byData )
{
switch ( wAddr & 0xf00f )
{
/* Set ROM Banks */
case 0x8000:
if ( Map21_Regs[ 8 ] & 0x02 )
{
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK2 = ROMPAGE( byData );
} else {
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK0 = ROMPAGE( byData );
}
break;
case 0xa000:
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK1 = ROMPAGE( byData );
break;
/* Name Table Mirroring */
case 0x9000:
switch ( byData & 0x03 )
{
case 0:
NESCore_Mirroring( 1 );
break;
case 1:
NESCore_Mirroring( 0 );
break;
case 2:
NESCore_Mirroring( 3 );
break;
case 3:
NESCore_Mirroring( 2 );
break;
}
break;
case 0x9002:
Map21_Regs[ 8 ] = byData;
break;
case 0xb000:
Map21_Regs[ 0 ] = ( Map21_Regs[ 0 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 0 ] = VROMPAGE( Map21_Regs[ 0 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xb002:
Map21_Regs[ 0 ] = ( Map21_Regs[ 0 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 0 ] = VROMPAGE( Map21_Regs[ 0 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xb001:
case 0xb004:
Map21_Regs[ 1 ] = ( Map21_Regs[ 1 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 1 ] = VROMPAGE( Map21_Regs[ 1 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xb003:
case 0xb006:
Map21_Regs[ 1 ] = ( Map21_Regs[ 1 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 1 ] = VROMPAGE( Map21_Regs[ 1 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xc000:
Map21_Regs[ 2 ] = ( Map21_Regs[ 2 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 2 ] = VROMPAGE( Map21_Regs[ 2 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xc002:
Map21_Regs[ 2 ] = ( Map21_Regs[ 2 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 2 ] = VROMPAGE( Map21_Regs[ 2 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xc001:
case 0xc004:
Map21_Regs[ 3 ] = ( Map21_Regs[ 3 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 3 ] = VROMPAGE( Map21_Regs[ 3 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xc003:
case 0xc006:
Map21_Regs[ 3 ] = ( Map21_Regs[ 3 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 3 ] = VROMPAGE( Map21_Regs[ 3 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xd000:
Map21_Regs[ 4 ] = ( Map21_Regs[ 4 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 4 ] = VROMPAGE( Map21_Regs[ 4 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xd002:
Map21_Regs[ 4 ] = ( Map21_Regs[ 4 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 4 ] = VROMPAGE( Map21_Regs[ 4 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xd001:
case 0xd004:
Map21_Regs[ 5 ] = ( Map21_Regs[ 5 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 5 ] = VROMPAGE( Map21_Regs[ 5 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xd003:
case 0xd006:
Map21_Regs[ 5 ] = ( Map21_Regs[ 5 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 5 ] = VROMPAGE( Map21_Regs[ 5 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xe000:
Map21_Regs[ 6 ] = ( Map21_Regs[ 6 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 6 ] = VROMPAGE( Map21_Regs[ 6 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xe002:
Map21_Regs[ 6 ] = ( Map21_Regs[ 6 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 6 ] = VROMPAGE( Map21_Regs[ 6 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xe001:
case 0xe004:
Map21_Regs[ 7 ] = ( Map21_Regs[ 7 ] & 0xf0 ) | ( byData & 0x0f );
W.PPUBANK[ 7 ] = VROMPAGE( Map21_Regs[ 7 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xe003:
case 0xe006:
Map21_Regs[ 7 ] = ( Map21_Regs[ 7 ] & 0x0f ) | ( ( byData & 0x0f ) << 4 );
W.PPUBANK[ 7 ] = VROMPAGE( Map21_Regs[ 7 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xf000:
Map21_IRQ_Latch = ( Map21_IRQ_Latch & 0xf0 ) | ( byData & 0x0f );
break;
case 0xf002:
Map21_IRQ_Latch = ( Map21_IRQ_Latch & 0x0f ) | ( ( byData & 0x0f ) << 4 );
break;
case 0xf003:
if ( Map21_IRQ_Enable & 0x01 )
{
Map21_IRQ_Enable |= 0x02;
} else {
Map21_IRQ_Enable &= 0x01;
}
break;
case 0xf004:
Map21_IRQ_Enable = byData & 0x03;
if ( Map21_IRQ_Enable & 0x02 )
{
Map21_IRQ_Cnt = Map21_IRQ_Latch;
}
break;
}
}
void Map75_Write( word wAddr, byte byData )
{
switch ( wAddr & 0xf000 )
{
/* Set ROM Banks */
case 0x8000:
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK0 = ROMPAGE( byData );
break;
case 0x9000:
/* Set Mirroring */
if ( byData & 0x01 )
{
NESCore_Mirroring( 0 );
} else {
NESCore_Mirroring( 1 );
}
/* Set PPU Banks */
Map75_Regs[ 0 ] = ( Map75_Regs[ 0 ] & 0x0f ) | ( ( byData & 0x02 ) << 3 );
W.PPUBANK[ 0 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 0 );
W.PPUBANK[ 1 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 1 );
W.PPUBANK[ 2 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 2 );
W.PPUBANK[ 3 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 3 );
Map75_Regs[ 1 ] = ( Map75_Regs[ 1 ] & 0x0f ) | ( ( byData & 0x04 ) << 2 );
W.PPUBANK[ 4 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 0 );
W.PPUBANK[ 5 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 1 );
W.PPUBANK[ 6 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 2 );
W.PPUBANK[ 7 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 3 );
NESCore_Develop_Character_Data();
break;
/* Set ROM Banks */
case 0xA000:
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK1 = ROMPAGE( byData );
break;
/* Set ROM Banks */
case 0xC000:
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK2 = ROMPAGE( byData );
break;
case 0xE000:
/* Set PPU Banks */
Map75_Regs[ 0 ] = ( Map75_Regs[ 0 ] & 0x10 ) | ( byData & 0x0f );
W.PPUBANK[ 0 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 0 );
W.PPUBANK[ 1 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 1 );
W.PPUBANK[ 2 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 2 );
W.PPUBANK[ 3 ] = VROMPAGE( ( Map75_Regs[ 0 ] << 2 ) + 3 );
NESCore_Develop_Character_Data();
break;
case 0xF000:
/* Set PPU Banks */
Map75_Regs[ 1 ] = ( Map75_Regs[ 1 ] & 0x10 ) | ( byData & 0x0f );
W.PPUBANK[ 4 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 0 );
W.PPUBANK[ 5 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 1 );
W.PPUBANK[ 6 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 2 );
W.PPUBANK[ 7 ] = VROMPAGE( ( Map75_Regs[ 1 ] << 2 ) + 3 );
NESCore_Develop_Character_Data();
break;
}
}
void Map24_Write( word wAddr, byte byData )
{
switch ( wAddr )
{
case 0x8000:
/* Set ROM Banks */
W.ROMBANK0 = ROMPAGE( ( byData + 0 ) % ( S.NesHeader.ROMSize << 1) );
W.ROMBANK1 = ROMPAGE( ( byData + 1 ) % ( S.NesHeader.ROMSize << 1) );
break;
case 0xb003:
/* Name Table Mirroring */
switch ( byData & 0x0c )
{
case 0x00:
NESCore_Mirroring( 1 ); /* Vertical */
break;
case 0x04:
NESCore_Mirroring( 0 ); /* Horizontal */
break;
case 0x08:
NESCore_Mirroring( 3 ); /* One Screen 0x2000 */
break;
case 0x0c:
NESCore_Mirroring( 2 ); /* One Screen 0x2400 */
break;
}
break;
case 0xC000:
W.ROMBANK2 = ROMPAGE( byData % ( S.NesHeader.ROMSize << 1) );
break;
case 0xD000:
W.PPUBANK[ 0 ] = VROMPAGE( byData % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xD001:
W.PPUBANK[ 1 ] = VROMPAGE( byData % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xD002:
W.PPUBANK[ 2 ] = VROMPAGE( byData % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xD003:
W.PPUBANK[ 3 ] = VROMPAGE( byData % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xE000:
W.PPUBANK[ 4 ] = VROMPAGE( byData % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xE001:
W.PPUBANK[ 5 ] = VROMPAGE( byData % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xE002:
W.PPUBANK[ 6 ] = VROMPAGE( byData % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xE003:
W.PPUBANK[ 7 ] = VROMPAGE( byData % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xF000:
Map24_IRQ_Latch = byData;
break;
case 0xF001:
Map24_IRQ_State = byData & 0x03;
if(Map24_IRQ_State & 0x02)
{
Map24_IRQ_Count = Map24_IRQ_Latch;
}
break;
case 0xF002:
if(Map24_IRQ_State & 0x01)
{
Map24_IRQ_State |= 0x02;
}
else
{
Map24_IRQ_State &= 0x01;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map100_Write( word wAddr, byte byData )
{
switch ( wAddr & 0xE001 )
{
case 0x8000:
Map100_Reg[0] = byData;
break;
case 0x8001:
Map100_Reg[1] = byData;
switch ( Map100_Reg[0] & 0xC7 ) {
case 0x00:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr0 = byData&0xFE;
Map100_Chr1 = Map100_Chr0+1;
Map100_Set_PPU_Banks();
}
break;
case 0x01:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr2 = byData&0xFE;
Map100_Chr3 = Map100_Chr2+1;
Map100_Set_PPU_Banks();
}
break;
case 0x02:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr4 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x03:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr5 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x04:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr6 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x05:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr7 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x06:
Map100_Prg0 = byData;
Map100_Set_CPU_Banks();
break;
case 0x07:
Map100_Prg1 = byData;
Map100_Set_CPU_Banks();
break;
case 0x46:
Map100_Prg2 = byData;
Map100_Set_CPU_Banks();
break;
case 0x47:
Map100_Prg3 = byData;
Map100_Set_CPU_Banks();
break;
case 0x80:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr4 = byData&0xFE;
Map100_Chr5 = Map100_Chr4+1;
Map100_Set_PPU_Banks();
}
break;
case 0x81:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr6 = byData&0xFE;
Map100_Chr7 = Map100_Chr6+1;
Map100_Set_PPU_Banks();
}
break;
case 0x82:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr0 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x83:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr1 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x84:
if ( S.NesHeader.VROMSize > 0 ) {
Map100_Chr2 = byData;
Map100_Set_PPU_Banks();
}
break;
case 0x85:
if( S.NesHeader.VROMSize > 0 ) {
Map100_Chr3 = byData;
Map100_Set_PPU_Banks();
}
break;
}
break;
case 0xA000:
Map100_Reg[2] = byData;
if ( !S.ROM_FourScr )
{
if( byData & 0x01 ) NESCore_Mirroring( 0 );
else NESCore_Mirroring( 1 );
}
break;
case 0xA001:
Map100_Reg[3] = byData;
break;
case 0xC000:
Map100_Reg[4] = byData;
Map100_IRQ_Cnt = byData;
break;
case 0xC001:
Map100_Reg[5] = byData;
Map100_IRQ_Latch = byData;
break;
case 0xE000:
Map100_Reg[6] = byData;
Map100_IRQ_Enable = 0;
break;
case 0xE001:
Map100_Reg[7] = byData;
Map100_IRQ_Enable = 0xFF;
break;
}
}
void Map4_Write( word wAddr, byte bData )
{
dword dwBankNum;
switch ( wAddr & 0xe001 )
{
case 0x8000:
MS4.Regs[ 0 ] = bData;
Map4_Set_CPU_Banks();
break;
case 0x8001:
MS4.Regs[ 1 ] = bData;
dwBankNum = MS4.Regs[ 1 ];
switch ( MS4.Regs[ 0 ] & 0x07 )
{
/* Set PPU Banks */
case 0x00:
if ( S.NesHeader.VROMSize > 0 )
{
dwBankNum &= 0xfe;
MS4.PPU[0] = dwBankNum;
if ( Map4_Chr_Swap() )
{
W.PPUBANK[4] = VROMPAGE((MS4.PPU[0] ) % (Map4_Vsz));
W.PPUBANK[5] = VROMPAGE((MS4.PPU[0]+1) % (Map4_Vsz));
} else {
W.PPUBANK[0] = VROMPAGE((MS4.PPU[0] ) % (Map4_Vsz));
W.PPUBANK[1] = VROMPAGE((MS4.PPU[0]+1) % (Map4_Vsz));
}
NESCore_Develop_Character_Data();
}
break;
case 0x01:
if ( S.NesHeader.VROMSize > 0 )
{
dwBankNum &= 0xfe;
MS4.PPU[1] = dwBankNum;
if ( Map4_Chr_Swap() )
{
W.PPUBANK[6] = VROMPAGE((MS4.PPU[1] ) % (Map4_Vsz));
W.PPUBANK[7] = VROMPAGE((MS4.PPU[1]+1) % (Map4_Vsz));
} else {
W.PPUBANK[2] = VROMPAGE((MS4.PPU[1] ) % (Map4_Vsz));
W.PPUBANK[3] = VROMPAGE((MS4.PPU[1]+1) % (Map4_Vsz));
}
NESCore_Develop_Character_Data();
}
break;
case 0x02:
if ( S.NesHeader.VROMSize > 0 )
{
MS4.PPU[2] = dwBankNum;
if ( Map4_Chr_Swap() )
W.PPUBANK[0] = VROMPAGE( MS4.PPU[2] % ( Map4_Vsz ) );
else
W.PPUBANK[4] = VROMPAGE( MS4.PPU[2] % ( Map4_Vsz ) );
NESCore_Develop_Character_Data();
}
break;
case 0x03:
if ( S.NesHeader.VROMSize > 0 )
{
MS4.PPU[3] = dwBankNum;
if ( Map4_Chr_Swap() )
W.PPUBANK[1] = VROMPAGE( MS4.PPU[3] % ( Map4_Vsz ) );
else
W.PPUBANK[5] = VROMPAGE( MS4.PPU[3] % ( Map4_Vsz ) );
NESCore_Develop_Character_Data();
}
break;
case 0x04:
if ( S.NesHeader.VROMSize > 0 )
{
MS4.PPU[4] = dwBankNum;
if ( Map4_Chr_Swap() )
W.PPUBANK[2] = VROMPAGE( MS4.PPU[4] % ( Map4_Vsz ) );
else
W.PPUBANK[6] = VROMPAGE( MS4.PPU[4] % ( Map4_Vsz ) );
NESCore_Develop_Character_Data();
}
break;
case 0x05:
if ( S.NesHeader.VROMSize > 0 )
{
MS4.PPU[5] = dwBankNum;
if ( Map4_Chr_Swap() )
W.PPUBANK[3] = VROMPAGE( MS4.PPU[5] % ( Map4_Vsz ) );
else
W.PPUBANK[7] = VROMPAGE( MS4.PPU[5] % ( Map4_Vsz ) );
NESCore_Develop_Character_Data();
}
break;
/* Set ROM Banks */
case 0x06:
MS4.Prg0 = dwBankNum;
Map4_Set_CPU_Banks();
break;
case 0x07:
MS4.Prg1 = dwBankNum;
Map4_Set_CPU_Banks();
break;
}
break;
case 0xa000:
MS4.Regs[ 2 ] = bData & 1;
if (!S.ROM_FourScr)
{
if ( bData & 0x01 )
{
NESCore_Mirroring( 0 );
} else {
NESCore_Mirroring( 1 );
}
}
break;
case 0xa001:
MS4.Regs[ 3 ] = bData;
break;
case 0xe000: /* ACK IRQ */
MS4.IRQ_Enabled = 0;
break;
case 0xe001: /* Enable IRQ */
MS4.IRQ_Enabled = 1;
break;
}
/* Old IRQ Technique */
/*
if (wAddr >= 0xc000 && wAddr <= 0xdfff) {
if (wAddr % 2 == 0) {
MS4.IRQ_Counter = bData;
}
else {
MS4.IRQ_Latch = bData;
}
}
*/
if (wAddr >= 0xc000 && wAddr <= 0xdfff) {
if (wAddr % 2 == 0) {
MS4.IRQ_Latch = bData;
}
else {
MS4.IRQ_Counter = MS4.IRQ_Latch;
}
}
}
void Map16_Write( word wAddr, byte byData )
{
switch ( wAddr & 0x000f )
{
case 0x0000:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 0 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0x0001:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 1 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0x0002:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 2 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0x0003:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 3 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0x0004:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 4 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0x0005:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 5 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0x0006:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 6 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0x0007:
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 7 ] = VROMPAGE( byData );
NESCore_Develop_Character_Data();
break;
case 0x0008:
byData <<= 1;
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK0 = ROMPAGE( byData );
W.ROMBANK1 = ROMPAGE( byData + 1 );
break;
case 0x0009:
switch ( byData & 0x03 )
{
case 0x00:
NESCore_Mirroring( 1 );
break;
case 0x01:
NESCore_Mirroring( 0 );
break;
case 0x02:
NESCore_Mirroring( 3 );
break;
case 0x03:
NESCore_Mirroring( 2 );
break;
}
break;
case 0x000a:
Map16_IRQ_Enable = byData & 0x01;
Map16_IRQ_Cnt = Map16_IRQ_Latch;
break;
case 0x000b:
Map16_IRQ_Latch = ( Map16_IRQ_Latch & 0xff00 ) | byData;
break;
case 0x000c:
Map16_IRQ_Latch = ( (dword)byData << 8 ) | ( Map16_IRQ_Latch & 0x00ff );
break;
case 0x000d:
/* Write Protect */
break;
}
}
void Map10_Write( word wAddr, byte byData )
{
word wMapAddr;
wMapAddr = wAddr & 0xf000;
switch ( wMapAddr )
{
case 0xa000:
/* Set ROM Banks */
byData %= S.NesHeader.ROMSize;
byData <<= 1;
W.ROMBANK0 = ROMPAGE( byData );
W.ROMBANK1 = ROMPAGE( byData + 1 );
break;
case 0xb000:
/* Number of 4K Banks to Number of 1K Banks */
byData %= ( S.NesHeader.VROMSize << 1 );
byData <<= 2;
/* Latch Control */
latch3.lo_bank = byData;
if (0xfd == latch3.state)
{
/* Set PPU Banks */
W.PPUBANK[ 0 ] = VROMPAGE( byData );
W.PPUBANK[ 1 ] = VROMPAGE( byData + 1 );
W.PPUBANK[ 2 ] = VROMPAGE( byData + 2 );
W.PPUBANK[ 3 ] = VROMPAGE( byData + 3 );
NESCore_Develop_Character_Data();
}
break;
case 0xc000:
/* Number of 4K Banks to Number of 1K Banks */
byData %= ( S.NesHeader.VROMSize << 1 );
byData <<= 2;
/* Latch Control */
latch3.hi_bank = byData;
if (0xfe == latch3.state)
{
/* Set PPU Banks */
W.PPUBANK[ 0 ] = VROMPAGE( byData );
W.PPUBANK[ 1 ] = VROMPAGE( byData + 1 );
W.PPUBANK[ 2 ] = VROMPAGE( byData + 2 );
W.PPUBANK[ 3 ] = VROMPAGE( byData + 3 );
NESCore_Develop_Character_Data();
}
break;
case 0xd000:
/* Number of 4K Banks to Number of 1K Banks */
byData %= ( S.NesHeader.VROMSize << 1 );
byData <<= 2;
/* Latch Control */
latch4.lo_bank = byData;
if (0xfd == latch4.state)
{
/* Set PPU Banks */
W.PPUBANK[ 4 ] = VROMPAGE( byData );
W.PPUBANK[ 5 ] = VROMPAGE( byData + 1 );
W.PPUBANK[ 6 ] = VROMPAGE( byData + 2 );
W.PPUBANK[ 7 ] = VROMPAGE( byData + 3 );
NESCore_Develop_Character_Data();
}
break;
case 0xe000:
/* Number of 4K Banks to Number of 1K Banks */
byData %= ( S.NesHeader.VROMSize << 1 );
byData <<= 2;
/* Latch Control */
latch4.hi_bank = byData;
if (0xfe == latch4.state)
{
/* Set PPU Banks */
W.PPUBANK[ 4 ] = VROMPAGE( byData );
W.PPUBANK[ 5 ] = VROMPAGE( byData + 1 );
W.PPUBANK[ 6 ] = VROMPAGE( byData + 2 );
W.PPUBANK[ 7 ] = VROMPAGE( byData + 3 );
NESCore_Develop_Character_Data();
}
break;
case 0xf000:
/* Name Table Mirroring */
NESCore_Mirroring( byData & 0x01 ? 0 : 1);
break;
}
}
void Map33_Write( word wAddr, byte byData )
{
/* Set ROM Banks */
switch ( wAddr )
{
case 0x8000:
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK0 = ROMPAGE( byData );
break;
case 0x8001:
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK1 = ROMPAGE( byData );
break;
case 0x8002:
Map33_Regs[ 0 ] = byData * 2;
Map33_Regs[ 1 ] = byData * 2 + 1;
W.PPUBANK[ 0 ] = VROMPAGE( Map33_Regs[ 0 ] % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 1 ] = VROMPAGE( Map33_Regs[ 1 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0x8003:
Map33_Regs[ 2 ] = byData * 2;
Map33_Regs[ 3 ] = byData * 2 + 1;
W.PPUBANK[ 2 ] = VROMPAGE( Map33_Regs[ 2 ] % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 3 ] = VROMPAGE( Map33_Regs[ 3 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xa000:
Map33_Regs[ 4 ] = byData;
W.PPUBANK[ 4 ] = VROMPAGE( Map33_Regs[ 4 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xa001:
Map33_Regs[ 5 ] = byData;
W.PPUBANK[ 5 ] = VROMPAGE( Map33_Regs[ 5 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xa002:
Map33_Regs[ 6 ] = byData;
W.PPUBANK[ 6 ] = VROMPAGE( Map33_Regs[ 6 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xa003:
Map33_Regs[ 7 ] = byData;
W.PPUBANK[ 7 ] = VROMPAGE( Map33_Regs[ 7 ] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
break;
case 0xc000:
Map33_IRQ_Cnt = byData;
break;
case 0xc001:
case 0xc002:
case 0xe001:
case 0xe002:
if ( Map33_IRQ_Cnt == byData )
{
Map33_IRQ_Enable = 0xff;
} else {
Map33_IRQ_Enable = byData;
}
break;
case 0xe000:
if ( byData & 0x40 )
{
NESCore_Mirroring( 0 );
} else {
NESCore_Mirroring( 1 );
}
break;
}
}
void Map45_Write( word wAddr, byte byData )
{
dword swap;
switch(wAddr & 0xE001)
{
case 0x8000:
if((byData & 0x40) != (Map45_Regs[6] & 0x40))
{
swap = Map45_Prg0; Map45_Prg0 = Map45_Prg2; Map45_Prg2 = swap;
swap = Map45_P[0]; Map45_P[0] = Map45_P[2]; Map45_P[2] = swap;
W.ROMBANK0 = ROMPAGE( Map45_P[0] % ( S.NesHeader.ROMSize << 1) );
W.ROMBANK2 = ROMPAGE( Map45_P[2] % ( S.NesHeader.ROMSize << 1) );
}
if (S.NesHeader.ROMSize > 0)
{
if((byData & 0x80) != (Map45_Regs[6] & 0x80))
{
swap = Map45_Chr4; Map45_Chr4 = Map45_Chr0; Map45_Chr0 = swap;
swap = Map45_Chr5; Map45_Chr5 = Map45_Chr1; Map45_Chr1 = swap;
swap = Map45_Chr6; Map45_Chr6 = Map45_Chr2; Map45_Chr2 = swap;
swap = Map45_Chr7; Map45_Chr7 = Map45_Chr3; Map45_Chr3 = swap;
swap = Map45_C[4]; Map45_C[4] = Map45_C[0]; Map45_C[0] = swap;
swap = Map45_C[5]; Map45_C[5] = Map45_C[1]; Map45_C[1] = swap;
swap = Map45_C[6]; Map45_C[6] = Map45_C[2]; Map45_C[2] = swap;
swap = Map45_C[7]; Map45_C[7] = Map45_C[3]; Map45_C[3] = swap;
W.PPUBANK[ 0 ] = VROMPAGE( Map45_C[0] % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 1 ] = VROMPAGE( Map45_C[1] % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 2 ] = VROMPAGE( Map45_C[2] % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 3 ] = VROMPAGE( Map45_C[3] % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 4 ] = VROMPAGE( Map45_C[4] % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 5 ] = VROMPAGE( Map45_C[5] % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 6 ] = VROMPAGE( Map45_C[6] % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[ 7 ] = VROMPAGE( Map45_C[7] % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
}
}
Map45_Regs[6] = byData;
break;
case 0x8001:
switch(Map45_Regs[6] & 0x07)
{
case 0x00:
Map45_Chr0 = (byData & 0xFE)+0;
Map45_Chr1 = (byData & 0xFE)+1;
Map45_Set_PPU_Banks();
break;
case 0x01:
Map45_Chr2 = (byData & 0xFE)+0;
Map45_Chr3 = (byData & 0xFE)+1;
Map45_Set_PPU_Banks();
break;
case 0x02:
Map45_Chr4 = byData;
Map45_Set_PPU_Banks();
break;
case 0x03:
Map45_Chr5 = byData;
Map45_Set_PPU_Banks();
break;
case 0x04:
Map45_Chr6 = byData;
Map45_Set_PPU_Banks();
break;
case 0x05:
Map45_Chr7 = byData;
Map45_Set_PPU_Banks();
break;
case 0x06:
if(Map45_Regs[6] & 0x40)
{
Map45_Prg2 = byData & 0x3F;
Map45_Set_CPU_Bank6(byData);
}
else
{
Map45_Prg0 = byData & 0x3F;
Map45_Set_CPU_Bank4(byData);
}
break;
case 0x07:
Map45_Prg1 = byData & 0x3F;
Map45_Set_CPU_Bank5(byData);
break;
}
break;
case 0xA000:
if ( byData & 0x01 )
{
NESCore_Mirroring( 0 );
} else {
NESCore_Mirroring( 1 );
}
break;
case 0xC000:
Map45_IRQ_Cnt = byData;
break;
case 0xC001:
Map45_IRQ_Latch = byData;
break;
case 0xE000:
Map45_IRQ_Enable = 0;
break;
case 0xE001:
Map45_IRQ_Enable = 1;
break;
}
}
void Map67_Write( word wAddr, byte byData )
{
switch ( wAddr & 0xf800 )
{
/* Set PPU Banks */
case 0x8800:
byData <<= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 0 ] = VROMPAGE( byData + 0 );
W.PPUBANK[ 1 ] = VROMPAGE( byData + 1 );
NESCore_Develop_Character_Data();
break;
case 0x9800:
byData <<= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 2 ] = VROMPAGE( byData + 0 );
W.PPUBANK[ 3 ] = VROMPAGE( byData + 1 );
NESCore_Develop_Character_Data();
break;
case 0xa800:
byData <<= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 4 ] = VROMPAGE( byData + 0 );
W.PPUBANK[ 5 ] = VROMPAGE( byData + 1 );
NESCore_Develop_Character_Data();
break;
case 0xb800:
byData <<= 1;
byData %= ( S.NesHeader.VROMSize << 3 );
W.PPUBANK[ 6 ] = VROMPAGE( byData + 0 );
W.PPUBANK[ 7 ] = VROMPAGE( byData + 1 );
NESCore_Develop_Character_Data();
break;
case 0xc800:
Map67_IRQ_Cnt = Map67_IRQ_Latch;
Map67_IRQ_Latch = byData;
break;
case 0xd800:
Map67_IRQ_Enable = byData & 0x10;
break;
case 0xe800:
switch ( byData & 0x03 )
{
case 0:
NESCore_Mirroring( 1 );
break;
case 1:
NESCore_Mirroring( 0 );
break;
case 2:
NESCore_Mirroring( 3 );
break;
case 3:
NESCore_Mirroring( 2 );
break;
}
break;
/* Set ROM Banks */
case 0xf800:
byData <<= 1;
byData %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK0 = ROMPAGE( byData + 0 );
W.ROMBANK1 = ROMPAGE( byData + 1 );
break;
}
}
/*-------------------------------------------------------------------*/
void Map83_Write( word wAddr, byte byData )
{
/* Set ROM Banks */
switch( wAddr )
{
case 0x8000:
case 0xB000:
case 0xB0FF:
case 0xB1FF:
Map83_Regs[0] = byData;
Map83_Chr_Bank = (byData & 0x30) << 4;
W.ROMBANK0 = ROMPAGE( (byData*2+0) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK1 = ROMPAGE( (byData*2+1) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK2 = ROMPAGE( (((byData&0x30)|0x0F)*2+0) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK3 = ROMPAGE( (((byData&0x30)|0x0F)*2+1) % (S.NesHeader.ROMSize << 1) );
break;
case 0x8100:
if ( S.NesHeader.VROMSize <= 32 )
{
Map83_Regs[1] = byData;
}
if ((byData & 0x03) == 0x00)
{
NESCore_Mirroring( 1 );
}
else if((byData & 0x03) == 0x01)
{
NESCore_Mirroring( 0 );
}
else if((byData & 0x03) == 0x02)
{
NESCore_Mirroring( 3 );
}
else
{
NESCore_Mirroring( 2 );
}
break;
case 0x8200:
Map83_IRQ_Cnt = ( Map83_IRQ_Cnt & 0xFF00 ) | (dword)byData;
break;
case 0x8201:
Map83_IRQ_Cnt = ( Map83_IRQ_Cnt & 0x00FF ) | ((dword)byData << 8);
Map83_IRQ_Enabled = byData;
break;
case 0x8300:
W.ROMBANK0 = ROMPAGE( byData % (S.NesHeader.ROMSize << 1) );
break;
case 0x8301:
W.ROMBANK1 = ROMPAGE( byData % (S.NesHeader.ROMSize << 1) );
break;
case 0x8302:
W.ROMBANK2 = ROMPAGE( byData % (S.NesHeader.ROMSize << 1) );
break;
case 0x8310:
if ((Map83_Regs[1] & 0x30) == 0x30)
{
W.PPUBANK[0] = VROMPAGE( (Map83_Chr_Bank^byData) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
else if((Map83_Regs[1] & 0x30) == 0x10 || (Map83_Regs[1] & 0x30) == 0x20)
{
W.PPUBANK[0] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+0) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[1] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+1) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
break;
case 0x8311:
if ((Map83_Regs[1] & 0x30) == 0x30)
{
W.PPUBANK[1] = VROMPAGE( (Map83_Chr_Bank^byData) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
else if((Map83_Regs[1] & 0x30) == 0x10 || (Map83_Regs[1] & 0x30) == 0x20)
{
W.PPUBANK[2] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+0) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[3] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+1) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
break;
case 0x8312:
if ((Map83_Regs[1] & 0x30) == 0x30)
{
W.PPUBANK[2] = VROMPAGE( (Map83_Chr_Bank^byData) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
else if((Map83_Regs[1] & 0x30) == 0x10 || (Map83_Regs[1] & 0x30) == 0x20)
{
W.PPUBANK[4] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+0) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[5] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+1) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
break;
case 0x8313:
if ((Map83_Regs[1] & 0x30) == 0x30)
{
W.PPUBANK[3] = VROMPAGE( (Map83_Chr_Bank^byData) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
else if((Map83_Regs[1] & 0x30) == 0x10 || (Map83_Regs[1] & 0x30) == 0x20)
{
W.PPUBANK[6] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+0) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[7] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+1) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
break;
case 0x8314:
if ((Map83_Regs[1] & 0x30) == 0x30)
{
W.PPUBANK[4] = VROMPAGE( (Map83_Chr_Bank^byData) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
else if((Map83_Regs[1] & 0x30) == 0x10 || (Map83_Regs[1] & 0x30) == 0x20)
{
W.PPUBANK[4] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+0) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[5] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+1) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
break;
case 0x8315:
if ((Map83_Regs[1] & 0x30) == 0x30)
{
W.PPUBANK[5] = VROMPAGE( (Map83_Chr_Bank^byData) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
else if ((Map83_Regs[1] & 0x30) == 0x10 || (Map83_Regs[1] & 0x30) == 0x20)
{
W.PPUBANK[6] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+0) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[7] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+1) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
break;
case 0x8316:
if ((Map83_Regs[1] & 0x30) == 0x30)
{
W.PPUBANK[6] = VROMPAGE( (Map83_Chr_Bank^byData) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
else if ((Map83_Regs[1] & 0x30) == 0x10 || (Map83_Regs[1] & 0x30) == 0x20)
{
W.PPUBANK[4] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+0) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[5] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+1) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
break;
case 0x8317:
if ((Map83_Regs[1] & 0x30) == 0x30)
{
W.PPUBANK[7] = VROMPAGE( (Map83_Chr_Bank^byData) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
else if ( (Map83_Regs[1] & 0x30) == 0x10 || (Map83_Regs[1] & 0x30) == 0x20)
{
W.PPUBANK[6] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+0) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[7] = VROMPAGE( (((Map83_Chr_Bank^byData)*2)+1) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
}
break;
case 0x8318:
W.ROMBANK0 = ROMPAGE( (((Map83_Regs[0]&0x30)|byData)*2+0) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK1 = ROMPAGE( (((Map83_Regs[0]&0x30)|byData)*2+1) % (S.NesHeader.ROMSize << 1) );
break;
}
}