static void esky_init2()
{
NRF24L01_FlushTx();
packet_sent = 0;
rf_ch_num = 0;
u32 channel_ord = rand32_r(0, 0) % 74;
channel_code = 10 + (u8) channel_ord;
u8 channel1, channel2;
channel1 = 10 + (u8) ((37 + channel_ord*5) % 74);
channel2 = 10 + (u8) ((channel_ord*5) % 74) ;
printf("channel code %d, channel1 %d, channel2 %d\n", (int) channel_code, (int) channel1, (int) channel2);
rf_channels[0] = channel1;
rf_channels[1] = channel1;
rf_channels[2] = channel1;
rf_channels[3] = channel2;
rf_channels[4] = channel2;
rf_channels[5] = channel2;
end_bytes[0] = 6;
end_bytes[1] = channel1*2;
end_bytes[2] = channel2*2;
end_bytes[3] = 6;
end_bytes[4] = channel1*2;
end_bytes[5] = channel2*2;
// Turn radio power on
NRF24L01_SetTxRxMode(TX_EN);
u8 config = BV(NRF24L01_00_EN_CRC) | BV(NRF24L01_00_CRCO) | BV(NRF24L01_00_PWR_UP);
NRF24L01_WriteReg(NRF24L01_00_CONFIG, config);
// Implicit delay in callback
// delayMicroseconds(150);
}
static int cflie_init()
{
NRF24L01_Initialize();
// CRC, radio on
NRF24L01_SetTxRxMode(TX_EN);
NRF24L01_WriteReg(NRF24L01_00_CONFIG, BV(NRF24L01_00_EN_CRC) | BV(NRF24L01_00_CRCO) | BV(NRF24L01_00_PWR_UP));
NRF24L01_WriteReg(NRF24L01_01_EN_AA, 0x01); // Auto Acknowledgement for data pipe 0
NRF24L01_WriteReg(NRF24L01_02_EN_RXADDR, 0x01); // Enable data pipe 0
NRF24L01_WriteReg(NRF24L01_03_SETUP_AW, TX_ADDR_SIZE-2); // 5-byte RX/TX address
NRF24L01_WriteReg(NRF24L01_04_SETUP_RETR, 0x13); // 3 retransmits, 500us delay
NRF24L01_WriteReg(NRF24L01_05_RF_CH, rf_channel); // Defined by model id
NRF24L01_SetBitrate(data_rate); // Defined by model id
NRF24L01_SetPower(Model.tx_power);
NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70); // Clear data ready, data sent, and retransmit
NRF24L01_WriteRegisterMulti(NRF24L01_0A_RX_ADDR_P0, rx_tx_addr, TX_ADDR_SIZE);
NRF24L01_WriteRegisterMulti(NRF24L01_10_TX_ADDR, rx_tx_addr, TX_ADDR_SIZE);
// this sequence necessary for module from stock tx
NRF24L01_ReadReg(NRF24L01_1D_FEATURE);
NRF24L01_Activate(0x73); // Activate feature register
NRF24L01_ReadReg(NRF24L01_1D_FEATURE);
NRF24L01_WriteReg(NRF24L01_1C_DYNPD, 0x01); // Enable Dynamic Payload Length on pipe 0
NRF24L01_WriteReg(NRF24L01_1D_FEATURE, 0x06); // Enable Dynamic Payload Length, enable Payload with ACK
// 50ms delay in callback
return 50000;
}
int NRF24L01_Reset()
{
NRF24L01_FlushTx();
NRF24L01_FlushRx();
u8 status1 = Strobe(NOP);
u8 status2 = NRF24L01_ReadReg(0x07);
NRF24L01_SetTxRxMode(TXRX_OFF);
return (status1 == status2 && (status1 & 0x0f) == 0x0e);
}
static void DM002_init()
{
NRF24L01_Initialize();
NRF24L01_SetTxRxMode(TX_EN);
XN297_SetTXAddr((uint8_t *)"\x26\xA8\x67\x35\xCC", DM002_ADDRESS_SIZE);
NRF24L01_FlushTx();
NRF24L01_FlushRx();
NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70); // Clear data ready, data sent, and retransmit
NRF24L01_WriteReg(NRF24L01_01_EN_AA, 0x00); // No Auto Acknowldgement on all data pipes
NRF24L01_WriteReg(NRF24L01_02_EN_RXADDR, 0x01); // Enable data pipe 0 only
NRF24L01_SetBitrate(NRF24L01_BR_1M); // 1Mbps
NRF24L01_SetPower(Model.tx_power);
// Check for Beken BK2421/BK2423 chip
// It is done by using Beken specific activate code, 0x53
// and checking that status register changed appropriately
// There is no harm to run it on nRF24L01 because following
// closing activate command changes state back even if it
// does something on nRF24L01
NRF24L01_Activate(0x53); // magic for BK2421 bank switch
dbgprintf("Trying to switch banks\n");
if (NRF24L01_ReadReg(NRF24L01_07_STATUS) & 0x80) {
dbgprintf("BK2421 detected\n");
// Beken registers don't have such nice names, so we just mention
// them by their numbers
// It's all magic, eavesdropped from real transfer and not even from the
// data sheet - it has slightly different values
NRF24L01_WriteRegisterMulti(0x00, (u8 *) "\x40\x4B\x01\xE2", 4);
NRF24L01_WriteRegisterMulti(0x01, (u8 *) "\xC0\x4B\x00\x00", 4);
NRF24L01_WriteRegisterMulti(0x02, (u8 *) "\xD0\xFC\x8C\x02", 4);
NRF24L01_WriteRegisterMulti(0x03, (u8 *) "\x99\x00\x39\x21", 4);
NRF24L01_WriteRegisterMulti(0x04, (u8 *) "\xD9\x96\x82\x1B", 4);
NRF24L01_WriteRegisterMulti(0x05, (u8 *) "\x24\x06\x7F\xA6", 4);
NRF24L01_WriteRegisterMulti(0x0C, (u8 *) "\x00\x12\x73\x00", 4);
NRF24L01_WriteRegisterMulti(0x0D, (u8 *) "\x46\xB4\x80\x00", 4);
NRF24L01_WriteRegisterMulti(0x04, (u8 *) "\xDF\x96\x82\x1B", 4);
NRF24L01_WriteRegisterMulti(0x04, (u8 *) "\xD9\x96\x82\x1B", 4);
} else {
dbgprintf("nRF24L01 detected\n");
}
NRF24L01_Activate(0x53); // switch bank back
}
u16 ASSAN_callback()
{
switch (state)
{
// Bind
case BIND0:
//Config RX @1M
NRF24L01_WriteReg(NRF24L01_05_RF_CH, RF_BIND_CHANNEL);
NRF24L01_SetBitrate(NRF24L01_BR_1M); // 1Mbps
NRF24L01_SetTxRxMode(RX_EN);
state = BIND1;
/* FALLTHROUGH */
case BIND1:
//Wait for receiver to send the frames
if( NRF24L01_ReadReg(NRF24L01_07_STATUS) & BV(NRF24L01_07_RX_DR))
{ //Something has been received
NRF24L01_ReadPayload(packet, PACKET_SIZE);
if(packet[19]==0x13)
{ //Last frame received
state = BIND2 | WAIT;
//Switch to TX
NRF24L01_SetTxRxMode(TXRX_OFF);
NRF24L01_SetTxRxMode(TX_EN);
//Prepare bind packet
memset(packet,0x05,PACKET_SIZE-5);
packet[15]=0x99;
for(u8 i=0;i<4;i++)
packet[16+i]=packet[23-i];
packet_count=0;
return 10000;
}
}
return 1000;
case BIND2|WAIT:
if(++packet_count == 27) // Wait 270ms in total...
{
packet_count = 0;
state &= ~WAIT;
}
return 10000;
case BIND2:
// Send 20 packets
packet_count++;
if(packet_count==20)
packet[15]=0x13; // different value for last packet
NRF24L01_WritePayload(packet, PACKET_SIZE);
if(packet_count==20)
{
state = DATA0 | WAIT;
packet_count = 0;
}
return 22520;
case DATA0|WAIT:
if(++packet_count == 217)
state &= ~WAIT;
return 10000;
// Normal operation
case DATA0:
// Bind Done
PROTOCOL_SetBindState(0);
NRF24L01_SetBitrate(NRF24L01_BR_250K); // 250Kbps
NRF24L01_SetTxRxMode(TXRX_OFF);
NRF24L01_SetTxRxMode(TX_EN);
/* FALLTHROUGH */
case DATA1:
case DATA4:
// Change ID and RF channel
NRF24L01_WriteRegisterMulti(NRF24L01_10_TX_ADDR, packet+20+4*hopping_frequency_no, ADDRESS_LENGTH);
NRF24L01_WriteReg(NRF24L01_05_RF_CH, hopping_frequency[hopping_frequency_no]);
hopping_frequency_no^=0x01;
state=DATA2;
return 2000;
case DATA2:
case DATA3:
send_packet();
state++; // DATA 3 or 4
return 5000;
}
return 0;
}
static void send_packet(u8 bind)
{
union {
u16 value;
struct {
u8 lsb;
u8 msb;
} bytes;
} chanval;
if (bind) {
if (telemetry)
packet[0] = 0xa3;
else
packet[0] = 0xa4;
memcpy(&packet[1], rx_tx_addr, 5);
memcpy(&packet[6], rf_channels, 4);
switch (Model.proto_opts[PROTOOPTS_FORMAT]) {
case FORMAT_REGULAR:
packet[10] = txid[0];
packet[11] = txid[1];
break;
case FORMAT_X16_AH:
packet[10] = 0x00;
packet[11] = 0x00;
break;
case FORMAT_IRDRONE:
packet[10] = 0x30;
packet[11] = 0x01;
break;
}
} else {
switch (Model.proto_opts[PROTOOPTS_FORMAT]) {
case FORMAT_REGULAR:
packet[0] = 0xa5;
break;
case FORMAT_X16_AH:
case FORMAT_IRDRONE:
packet[0] = 0xa6;
break;
}
packet[1] = 0xfa; // normal mode is 0xf7, expert 0xfa
packet[2] = GET_FLAG(CHANNEL_FLIP, 0x08)
| GET_FLAG(CHANNEL_HEADLESS, 0x02)
| GET_FLAG(CHANNEL_RTH, 0x01)
| GET_FLAG(CHANNEL_VIDEO, 0x10)
| GET_FLAG(CHANNEL_PICTURE, 0x20);
packet[3] = GET_FLAG(CHANNEL_INVERTED, 0x80)
| GET_FLAG(CHANNEL_TO, 0x20)
| GET_FLAG(CHANNEL_EMGSTOP, 0x04);
chanval.value = scale_channel(CHANNEL1, 0x3ff, 0); // aileron
packet[4] = chanval.bytes.msb + DYNTRIM(chanval.value);
packet[5] = chanval.bytes.lsb;
chanval.value = scale_channel(CHANNEL2, 0, 0x3ff); // elevator
packet[6] = chanval.bytes.msb + DYNTRIM(chanval.value);
packet[7] = chanval.bytes.lsb;
chanval.value = scale_channel(CHANNEL3, 0, 0x3ff); // throttle
packet[8] = chanval.bytes.msb + 0x7c;
packet[9] = chanval.bytes.lsb;
chanval.value = scale_channel(CHANNEL4, 0x3ff, 0); // rudder
packet[10] = chanval.bytes.msb + DYNTRIM(chanval.value);
packet[11] = chanval.bytes.lsb;
}
switch (Model.proto_opts[PROTOOPTS_FORMAT]) {
case FORMAT_REGULAR:
packet[12] = txid[2];
packet[13] = 0x0a;
break;
case FORMAT_X16_AH:
packet[12] = 0x00;
packet[13] = 0x00;
break;
case FORMAT_IRDRONE:
packet[12] = 0xe0;
packet[13] = 0x2e;
break;
}
packet[14] = checksum();
NRF24L01_WriteReg(NRF24L01_05_RF_CH,
bind ? bind_chan : rf_channels[rf_chan++]);
rf_chan %= sizeof(rf_channels);
NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70);
NRF24L01_FlushTx();
XN297_WritePayload(packet, PACKET_SIZE);
NRF24L01_SetTxRxMode(TXRX_OFF);
NRF24L01_SetTxRxMode(TX_EN);
// Power on, TX mode, 2byte CRC
// Why CRC0? xn297 does not interpret it - either 16-bit CRC or nothing
XN297_Configure(BV(NRF24L01_00_EN_CRC) | BV(NRF24L01_00_CRCO) |
BV(NRF24L01_00_PWR_UP));
if (telemetry) {
// switch radio to rx, no crc
NRF24L01_WriteReg(NRF24L01_00_CONFIG, 0x03);
}
// Check and adjust transmission power. We do this after
// transmission to not bother with timeout after power
// settings change - we have plenty of time until next
// packet.
if (tx_power != Model.tx_power) {
//Keep transmit power updated
tx_power = Model.tx_power;
NRF24L01_SetPower(tx_power);
}
#ifdef EMULATOR
dbgprintf("next chan 0x%02x, bind %d, data %02x",
bind ? bind_chan : rf_channels[rf_chan], bind,
packet[0]);
for (int i = 1; i < PACKET_SIZE; i++)
dbgprintf(" %02x", packet[i]);
dbgprintf("\n");
#endif
}
static int cflie_init()
{
NRF24L01_Initialize();
// CRC, radio on
NRF24L01_SetTxRxMode(TX_EN);
NRF24L01_WriteReg(NRF24L01_00_CONFIG, BV(NRF24L01_00_EN_CRC) | BV(NRF24L01_00_CRCO) | BV(NRF24L01_00_PWR_UP));
NRF24L01_WriteReg(NRF24L01_01_EN_AA, 0x01); // Auto Acknowledgement for data pipe 0
NRF24L01_WriteReg(NRF24L01_02_EN_RXADDR, 0x01); // Enable data pipe 0
NRF24L01_WriteReg(NRF24L01_03_SETUP_AW, TX_ADDR_SIZE-2); // 5-byte RX/TX address
NRF24L01_WriteReg(NRF24L01_04_SETUP_RETR, 0x13); // 3 retransmits, 500us delay
NRF24L01_WriteReg(NRF24L01_05_RF_CH, rf_channel); // Defined by model id
NRF24L01_SetBitrate(data_rate); // Defined by model id
NRF24L01_SetPower(Model.tx_power);
NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70); // Clear data ready, data sent, and retransmit
NRF24L01_WriteRegisterMulti(NRF24L01_0A_RX_ADDR_P0, rx_tx_addr, TX_ADDR_SIZE);
NRF24L01_WriteRegisterMulti(NRF24L01_10_TX_ADDR, rx_tx_addr, TX_ADDR_SIZE);
// this sequence necessary for module from stock tx
NRF24L01_ReadReg(NRF24L01_1D_FEATURE);
NRF24L01_Activate(0x73); // Activate feature register
NRF24L01_ReadReg(NRF24L01_1D_FEATURE);
NRF24L01_WriteReg(NRF24L01_1C_DYNPD, 0x01); // Enable Dynamic Payload Length on pipe 0
NRF24L01_WriteReg(NRF24L01_1D_FEATURE, 0x06); // Enable Dynamic Payload Length, enable Payload with ACK
// Check for Beken BK2421/BK2423 chip
// It is done by using Beken specific activate code, 0x53
// and checking that status register changed appropriately
// There is no harm to run it on nRF24L01 because following
// closing activate command changes state back even if it
// does something on nRF24L01
NRF24L01_Activate(0x53); // magic for BK2421 bank switch
dbgprintf("Trying to switch banks\n");
if (NRF24L01_ReadReg(NRF24L01_07_STATUS) & 0x80) {
dbgprintf("BK2421 detected\n");
long nul = 0;
// Beken registers don't have such nice names, so we just mention
// them by their numbers
// It's all magic, eavesdropped from real transfer and not even from the
// data sheet - it has slightly different values
NRF24L01_WriteRegisterMulti(0x00, (u8 *) "\x40\x4B\x01\xE2", 4);
NRF24L01_WriteRegisterMulti(0x01, (u8 *) "\xC0\x4B\x00\x00", 4);
NRF24L01_WriteRegisterMulti(0x02, (u8 *) "\xD0\xFC\x8C\x02", 4);
NRF24L01_WriteRegisterMulti(0x03, (u8 *) "\xF9\x00\x39\x21", 4);
NRF24L01_WriteRegisterMulti(0x04, (u8 *) "\xC1\x96\x9A\x1B", 4);
NRF24L01_WriteRegisterMulti(0x05, (u8 *) "\x24\x06\x7F\xA6", 4);
NRF24L01_WriteRegisterMulti(0x06, (u8 *) &nul, 4);
NRF24L01_WriteRegisterMulti(0x07, (u8 *) &nul, 4);
NRF24L01_WriteRegisterMulti(0x08, (u8 *) &nul, 4);
NRF24L01_WriteRegisterMulti(0x09, (u8 *) &nul, 4);
NRF24L01_WriteRegisterMulti(0x0A, (u8 *) &nul, 4);
NRF24L01_WriteRegisterMulti(0x0B, (u8 *) &nul, 4);
NRF24L01_WriteRegisterMulti(0x0C, (u8 *) "\x00\x12\x73\x00", 4);
NRF24L01_WriteRegisterMulti(0x0D, (u8 *) "\x46\xB4\x80\x00", 4);
NRF24L01_WriteRegisterMulti(0x0E, (u8 *) "\x41\x10\x04\x82\x20\x08\x08\xF2\x7D\xEF\xFF", 11);
NRF24L01_WriteRegisterMulti(0x04, (u8 *) "\xC7\x96\x9A\x1B", 4);
NRF24L01_WriteRegisterMulti(0x04, (u8 *) "\xC1\x96\x9A\x1B", 4);
} else {
dbgprintf("nRF24L01 detected\n");
}
NRF24L01_Activate(0x53); // switch bank back
// 50ms delay in callback
return 50000;
}