/*
* initialise the GDB stub I/O routines
*/
void __init gdbstub_io_init(void)
{
uint16_t scxctr;
int tmp;
switch (gdbstub_port->clock_src) {
case MNSCx_CLOCK_SRC_IOCLK:
gdbstub_port->ioclk = MN10300_IOCLK;
break;
#ifdef MN10300_IOBCLK
case MNSCx_CLOCK_SRC_IOBCLK:
gdbstub_port->ioclk = MN10300_IOBCLK;
break;
#endif
default:
BUG();
}
/* set up the serial port */
gdbstub_io_set_baud(115200);
/* we want to get serial receive interrupts */
set_intr_level(gdbstub_port->rx_irq,
NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL));
set_intr_level(gdbstub_port->tx_irq,
NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL));
set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL),
gdbstub_io_rx_handler);
*gdbstub_port->rx_icr |= GxICR_ENABLE;
tmp = *gdbstub_port->rx_icr;
/* enable the device */
scxctr = SC01CTR_CLN_8BIT; /* 1N8 */
switch (gdbstub_port->div_timer) {
case MNSCx_DIV_TIMER_16BIT:
scxctr |= SC0CTR_CK_TM8UFLOW_8; /* == SC1CTR_CK_TM9UFLOW_8
== SC2CTR_CK_TM10UFLOW_8 */
break;
case MNSCx_DIV_TIMER_8BIT:
scxctr |= SC0CTR_CK_TM2UFLOW_8;
break;
}
scxctr |= SC01CTR_TXE | SC01CTR_RXE;
*gdbstub_port->_control = scxctr;
tmp = *gdbstub_port->_control;
/* permit level 0 IRQs only */
arch_local_change_intr_mask_level(
NUM2EPSW_IM(CONFIG_DEBUGGER_IRQ_LEVEL + 1));
}
void __init gdbstub_io_init(void)
{
uint16_t scxctr;
int tmp;
switch (gdbstub_port->clock_src) {
case MNSCx_CLOCK_SRC_IOCLK:
gdbstub_port->ioclk = MN10300_IOCLK;
break;
#ifdef MN10300_IOBCLK
case MNSCx_CLOCK_SRC_IOBCLK:
gdbstub_port->ioclk = MN10300_IOBCLK;
break;
#endif
default:
BUG();
}
gdbstub_io_set_baud(115200);
set_intr_level(gdbstub_port->rx_irq,
NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL));
set_intr_level(gdbstub_port->tx_irq,
NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL));
set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL),
gdbstub_io_rx_handler);
*gdbstub_port->rx_icr |= GxICR_ENABLE;
tmp = *gdbstub_port->rx_icr;
scxctr = SC01CTR_CLN_8BIT;
switch (gdbstub_port->div_timer) {
case MNSCx_DIV_TIMER_16BIT:
scxctr |= SC0CTR_CK_TM8UFLOW_8;
break;
case MNSCx_DIV_TIMER_8BIT:
scxctr |= SC0CTR_CK_TM2UFLOW_8;
break;
}
scxctr |= SC01CTR_TXE | SC01CTR_RXE;
*gdbstub_port->_control = scxctr;
tmp = *gdbstub_port->_control;
arch_local_change_intr_mask_level(
NUM2EPSW_IM(CONFIG_DEBUGGER_IRQ_LEVEL + 1));
}
/*
* initialise some of the unit hardware before gdbstub is set up
*/
asmlinkage void __init unit_init(void)
{
/* set up the external interrupts */
SET_XIRQ_TRIGGER(0, XIRQ_TRIGGER_HILEVEL);
SET_XIRQ_TRIGGER(2, XIRQ_TRIGGER_LOWLEVEL);
SET_XIRQ_TRIGGER(3, XIRQ_TRIGGER_HILEVEL);
SET_XIRQ_TRIGGER(4, XIRQ_TRIGGER_LOWLEVEL);
SET_XIRQ_TRIGGER(5, XIRQ_TRIGGER_LOWLEVEL);
#ifdef CONFIG_EXT_SERIAL_IRQ_LEVEL
set_intr_level(XIRQ0, NUM2GxICR_LEVEL(CONFIG_EXT_SERIAL_IRQ_LEVEL));
#endif
#ifdef CONFIG_ETHERNET_IRQ_LEVEL
set_intr_level(XIRQ3, NUM2GxICR_LEVEL(CONFIG_ETHERNET_IRQ_LEVEL));
#endif
}
/*
* initialise the unit hardware
*/
asmlinkage void __init unit_pci_init(void)
{
struct pci_bus bus; /* Fake bus and device */
struct pci_ops *o = &pci_direct_ampci;
u32 x;
set_intr_level(XIRQ1, NUM2GxICR_LEVEL(CONFIG_PCI_IRQ_LEVEL));
memset(&bus, 0, sizeof(bus));
MEM_PAGING_REG = 0xE8000000;
/* we need to set up the bridge _now_ or we won't be able to access the
* PCI config registers
*/
BRIDGEREGW(PCI_COMMAND) |=
PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER;
BRIDGEREGW(PCI_STATUS) = 0xF800;
BRIDGEREGB(PCI_LATENCY_TIMER) = 0x10;
BRIDGEREGL(PCI_BASE_ADDRESS_0) = 0x80000000;
BRIDGEREGB(PCI_INTERRUPT_LINE) = 1;
BRIDGEREGL(0x48) = 0x98000000; /* AMPCI base addr */
BRIDGEREGB(0x41) = 0x00; /* secondary bus
* number */
BRIDGEREGB(0x42) = 0x01; /* subordinate bus
* number */
BRIDGEREGB(0x44) = 0x01;
BRIDGEREGL(0x50) = 0x00000001;
BRIDGEREGL(0x58) = 0x00001002;
BRIDGEREGL(0x5C) = 0x00000011;
/* we also need to set up the PCI-PCI bridge */
bus.number = 0;
/* IO: 0x00000000-0x00020000 */
o->read (&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, &x);
x |= PCI_COMMAND_MASTER |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
o->write(&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, x);
o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x);
o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x);
o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x);
o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x);
o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, 0x01);
o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x);
o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, 0x00020000);
o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x);
o->write(&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, 0xEBB0EA00);
o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x);
o->write(&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, 0xE9F0E800);
o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x);
unit_disable_pcnet(&bus, o);
}
static inline void setup_jiffies_interrupt(int irq,
struct irqaction *action)
{
u16 tmp;
setup_irq(irq, action);
set_intr_level(irq, NUM2GxICR_LEVEL(CONFIG_TIMER_IRQ_LEVEL));
GxICR(irq) |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST;
tmp = GxICR(irq);
}
asmlinkage void __init unit_init(void)
{
#ifndef CONFIG_GDBSTUB_ON_TTYSx
#ifdef CONFIG_EXT_SERIAL_IRQ_LEVEL
set_intr_level(XIRQ0, NUM2GxICR_LEVEL(CONFIG_EXT_SERIAL_IRQ_LEVEL));
#endif
#endif
}
