void CCompiler::emit_dst(u32 *hw,u8 slot,struct nvfx_insn *insn)
{
struct nvfx_reg *dst = &insn->dst;
switch(dst->type) {
case NVFXSR_NONE:
hw[3] |= NV40_VP_INST_DEST_MASK;
if(slot==0)
hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
else
hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
break;
case NVFXSR_TEMP:
hw[3] |= NV40_VP_INST_DEST_MASK;
if (slot == 0)
hw[0] |= (dst->index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
else
hw[3] |= (dst->index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
break;
case NVFXSR_OUTPUT:
switch (dst->index) {
case NV30_VP_INST_DEST_CLP(0):
dst->index = NVFX_VP(INST_DEST_FOGC);
insn->mask = NVFX_VP_MASK_Y;
m_nOutputMask |= (1 << 6);
break;
case NV30_VP_INST_DEST_CLP(1):
dst->index = NVFX_VP(INST_DEST_FOGC);
insn->mask = NVFX_VP_MASK_Z;
m_nOutputMask |= (1 << 7);
break;
case NV30_VP_INST_DEST_CLP(2):
dst->index = NVFX_VP(INST_DEST_FOGC);
insn->mask = NVFX_VP_MASK_W;
m_nOutputMask |= (1 << 8);
break;
case NV30_VP_INST_DEST_CLP(3):
dst->index = NVFX_VP(INST_DEST_PSZ);
insn->mask = NVFX_VP_MASK_Y;
m_nOutputMask |= (1 << 9);
break;
case NV30_VP_INST_DEST_CLP(4):
dst->index = NVFX_VP(INST_DEST_PSZ);
insn->mask = NVFX_VP_MASK_Z;
m_nOutputMask |= (1 << 10);
break;
case NV30_VP_INST_DEST_CLP(5):
dst->index = NVFX_VP(INST_DEST_PSZ);
insn->mask = NVFX_VP_MASK_W;
m_nOutputMask |= (1 << 11);
break;
case NV40_VP_INST_DEST_COL0 : m_nOutputMask |= (1 << 0); break;
case NV40_VP_INST_DEST_COL1 : m_nOutputMask |= (1 << 1); break;
case NV40_VP_INST_DEST_BFC0 : m_nOutputMask |= (1 << 2); break;
case NV40_VP_INST_DEST_BFC1 : m_nOutputMask |= (1 << 3); break;
case NV40_VP_INST_DEST_FOGC : m_nOutputMask |= (1 << 4); break;
case NV40_VP_INST_DEST_PSZ : m_nOutputMask |= (1 << 5); break;
default:
if(dst->index>=NV40_VP_INST_DEST_TC(0) && dst->index<=NV40_VP_INST_DEST_TC(7)) m_nOutputMask |= (1<<(dst->index - NV40_VP_INST_DEST_TC0 + 14));
break;
}
hw[3] |= (dst->index << NV40_VP_INST_DEST_SHIFT);
if (slot == 0) {
hw[0] |= NV40_VP_INST_VEC_RESULT;
hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
} else {
hw[3] |= NV40_VP_INST_SCA_RESULT;
hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
}
break;
}
}
static void
emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_reg dst)
{
struct nvfx_vertex_program *vp = vpc->vp;
switch (dst.type) {
case NVFXSR_NONE:
if(!nvfx->is_nv4x)
hw[0] |= NV30_VP_INST_DEST_TEMP_ID_MASK;
else {
hw[3] |= NV40_VP_INST_DEST_MASK;
if (slot == 0)
hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
else
hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
}
break;
case NVFXSR_TEMP:
if(!nvfx->is_nv4x)
hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
else {
hw[3] |= NV40_VP_INST_DEST_MASK;
if (slot == 0)
hw[0] |= (dst.index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
else
hw[3] |= (dst.index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
}
break;
case NVFXSR_OUTPUT:
/* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
if(nvfx->is_nv4x) {
switch (dst.index) {
case NV30_VP_INST_DEST_CLP(0):
dst.index = NVFX_VP(INST_DEST_FOGC);
break;
case NV30_VP_INST_DEST_CLP(1):
dst.index = NVFX_VP(INST_DEST_FOGC);
break;
case NV30_VP_INST_DEST_CLP(2):
dst.index = NVFX_VP(INST_DEST_FOGC);
break;
case NV30_VP_INST_DEST_CLP(3):
dst.index = NVFX_VP(INST_DEST_PSZ);
break;
case NV30_VP_INST_DEST_CLP(4):
dst.index = NVFX_VP(INST_DEST_PSZ);
break;
case NV30_VP_INST_DEST_CLP(5):
dst.index = NVFX_VP(INST_DEST_PSZ);
break;
case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
}
}
if(!nvfx->is_nv4x) {
hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK;
/*XXX: no way this is entirely correct, someone needs to
* figure out what exactly it is.
*/
hw[3] |= 0x800;
} else {
hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
if (slot == 0) {
hw[0] |= NV40_VP_INST_VEC_RESULT;
hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
} else {
hw[3] |= NV40_VP_INST_SCA_RESULT;
hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
}
}
break;
default:
assert(0);
}
}