static void omap3_l4ta_write(void *opaque, target_phys_addr_t addr, uint32_t value) { struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque; switch (addr) { case 0x00: /* COMPONENT_L */ case 0x04: /* COMPONENT_H */ case 0x18: /* CORE_L */ case 0x1c: /* CORE_H */ OMAP_RO_REG(s->base + addr); break; case 0x20: /* AGENT_CONTROL_L */ s->control = value & 0x00000701; break; case 0x24: /* AGENT_CONTROL_H */ s->control_h = value & 0x100; /* TODO: shouldn't this be read-only? */ break; case 0x28: /* AGENT_STATUS_L */ if (value & 0x100) s->status &= ~0x100; /* REQ_TIMEOUT */ break; case 0x2c: /* AGENT_STATUS_H */ /* no writable bits although the register is listed as RW */ break; default: OMAP_BAD_REG(s->base + addr); break; } }
static void omap_l4ta_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; if (size != 4) { return omap_badwidth_write32(opaque, addr, value); } switch (addr) { case 0x00: /* COMPONENT */ case 0x28: /* AGENT_STATUS */ OMAP_RO_REG(addr); break; case 0x20: /* AGENT_CONTROL */ s->control = value & 0x01000700; if (value & 1) /* OCP_RESET */ s->status &= ~1; /* REQ_TIMEOUT */ break; default: OMAP_BAD_REG(addr); } }
static void omap_uart_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_uart_s *s = (struct omap_uart_s *) opaque; if (size == 4) { omap_badwidth_write8(opaque, addr, value); return; } switch (addr) { case 0x20: /* MDR1 */ s->mdr[0] = value & 0x7f; break; case 0x24: /* MDR2 */ s->mdr[1] = value & 0xff; break; case 0x40: /* SCR */ s->scr = value & 0xff; break; case 0x48: /* EBLR (OMAP2) */ s->eblr = value & 0xff; break; case 0x4C: /* OSC_12M_SEL (OMAP1) */ s->clksel = value & 1; break; case 0x44: /* SSR */ case 0x50: /* MVR */ case 0x58: /* SYSS (OMAP2) */ OMAP_RO_REG(addr); break; case 0x54: /* SYSC (OMAP2) */ s->syscontrol = value & 0x1d; if (value & 2) omap_uart_reset(s); break; case 0x5c: /* WER (OMAP2) */ s->wkup = value & 0x7f; break; case 0x60: /* CFPS (OMAP2) */ s->cfps = value & 0xff; break; default: OMAP_BAD_REG(addr); } }
static void omap_uart_write(void *opaque, target_phys_addr_t addr, uint32_t value) { struct omap_uart_s *s = (struct omap_uart_s *) opaque; addr &= 0xff; switch (addr) { case 0x20: /* MDR1 */ s->mdr[0] = value & 0x7f; break; case 0x24: /* MDR2 */ s->mdr[1] = value & 0xff; break; case 0x40: /* SCR */ s->scr = value & 0xff; break; case 0x48: /* EBLR (OMAP2) */ s->eblr = value & 0xff; break; case 0x4C: /* OSC_12M_SEL (OMAP1) */ s->clksel = value & 1; break; case 0x44: /* SSR */ case 0x50: /* MVR */ case 0x58: /* SYSS (OMAP2) */ OMAP_RO_REG(addr); break; case 0x54: /* SYSC (OMAP2) */ s->syscontrol = value & 0x1d; if (value & 2) omap_uart_reset(s); break; case 0x5c: /* WER (OMAP2) */ s->wkup = value & 0x7f; break; case 0x60: /* CFPS (OMAP2) */ s->cfps = value & 0xff; break; default: OMAP_BAD_REG(addr); } }
static void omap2_l4ta_write(void *opaque, target_phys_addr_t addr, uint32_t value) { struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; switch (addr) { case 0x00: /* COMPONENT */ case 0x28: /* AGENT_STATUS */ OMAP_RO_REG(addr); break; case 0x20: /* AGENT_CONTROL */ s->control = value & 0x01000700; if (value & 1) /* OCP_RESET */ s->status &= ~1; /* REQ_TIMEOUT */ break; default: OMAP_BAD_REG(addr); } }