/* Wait for PQI reset completion for the adapter*/
int pqisrc_wait_for_pqi_reset_completion(pqisrc_softstate_t *softs)
{
int ret = PQI_STATUS_SUCCESS;
pqi_reset_reg_t reset_reg;
int pqi_reset_timeout = 0;
uint64_t val = 0;
uint32_t max_timeout = 0;
val = PCI_MEM_GET64(softs, &softs->pqi_reg->pqi_dev_adminq_cap, PQI_ADMINQ_CAP);
max_timeout = (val & 0xFFFF00000000) >> 32;
DBG_INIT("max_timeout for PQI reset completion in 100 msec units = %u\n", max_timeout);
while(1) {
if (pqi_reset_timeout++ == max_timeout) {
return PQI_STATUS_TIMEOUT;
}
OS_SLEEP(PQI_RESET_POLL_INTERVAL);/* 100 msec */
reset_reg.all_bits = PCI_MEM_GET32(softs,
&softs->pqi_reg->dev_reset, PQI_DEV_RESET);
if (reset_reg.bits.reset_action == PQI_RESET_ACTION_COMPLETED)
break;
}
return ret;
}
/*!
* Status is currently not used
*
* @param display
* @param port_number
* @param status
*
* @return 0 on success
* @return 1 on failure
*/
static int post_program_port_plb(igd_display_context_t *display,
unsigned short port_number,
unsigned long status)
{
int ret;
igd_display_port_t *port;
igd_timing_info_t *timings;
unsigned long portreg;
EMGD_TRACE_ENTER;
port = PORT(display, port_number);
timings = PIPE(display)->timing;
/*
* Writing the sDVO control register here works around a problem
* where the sDVO port is not turning on when using a CH7308
* card in a 915 GM based system and the port order is 5200.
*
* In addition, post_set_mode() below, will report that the
* "inputs are not trained", however, this does not seem to
* have any negative effects.
*/
portreg = READ_MMIO_REG(display, port->port_reg);
WRITE_MMIO_REG(display, port->port_reg, (portreg & ~BIT31));
WRITE_MMIO_REG(display, port->port_reg, portreg);
/* Reenable/Redisable other port */
if (port->port_reg == 0x61140) {
WRITE_MMIO_REG(display, 0x61160, READ_MMIO_REG(display,
0x61160));
} else {
WRITE_MMIO_REG(display, 0x61140,
READ_MMIO_REG(display, 0x61140));
}
/*
* Added for Lakeport A0
* Port clock multiplier bits 4-7, needs to be rewritten
*/
WRITE_MMIO_REG(display, PIPE(display)->clock_reg->dpll_control,
READ_MMIO_REG(display, PIPE(display)->clock_reg->dpll_control));
/* We must wait for 150 us for the dpll clock to warm up */
OS_SLEEP(150);
ret = 0;
/* call post_set_mode() if exists */
if (port->pd_driver->post_set_mode) {
ret = port->pd_driver->post_set_mode(port->pd_context, timings,
1<<PIPE(display)->pipe_num);
if (ret) {
EMGD_ERROR("PD post_set_mode returned: 0x%x", ret);
}
}
EMGD_TRACE_EXIT;
return ret;
}
// OSTaskIdleHook ************************************************************
// This hook is invoked from the idle task.
void OSTaskIdleHook()
{ if (idleTrigger) //Issue a debug message, each time the idle task is reinvoked
{ DBGPRINT(0x00000020, "*** OSTaskIdleHook\n");
idleTrigger = FALSE;
}
OS_SLEEP(); //Give Windows a chance to run other applications to when uCOS-II idles
}
/*
* Validate the PQI mode of adapter.
*/
int pqisrc_check_pqimode(pqisrc_softstate_t *softs)
{
int ret = PQI_STATUS_FAILURE;
int tmo = 0;
uint64_t signature = 0;
DBG_FUNC("IN\n");
/* Check the PQI device signature */
tmo = PQISRC_PQIMODE_READY_TIMEOUT;
do {
signature = LE_64(PCI_MEM_GET64(softs, &softs->pqi_reg->signature, PQI_SIGNATURE));
if (memcmp(&signature, PQISRC_PQI_DEVICE_SIGNATURE,
sizeof(uint64_t)) == 0) {
ret = PQI_STATUS_SUCCESS;
break;
}
OS_SLEEP(PQISRC_MODE_READY_POLL_INTERVAL);
} while (tmo--);
PRINT_PQI_SIGNATURE(signature);
if (tmo <= 0) {
DBG_ERR("PQI Signature is invalid\n");
ret = PQI_STATUS_TIMEOUT;
goto err_out;
}
tmo = PQISRC_PQIMODE_READY_TIMEOUT;
/* Check function and status code for the device */
COND_WAIT((PCI_MEM_GET64(softs, &softs->pqi_reg->admin_q_config,
PQI_ADMINQ_CONFIG) == PQI_ADMIN_QUEUE_CONF_FUNC_STATUS_IDLE), tmo);
if (!tmo) {
DBG_ERR("PQI device is not in IDLE state\n");
ret = PQI_STATUS_TIMEOUT;
goto err_out;
}
tmo = PQISRC_PQIMODE_READY_TIMEOUT;
/* Check the PQI device status register */
COND_WAIT(LE_32(PCI_MEM_GET32(softs, &softs->pqi_reg->pqi_dev_status, PQI_DEV_STATUS)) &
PQI_DEV_STATE_AT_INIT, tmo);
if (!tmo) {
DBG_ERR("PQI Registers are not ready\n");
ret = PQI_STATUS_TIMEOUT;
goto err_out;
}
DBG_FUNC("OUT\n");
return ret;
err_out:
DBG_FUNC("OUT failed\n");
return ret;
}
/*!
* Function to sleep in micro seconds. This can be called with millisecond
* ranges.
*
* @param usec
*
* @return void
*/
void igd_pd_usleep(unsigned long usec)
{
if (usec <= 1000) {
OS_SLEEP(usec);
} else {
os_alarm_t alarm = OS_SET_ALARM((usec+999)/1000);
do {
OS_SCHEDULE();
} while (!OS_TEST_ALARM(alarm));
}
} /* end igd_pd_usleep() */
void dsp_control_plane_format_tnc(igd_context_t *context,
int enable, int plane, igd_plane_t *plane_override)
{
igd_plane_t * pl = NULL;
unsigned char *mmio = EMGD_MMIO(context->device_context.virt_mmadr);
unsigned long tmp;
if (plane_override == NULL) {
pl = (plane == 0) ? &planea_tnc : &planeb_tnc;
} else {
pl = plane_override;
}
tmp = EMGD_READ32(mmio + pl->plane_reg);
/*
* Pixel format bits (29:26) are in plane control register 0x70180 for
* Plane A and 0x71180 for Plane B
* 0110 = XRGB pixel format
* 0111 = ARGB pixel format
* Note that the plane control register is double buffered and will be
* updated on the next VBLANK operation so there is no need to sync with
* an explicit VSYNC.
*/
if(enable) {
if((tmp & DSPxCNTR_SRC_FMT_MASK) == DSPxCNTR_RGB_8888) {
tmp = tmp & (~(DSPxCNTR_SRC_FMT_MASK));
EMGD_WRITE32(tmp | DSPxCNTR_ARGB_8888, mmio + pl->plane_reg);
EMGD_READ32(mmio + pl->plane_reg);
tmp = EMGD_READ32(mmio + pl->plane_reg + 0x1c);
EMGD_WRITE32(tmp, mmio + pl->plane_reg + 0x1c);
EMGD_DEBUG("Changed pixel format from XRGB to ARGB\n");
}
} else {
if((tmp & DSPxCNTR_SRC_FMT_MASK) == DSPxCNTR_ARGB_8888) {
tmp = tmp & (~(DSPxCNTR_SRC_FMT_MASK));
EMGD_WRITE32(tmp | DSPxCNTR_RGB_8888, mmio + pl->plane_reg);
EMGD_READ32(mmio + pl->plane_reg);
tmp = EMGD_READ32(mmio + pl->plane_reg + 0x1c);
EMGD_WRITE32(tmp, mmio + pl->plane_reg + 0x1c);
OS_SLEEP(100);
EMGD_DEBUG("Changed pixel format from ARGB to XRGB\n");
}
}
EMGD_DEBUG("Plane register 0x%lX has value of 0x%X\n", pl->plane_reg,
EMGD_READ32(mmio + pl->plane_reg));
}
/* Validate the FW status PQI_CTRL_KERNEL_UP_AND_RUNNING */
int pqisrc_check_fw_status(pqisrc_softstate_t *softs)
{
int ret = PQI_STATUS_SUCCESS;
uint32_t timeout = SIS_STATUS_OK_TIMEOUT;
DBG_FUNC("IN\n");
OS_SLEEP(1000000);
COND_WAIT((GET_FW_STATUS(softs) &
PQI_CTRL_KERNEL_UP_AND_RUNNING), timeout);
if (!timeout) {
DBG_ERR("FW check status timedout\n");
ret = PQI_STATUS_TIMEOUT;
}
DBG_FUNC("OUT\n");
return ret;
}
/*!
*
* @param mmio
*
* @return void
*/
static void disable_vga_plb (unsigned char *mmio)
{
unsigned long temp;
unsigned char sr01;
EMGD_TRACE_ENTER;
/* Disable VGA plane if it is enabled. */
temp = EMGD_READ32(EMGD_MMIO(mmio) + VGACNTRL);
if ((temp & BIT31) == 0) {
/* Read SR01 */
READ_VGA(mmio, SR_PORT, 0x01, sr01);
/* Turn on SR01 bit 5 */
WRITE_VGA(mmio, SR_PORT, 0x01, sr01|BIT(5));
/* Wait for 30us */
OS_SLEEP(30);
temp |= BIT31; /* set bit 31 to disable */
temp &= ~BIT30; /* clear bit 30 to get VGA display in normal size */
EMGD_WRITE32(temp, EMGD_MMIO(mmio) + VGACNTRL);
}
/*
* When turing off the VGA plane the palette sometimes gets stuck.
* if we do a couple reads to the palette it will unstuck.
*/
if((1L<<31) & EMGD_READ32( EMGD_MMIO(mmio) + PIPEA_CONF )) {
EMGD_DEBUG("VGA Palette workaround");
EMGD_READ32(EMGD_MMIO(mmio) + DPALETTE_A);
EMGD_READ32(EMGD_MMIO(mmio) + DPALETTE_A);
}
if((1L<<31) & EMGD_READ32( EMGD_MMIO(mmio) + PIPEB_CONF )) {
EMGD_DEBUG("VGA Palette workaround");
EMGD_READ32(EMGD_MMIO(mmio) + DPALETTE_B);
EMGD_READ32(EMGD_MMIO(mmio) + DPALETTE_B);
}
EMGD_TRACE_EXIT;
}
void OSTaskIdleHook()
{ OS_SLEEP();
}
int wlan_mlme_deauth_request(wlan_if_t vaphandle, u_int8_t *macaddr, IEEE80211_REASON_CODE reason)
{
struct ieee80211vap *vap = vaphandle;
struct ieee80211_node *ni;
int error = 0;
IEEE80211_DPRINTF(vap, IEEE80211_MSG_MLME, "%s\n", __func__);
/*
* if a node exist with the given address already , use it.
* if not use bss node.
*/
ni = ieee80211_vap_find_node(vap, macaddr);
if (ni == NULL) {
if (IEEE80211_ADDR_EQ(macaddr, IEEE80211_GET_BCAST_ADDR(vap->iv_ic)))
ni = ieee80211_ref_node(vap->iv_bss);
else{
error = -EIO;
goto exit;
}
}
/* Send deauth frame */
error = ieee80211_send_deauth(ni, reason);
/* Node needs to be removed from table as well, do it only for AP/IBSS now */
#if ATH_SUPPORT_IBSS
if ((vap->iv_opmode == IEEE80211_M_HOSTAP || vap->iv_opmode == IEEE80211_M_IBSS) && ni != vap->iv_bss) {
#else
if (vap->iv_opmode == IEEE80211_M_HOSTAP && ni != vap->iv_bss) {
#if ATH_SUPPORT_AOW
ieee80211_aow_join_indicate(ni->ni_ic, AOW_STA_DISCONNECTED, ni);
#endif /* ATH_SUPPORT_AOW */
#endif /* ATH_SUPPORT_IBSS */
IEEE80211_NODE_LEAVE(ni);
}
/* claim node immediately */
ieee80211_free_node(ni);
if (error) {
goto exit;
}
/*
* Call MLME confirmation handler => mlme_deauth_complete
* This should reflect the tx completion status of the deauth frame,
* but since we don't have per frame completion, we'll always indicate success here.
*/
IEEE80211_DELIVER_EVENT_MLME_DEAUTH_COMPLETE(vap,macaddr, IEEE80211_STATUS_SUCCESS);
exit:
return error;
}
int wlan_mlme_disassoc_request(wlan_if_t vaphandle, u_int8_t *macaddr, IEEE80211_REASON_CODE reason)
{
struct ieee80211vap *vap = vaphandle;
struct ieee80211_node *ni;
int error = 0;
IEEE80211_DPRINTF(vap, IEEE80211_MSG_MLME, "%s\n", __func__);
/* Broadcast Addr - disassociate all stations */
if (IEEE80211_ADDR_EQ(macaddr, IEEE80211_GET_BCAST_ADDR(vap->iv_ic))) {
if (vap->iv_opmode == IEEE80211_M_STA) {
IEEE80211_DPRINTF(vap, IEEE80211_MSG_MLME,
"%s: unexpected station vap with all 0xff mac address", __func__);
ASSERT(0);
goto exit;
} else {
/* Iterate station list only when PMF is not enabled */
if (!wlan_vap_is_pmf_enabled(vap)) {
wlan_iterate_station_list(vap, sta_disassoc, NULL);
goto exit;
}
}
}
/*
* if a node exist with the given address already , use it.
* if not use bss node.
*/
ni = ieee80211_vap_find_node(vap, macaddr);
if (ni == NULL) {
if (IEEE80211_ADDR_EQ(macaddr, IEEE80211_GET_BCAST_ADDR(vap->iv_ic)))
ni = ieee80211_ref_node(vap->iv_bss);
else{
error = -EIO;
goto exit;
}
}
/* Send disassoc frame */
error = ieee80211_send_disassoc(ni, reason);
/* Node needs to be removed from table as well, do it only for AP now */
if (vap->iv_opmode == IEEE80211_M_HOSTAP && ni != vap->iv_bss) {
#if ATH_SUPPORT_AOW
ieee80211_aow_join_indicate(ni->ni_ic, AOW_STA_DISCONNECTED, ni);
#endif /* ATH_SUPPORT_AOW */
IEEE80211_NODE_LEAVE(ni);
}
/* claim node immediately */
ieee80211_free_node(ni);
if (error) {
goto exit;
}
/*
* Call MLME confirmation handler => mlme_disassoc_complete
* This should reflect the tx completion status of the disassoc frame,
* but since we don't have per frame completion, we'll always indicate success here.
*/
IEEE80211_DELIVER_EVENT_MLME_DISASSOC_COMPLETE(vap, macaddr, reason, IEEE80211_STATUS_SUCCESS);
exit:
return error;
}
int wlan_mlme_start_bss(wlan_if_t vaphandle)
{
struct ieee80211vap *vap = vaphandle;
struct ieee80211_mlme_priv *mlme_priv = vap->iv_mlme_priv;
int error = 0;
IEEE80211_DPRINTF(vap, IEEE80211_MSG_MLME, "%s\n", __func__);
switch(vap->iv_opmode) {
case IEEE80211_M_IBSS:
IEEE80211_DPRINTF(vap, IEEE80211_MSG_MLME, "%s: Create adhoc bss\n", __func__);
/* Reset state */
mlme_priv->im_connection_up = 0;
error = mlme_create_adhoc_bss(vap);
break;
case IEEE80211_M_MONITOR:
case IEEE80211_M_HOSTAP:
case IEEE80211_M_BTAMP:
/*
* start the AP . the channel/ssid should have been setup already.
*/
IEEE80211_DPRINTF(vap, IEEE80211_MSG_MLME, "%s: Create infrastructure(AP) bss\n", __func__);
error = mlme_create_infra_bss(vap);
break;
default:
ASSERT(0);
}
return error;
}
bool wlan_coext_enabled(wlan_if_t vaphandle)
{
struct ieee80211com *ic = vaphandle->iv_ic;
return (ic->ic_flags & IEEE80211_F_COEXT_DISABLE) ? FALSE : TRUE;
}
void wlan_determine_cw(wlan_if_t vaphandle, wlan_chan_t channel)
{
struct ieee80211com *ic = vaphandle->iv_ic;
int is_chan_ht40 = channel->ic_flags & (IEEE80211_CHAN_11NG_HT40PLUS |
IEEE80211_CHAN_11NG_HT40MINUS);
if (is_chan_ht40 && (channel->ic_flags & IEEE80211_CHAN_HT40INTOL)) {
ic->ic_bss_to20(ic);
}
}
static void
sta_deauth(void *arg, struct ieee80211_node *ni)
{
struct ieee80211vap *vap = ni->ni_vap;
u_int8_t macaddr[6];
IEEE80211_DPRINTF(vap, IEEE80211_MSG_MLME, "%s: deauth station %s \n",
__func__,ether_sprintf(ni->ni_macaddr));
IEEE80211_ADDR_COPY(macaddr, ni->ni_macaddr);
if (ni->ni_associd) {
/*
* if it is associated, then send disassoc.
*/
ieee80211_send_deauth(ni, IEEE80211_REASON_AUTH_LEAVE);
}
IEEE80211_NODE_LEAVE(ni);
IEEE80211_DELIVER_EVENT_MLME_DEAUTH_INDICATION(vap, macaddr, IEEE80211_REASON_AUTH_LEAVE);
}
static void
sta_disassoc(void *arg, struct ieee80211_node *ni)
{
struct ieee80211vap *vap = ni->ni_vap;
u_int8_t macaddr[6];
IEEE80211_DPRINTF(vap, IEEE80211_MSG_MLME, "%s: disassoc station %s \n",
__func__,ether_sprintf(ni->ni_macaddr));
IEEE80211_ADDR_COPY(macaddr, ni->ni_macaddr);
if (ni->ni_associd) {
/*
* if it is associated, then send disassoc.
*/
ieee80211_send_disassoc(ni, IEEE80211_REASON_ASSOC_LEAVE);
#if ATH_SUPPORT_AOW
ieee80211_aow_join_indicate(ni->ni_ic, AOW_STA_DISCONNECTED, ni);
#endif /* ATH_SUPPORT_AOW */
}
IEEE80211_NODE_LEAVE(ni);
IEEE80211_DELIVER_EVENT_MLME_DISASSOC_COMPLETE(vap, macaddr,
IEEE80211_REASON_ASSOC_LEAVE, IEEE80211_STATUS_SUCCESS);
}
int wlan_mlme_stop_bss(wlan_if_t vaphandle, int flags)
{
#define WAIT_RX_INTERVAL 10000
u_int32_t elapsed_time = 0;
struct ieee80211vap *vap = vaphandle;
struct ieee80211_mlme_priv *mlme_priv = vap->iv_mlme_priv;
int error = 0;
IEEE80211_DPRINTF(vap, IEEE80211_MSG_MLME, "%s flags = 0x%x\n", __func__, flags);
/*
* Wait for current rx path to finish. Assume only one rx thread.
*/
if (flags & WLAN_MLME_STOP_BSS_F_WAIT_RX_DONE) {
do {
if (OS_ATOMIC_CMPXCHG(&vap->iv_rx_gate, 0, 1) == 0) {
break;
}
OS_SLEEP(WAIT_RX_INTERVAL);
elapsed_time += WAIT_RX_INTERVAL;
if (elapsed_time > (100 * WAIT_RX_INTERVAL))
ieee80211_note (vap,"%s: Rx pending count stuck. Investigate!!!\n", __func__);
} while (1);
}
switch(vap->iv_opmode) {
#if UMAC_SUPPORT_IBSS
case IEEE80211_M_IBSS:
mlme_stop_adhoc_bss(vap, flags);
break;
#endif
case IEEE80211_M_HOSTAP:
case IEEE80211_M_BTAMP:
/* disassoc/deauth all stations */
IEEE80211_DPRINTF(vap, IEEE80211_MSG_MLME, "%s: dsassocing/deauth all stations \n", __func__);
if(vap->iv_send_deauth)
wlan_iterate_station_list(vap, sta_deauth, NULL);
else
wlan_iterate_station_list(vap, sta_disassoc, NULL);
break;
case IEEE80211_M_STA:
/* There should be no mlme requests pending */
ASSERT(vap->iv_mlme_priv->im_request_type == MLME_REQ_NONE);
/* Reset state variables */
mlme_priv->im_connection_up = 0;
mlme_sta_swbmiss_timer_stop(vap);
ieee80211_sta_leave(vap->iv_bss);
break;
default:
break;
}
if (flags & WLAN_MLME_STOP_BSS_F_FORCE_STOP_RESET) {
/* put vap in init state */
ieee80211_vap_stop(vap, TRUE);
} else {
/* put vap in stopping state */
if (flags & WLAN_MLME_STOP_BSS_F_STANDBY)
ieee80211_vap_standby(vap);
else
ieee80211_vap_stop(vap, FALSE);
}
if (!(flags & WLAN_MLME_STOP_BSS_F_NO_RESET))
error = ieee80211_reset_bss(vap);
/*
* Release the rx mutex.
*/
if (flags & WLAN_MLME_STOP_BSS_F_WAIT_RX_DONE) {
(void) OS_ATOMIC_CMPXCHG(&vap->iv_rx_gate, 1, 0);
}
return error;
#undef WAIT_RX_INTERVAL
}
/*!
*
* @param context
*
* @return void
*/
static void reset_plane_pipe_ports_plb(igd_context_t *context)
{
igd_plane_t *plane;
igd_display_pipe_t *pipe;
igd_display_port_t *port,*tv_port=NULL;
unsigned long temp;
unsigned long i;
unsigned char *mmio;
inter_module_dispatch_t *md;
EMGD_TRACE_ENTER;
/*
* Disable all plane, pipe and port registers because the
* bios may have been using a different set. Only unset the
* enable bit.
*/
mmio = EMGD_MMIO(context->device_context.virt_mmadr);
md = &context->mod_dispatch;
disable_vga_plb(EMGD_MMIO(mmio));
/* Turn off ports */
port = NULL;
while((port = md->dsp_get_next_port(context, port, 0)) != NULL) {
/* if the port is TV, then don't set the power to S3 as this causes
* blank screen on analog port after killx or cosole mode,
* probably because the external clock needs to be on till the pipes and
* DPLLs are off
*/
if (port->pd_driver) {
#ifndef CONFIG_FASTBOOT
if(port->pd_type == PD_DISPLAY_TVOUT) {
tv_port = port;
}else {
port->pd_driver->set_power(port->pd_context, IGD_POWERSTATE_D3);
}
#endif
}
/* Disable WRITE protection on PIPE B for parts with Int-LVDS*/
/* This should never happen as the panel power was set to D3 above */
if (port->port_reg == LVDSCNTR) {
if(EMGD_READ32(EMGD_MMIO(mmio) + LVDS_PNL_PWR_CTL) & 0x1) {
EMGD_WRITE32(0xABCD0000, EMGD_MMIO(mmio) + LVDS_PNL_PWR_CTL);
i=0;
while(i++ < 0x10) {
OS_SLEEP(10);
if((EMGD_READ32(EMGD_MMIO(mmio)+LVDS_PNL_PWR_STS)&BIT(31))==0) {
break;
}
}
}
}
temp = EMGD_READ32(EMGD_MMIO(mmio) + port->port_reg);
EMGD_WRITE32((temp & ~BIT31), EMGD_MMIO(mmio) + port->port_reg);
}
plane = NULL;
while ((plane = md->dsp_get_next_plane(context, plane, 1)) != NULL) {
/* Only display display planes.
* Leave cursor, VGA, overlay, sprite planes alone since they will
* need a different disable bit/sequence.
*/
temp = EMGD_READ32(EMGD_MMIO(mmio) + plane->plane_reg);
if ((plane->plane_features & IGD_PLANE_DISPLAY)) {
if ( temp & BIT31 ) {
if(plane->plane_reg == DSPACNTR) {
EMGD_WRITE32((temp & device_data->plane_a_preserve),
EMGD_MMIO(mmio) + plane->plane_reg);
}
else { /* if it's plane b or plane c */
EMGD_WRITE32((temp & device_data->plane_b_c_preserve),
EMGD_MMIO(mmio) + plane->plane_reg);
}
EMGD_WRITE32(0, EMGD_MMIO(mmio) + plane->plane_reg+4);
}
} else if ((plane->plane_features & IGD_PLANE_CURSOR)) {
EMGD_WRITE32((temp & 0xffffffe8),
EMGD_MMIO(mmio) + plane->plane_reg);
EMGD_WRITE32(0, EMGD_MMIO(mmio) + plane->plane_reg+4);
}
}
/* Turn off pipes */
pipe = NULL;
while ((pipe = md->dsp_get_next_pipe(context, pipe, 0))) {
wait_for_vblank_plb(EMGD_MMIO(mmio), pipe->pipe_reg);
temp = EMGD_READ32(EMGD_MMIO(mmio) + pipe->pipe_reg);
if ( temp & BIT31 ) {
EMGD_WRITE32((temp & device_data->pipe_preserve),
EMGD_MMIO(mmio) + pipe->pipe_reg);
}
}
/* pipes and DPLLs are off, now set the power for TV */
if(tv_port && tv_port->pd_driver) {
tv_port->pd_driver->set_power(tv_port->pd_context, IGD_POWERSTATE_D3);
}
EMGD_TRACE_EXIT;
} /* end reset_plane_pipe_ports */
/**
* Main function task
* @param void
* @returns void
*/
void CONIN_vTask(void) {
static float u0 = 0;
static float uIn1 = 0;
static float uIn2 = 0;
float new_count1 = 0;
float new_count2 = 0;
for (;;)
{
if(CONIN_MSECState == MSEC_enRunning)
{
new_count1 = EQep1Regs.QPOSCNT;
if((new_count1 > 0x7FFFFFFF) && (new_count1 <= 0xFFFFFFFF))
{
/**
* ================================= Izquierda */
new_count1 = new_count1 - EQep1Regs.QPOSMAX;
uIn1 = ((new_count1*EQEP__nKEncoder)/EQEP__nDivEncoder)-EQEP__nOffsetMilim1;
}
else if ((new_count1 < 0x7FFFFFFF) && (new_count1 >= 0))
{
/**
* ================================= Derecha */
uIn1 = ((new_count1*EQEP__nKEncoder)/EQEP__nDivEncoder)-EQEP__nOffsetMilim1;
}
new_count2 = EQep2Regs.QPOSCNT;
if((new_count2 > 0x7FFFFFFF) && (new_count2 <= 0xFFFFFFFF))
{
/**
* ================================= Izquierda */
new_count2 = new_count2 - EQep2Regs.QPOSMAX;
uIn2 = ((new_count2*EQEP__nKEncoder)/EQEP__nDivEncoder)-EQEP__nOffsetMilim2;
}
else if ((new_count2 < 0x7FFFFFFF) && (new_count2 >= 0))
{
/**
* ================================= Derecha */
uIn2 = ((new_count2*EQEP__nKEncoder)/EQEP__nDivEncoder)-EQEP__nOffsetMilim2;
uIn2 = -1.0*uIn2;/** TODO: Figure out why sign is different between Enc1 and Enc2 */
}
switch(SYS_ControlInputSource)
{
case MSEC_enInput1:
u0 = uIn1;
break;
case MSEC_enInput2:
u0 = uIn2;
break;
default:
/**
* ================================= wrong condition */
break;
}
/**
* u() and y() buffers shifting
*/
CONIN__vBufferShift();
/**
* u(0) update
*/
CONIN_PosInput1 = uIn1;
CONIN_PosInput2 = uIn2;
u0 = CONIN_SP - u0;
CONIN_pfu[0] = u0;
}
OS_SLEEP((Uint32)(CONIN_TaskPeriod));
}
}
unsigned int ovl2_send_instr_tnc(
igd_display_context_t *display,
ovl2_reg_tnc_t *spritec_regs_tnc,
unsigned int flags)
{
unsigned char *mmio = MMIO(display);
unsigned long tmp, pipe_reg, pipe_num;
inter_module_dispatch_t *md;
platform_context_tnc_t * platform;
EMGD_TRACE_ENTER;
/* We dont need the CMD_WAIT_OVL2_TNC instruction coz
* our alter_ovl code already querried status
* for last flip completion before getting here. See
* micro_prepare_ovl2_tnc called by alter_ovl2_tnc.
* It calls query overlay before the next flip
*/
/*If Overlay+FB Blend is requested and the FB is xRGB
*turn on the ARGB format. */
if(ovl_context->fb_blend_ovl) {
if((flags & IGD_OVL_ALTER_ON) == IGD_OVL_ALTER_ON) {
tmp = EMGD_READ32(mmio + PLANE(display)->plane_reg);
if((tmp & 0x3c000000) == 0x18000000) {
tmp = tmp & 0xc3FFFFFF;
EMGD_WRITE32(tmp | 0x1c000000, mmio + PLANE(display)->plane_reg);
EMGD_READ32(mmio + PLANE(display)->plane_reg);
tmp = EMGD_READ32(mmio + PLANE(display)->plane_reg + 0x1c);
EMGD_WRITE32(tmp, mmio + PLANE(display)->plane_reg + 0x1c);
}
} else {
tmp = EMGD_READ32(mmio + PLANE(display)->plane_reg);
if((tmp & 0x3c000000) == 0x1c000000) {
tmp = tmp & 0xc3FFFFFF;
EMGD_WRITE32(tmp | 0x18000000, mmio + PLANE(display)->plane_reg);
EMGD_READ32(mmio + PLANE(display)->plane_reg);
tmp = EMGD_READ32(mmio + PLANE(display)->plane_reg + 0x1c);
EMGD_WRITE32(tmp, mmio + PLANE(display)->plane_reg + 0x1c);
OS_SLEEP(100);
}
}
}
/* Send a load register instruction to write the Plane C sprite address
* which is the trigger register.
* This is an instruction, so it happens after blend, and since it
* is an instruction, we do not have to poll waiting for it. */
EMGD_WRITE32(spritec_regs_tnc->start, mmio + 0x7219C);
/* Since the ISR bit 0x100 actually doesnt work,
* we need to setup a trigger for a VBLANK event
* on Pipe-B to guarantee that the Sprite-C had
* actually completed its last flip.
* (ISR bit was tested on Poulsbo D2 by capturing
* timestamps of quick successive alter_overlays..
* checked ISR bit directly after the write to Sprite
* C Address register in process_vqueue handling..
* the ISR bit never changed
*/
md = &display->context->mod_dispatch;
platform = (platform_context_tnc_t *)display->context->
platform_context;
pipe_num = PIPE(display)->pipe_num;
if(pipe_num){
pipe_reg = PIPEB_STAT;
} else {
pipe_reg = PIPEA_STAT;
}
if(md && md->set_flip_pending){
OS_PTHREAD_MUTEX_LOCK(&platform->flip_mutex);
md->set_flip_pending(MMIO(display), pipe_reg);
OS_PTHREAD_MUTEX_UNLOCK(&platform->flip_mutex);
}
ovl_context->sync2 = WAIT_FOR_FLIP;
EMGD_TRACE_EXIT;
return IGD_SUCCESS;
}
unsigned int ovl2_send_instr_plb(
igd_display_context_t *display,
ovl2_reg_plb_t *spritec_regs_plb,
unsigned int flags)
{
unsigned char * mmio = MMIO(display);
unsigned long tmp;
inter_module_dispatch_t *md;
platform_context_plb_t * platform;
unsigned int pipe_num;
unsigned long pipe_reg;
int ret;
EMGD_TRACE_ENTER;
/* We dont need the CMD_WAIT_OVL2_PLB instruction coz
* our alter_ovl code already querried status
* for last flip completion before getting here. See
* micro_prepare_ovl2_plb called by alter_ovl2_plb.
* It calls query overlay before the next flip
*/
/*
* If Overlay + FB Blend is requested and the FB is xRGB
* turn on the ARGB format.
*/
if(ovl_context->fb_blend_ovl) {
if ((flags & IGD_OVL_ALTER_ON) != IGD_OVL_ALTER_ON) {
tmp = EMGD_READ32(mmio + PLANE(display)->plane_reg);
if((tmp & 0x3c000000) == 0x1c000000) {
tmp = tmp & 0xc3FFFFFF;
EMGD_WRITE32(tmp | 0x18000000, mmio + PLANE(display)->plane_reg);
tmp = EMGD_READ32(mmio + PLANE(display)->plane_reg + 4);
EMGD_WRITE32(tmp, mmio + PLANE(display)->plane_reg + 4);
OS_SLEEP(100);
}
} else {
tmp = EMGD_READ32(mmio + PLANE(display)->plane_reg);
if((tmp & 0x3c000000) == 0x18000000) {
EMGD_WRITE32(tmp | 0x1c000000, mmio + PLANE(display)->plane_reg);
tmp = EMGD_READ32(mmio + PLANE(display)->plane_reg + 4);
EMGD_WRITE32(tmp, mmio + PLANE(display)->plane_reg + 4);
}
}
}
/* Send a load register instruction to write the Plane C sprite address
* which is the trigger register.
* This is an instruction, so it happens after blend, and since it
* is an instruction, we do not have to poll waiting for it. */
EMGD_WRITE32(spritec_regs_plb->start, mmio + 0x72184);
md = &display->context->mod_dispatch;
platform = (platform_context_plb_t *)display->context->
platform_context;
pipe_num = PIPE(display)->pipe_num;
if(pipe_num){
pipe_reg = 0x71024;
} else {
pipe_reg = 0x70024;
}
if(md && md->set_flip_pending){
/* For second overlay, Poulsbo has no ISR bit
* to reflect the flip pending for Display
* Sprite C. So we use Pipe-B vblank status
* as a substitute
*/
ret = OS_PTHREAD_MUTEX_LOCK(&platform->flip_mutex);
md->set_flip_pending(MMIO(display), pipe_reg);
OS_PTHREAD_MUTEX_UNLOCK(&platform->flip_mutex);
}
ovl_context->sync2 = 0;
display->context->dispatch.sync(display,
IGD_PRIORITY_NORMAL,
&ovl_context->sync2,
IGD_SYNC_NONBLOCK);
EMGD_TRACE_EXIT;
return IGD_SUCCESS;
}
