/*******************************************************************************
* Function Name : USBF_FCD_EP_Flush()
* Description : This Function flushes the buffer.
* Input : Endpoint Address.
* Output : None
* Return : status
*******************************************************************************/
uint32_t PCD_EP_Flush (uint8_t ep_addr)
{
uint8_t is_out = 0;
uint8_t ep_nbr = 0;
ep_nbr = ep_addr & 0x7F;
is_out = ((ep_addr & 0x80) == 0x80) ? 0 : 1;
if (is_out == 0)
{
OTGD_FS_FlushTxFifo(ep_nbr);
}
else
{
OTGD_FS_FlushRxFifo();
}
PCD_EP_ClrStall(ep_addr);
return (0);
}
/*******************************************************************************
* Function Name : OTGD_FS_Handle_UsbReset_ISR
* Description : This interrupt occurs when a USB Reset is detected.
* Input : None
* Output : None
* Return : status
*******************************************************************************/
uint32_t OTGD_FS_Handle_UsbReset_ISR(void)
{
USB_OTG_DAINT_TypeDef daintmsk;
USB_OTG_DOEPMSKx_TypeDef doepmsk;
USB_OTG_DIEPMSKx_TypeDef diepmsk;
USB_OTG_DCFG_TypeDef dcfg;
USB_OTG_DCTL_TypeDef dctl;
USB_OTG_GINTSTS_TypeDef gintsts;
uint32_t i = 0;
daintmsk.d32 = 0;
doepmsk.d32 = 0;
diepmsk.d32 = 0;
dcfg.d32 =0;
dctl.d32 = 0;
gintsts.d32 = 0;
/* Clear the Remote Wakeup Signalling */
dctl.b.rmtwkupsig = 1;
USB_OTG_MODIFY_REG32(&USB_OTG_FS_regs.DEV->DCTL, dctl.d32, 0 );
/* Flush the NP Tx FIFO */
OTGD_FS_FlushTxFifo( 0 );
/* clear pending interrupts */
for (i = 0; i < NUM_TX_FIFOS ; i++)
{
USB_OTG_WRITE_REG32(&USB_OTG_FS_regs.DINEPS[i]->DIEPINTx, 0xFF);
USB_OTG_WRITE_REG32(&USB_OTG_FS_regs.DOUTEPS[i]->DOEPINTx, 0xFF);
}
USB_OTG_WRITE_REG32(&USB_OTG_FS_regs.DEV->DAINT, 0xFFFFFFFF );
daintmsk.ep.in = 1;
daintmsk.ep.out = 1;
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DAINTMSK, daintmsk.d32 );
doepmsk.b.setup = 1;
doepmsk.b.b2bsetup = 1;
doepmsk.b.xfercompl = 1;
doepmsk.b.epdis = 1;
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DOEPMSK, doepmsk.d32 );
diepmsk.b.xfercompl = 1;
diepmsk.b.timeout = 1;
diepmsk.b.epdis = 1;
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DIEPMSK, diepmsk.d32 );
/* Reset Device Address */
dcfg.d32 = USB_OTG_READ_REG32( &USB_OTG_FS_regs.DEV->DCFG);
dcfg.b.devaddr = 0;
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DCFG, dcfg.d32);
/* setup EP0 to receive SETUP packets */
PCD_EP0_OutStart();
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.usbreset = 1;
USB_OTG_WRITE_REG32 (&USB_OTG_FS_regs.GREGS->GINTSTS, gintsts.d32);
/* Call the user reset function */
OTGD_FS_DEVICE_RESET;
/* Call user function */
INTR_USBRESET_Callback();
return 1;
}
/*******************************************************************************
* Function Name : OTGD_FS_CoreInitDev
* Description : Initialize the USB_OTG controller registers for device mode
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_CoreInitDev (void)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_DEPCTLx_TypeDef depctl;
USB_OTG_DCFG_TypeDef dcfg;
USB_OTG_FIFOSIZ_TypeDef txfifosize0;
USB_OTG_FIFOSIZ_TypeDef txfifosize;
uint32_t i = 0;
depctl.d32 = 0;
dcfg.d32 = 0;
txfifosize0.d32 = 0;
txfifosize.d32 = 0;
/* Set device speed */
InitDevSpeed ();
/* Restart the Phy Clock */
USB_OTG_WRITE_REG32(USB_OTG_FS_regs.PCGCCTL, 0);
/* Device configuration register */
dcfg.d32 = USB_OTG_READ_REG32( &USB_OTG_FS_regs.DEV->DCFG);
dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80;
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DCFG, dcfg.d32 );
/* set Rx FIFO size */
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.GREGS->GRXFSIZ, RX_FIFO_SIZE);
/* EP0 TX*/
txfifosize0.b.depth = TX0_FIFO_SIZE;
txfifosize0.b.startaddr = RX_FIFO_SIZE;
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.GREGS->DIEPTXF0, txfifosize0.d32 );
/* EP1 TX*/
txfifosize.b.startaddr = txfifosize0.b.startaddr + txfifosize0.b.depth;
txfifosize.b.depth = TX1_FIFO_SIZE;
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.GREGS->DIEPTXFx[0], txfifosize.d32 );
/* EP2 TX*/
txfifosize.b.startaddr += txfifosize.b.depth;
txfifosize.b.depth = TX2_FIFO_SIZE;
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.GREGS->DIEPTXFx[1], txfifosize.d32 );
/* EP3 TX*/
txfifosize.b.startaddr += txfifosize.b.depth;
txfifosize.b.depth = TX3_FIFO_SIZE;
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.GREGS->DIEPTXFx[2], txfifosize.d32 );
/* Flush the FIFOs */
OTGD_FS_FlushTxFifo(0x10); /* all Tx FIFOs */
OTGD_FS_FlushRxFifo();
/* Clear all pending Device Interrupts */
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DIEPMSK, 0 );
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DOEPMSK, 0 );
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DAINT, 0xFFFFFFFF );
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DAINTMSK, 0 );
for (i = 0; i < NUM_TX_FIFOS; i++)
{
depctl.d32 = USB_OTG_READ_REG32(&USB_OTG_FS_regs.DINEPS[i]->DIEPCTLx);
if (depctl.b.epena)
{
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
else
{
depctl.d32 = 0;
}
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DINEPS[i]->DIEPCTLx, depctl.d32);
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DINEPS[i]->DIEPTSIZx, 0);
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DINEPS[i]->DIEPINTx, 0xFF);
}
for (i = 0; i < 1/* NUM_OUT_EPS*/; i++)
{
depctl.d32 = USB_OTG_READ_REG32(&USB_OTG_FS_regs.DOUTEPS[i]->DOEPCTLx);
if (depctl.b.epena)
{
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
else
{
depctl.d32 = 0;
}
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DOUTEPS[i]->DOEPCTLx, depctl.d32);
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DOUTEPS[i]->DOEPTSIZx, 0);
USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DOUTEPS[i]->DOEPINTx, 0xFF);
}
OTGD_FS_EnableDevInt();
return status;
}
/*******************************************************************************
* Function Name : OTGD_FS_CoreInitDev
* Description : Initialize the USB_OTG controller registers for device mode
* Input : None
* Output : None
* Return : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_CoreInitDev (void)
{
USB_OTG_Status status = USB_OTG_OK;
USB_OTG_dev_ep_ctl_data depctl;
uint32_t i;
USB_OTG_dev_cfg_data dcfg;
USB_OTG_fifo_size_data nptxfifosize;
USB_OTG_fifo_size_data txfifosize;
USB_OTG_dev_in_ep_msk_data msk;
dcfg.d32 = 0;
/* Set device speed */
InitDevSpeed ();
/* Restart the Phy Clock */
WRITE_REG32(core_regs.pcgcctl, 0);
/* Device configuration register */
dcfg.d32 = READ_REG32( &core_regs.dev_regs->dev_cfg);
dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80;
WRITE_REG32( &core_regs.dev_regs->dev_cfg, dcfg.d32 );
/* set Rx FIFO size */
WRITE_REG32( &core_regs.common_regs->rx_fifo_siz, RX_FIFO_SIZE);
/* Non-periodic Tx FIFO */
nptxfifosize.b.depth = DEV_NP_TX_FIFO_SIZE;
nptxfifosize.b.startaddr = RX_FIFO_SIZE;
WRITE_REG32( &core_regs.common_regs->np_tx_fifo_siz, nptxfifosize.d32 );
txfifosize.b.depth = DEV_NP_TX_FIFO_SIZE;
WRITE_REG32( &core_regs.common_regs->dev_p_tx_fsiz_dieptxf[0], txfifosize.d32 );
txfifosize.b.startaddr += txfifosize.b.depth;
txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
/* Flush the FIFOs */
OTGD_FS_FlushTxFifo(0x10); /* all Tx FIFOs */
OTGD_FS_FlushRxFifo();
/* Clear all pending Device Interrupts */
WRITE_REG32( &core_regs.dev_regs->dev_in_ep_msk, 0 );
WRITE_REG32( &core_regs.dev_regs->dev_out_ep_msk, 0 );
WRITE_REG32( &core_regs.dev_regs->dev_all_int, 0xFFFFFFFF );
WRITE_REG32( &core_regs.dev_regs->dev_all_int_msk, 0 );
for (i = 0; i <= MAX_TX_FIFOS; i++)
{
depctl.d32 = READ_REG32(&core_regs.inep_regs[i]->dev_in_ep_ctl);
if (depctl.b.epena)
{
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
else
{
depctl.d32 = 0;
}
WRITE_REG32( &core_regs.inep_regs[i]->dev_in_ep_ctl, depctl.d32);
WRITE_REG32( &core_regs.inep_regs[i]->dev_in_ep_txfer_siz, 0);
WRITE_REG32( &core_regs.inep_regs[i]->dev_in_ep_int, 0xFF);
}
for (i = 0; i < 1/* NUM_OUT_EPS*/; i++)
{
depctl.d32 = READ_REG32(&core_regs.outep_regs[i]->dev_out_ep_ctl);
if (depctl.b.epena)
{
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
else
{
depctl.d32 = 0;
}
WRITE_REG32( &core_regs.outep_regs[i]->dev_out_ep_ctl, depctl.d32);
WRITE_REG32( &core_regs.outep_regs[i]->dev_out_ep_txfer_siz, 0);
WRITE_REG32( &core_regs.outep_regs[i]->dev_out_ep_int, 0xFF);
}
msk.d32 = 0;
msk.b.txfifoundrn = 1;
MODIFY_REG32(&core_regs.dev_regs->dev_in_ep_msk, msk.d32, msk.d32);
OTGD_FS_EnableDevInt();
return status;
}
