};
void bootblock_mainboard_early_init(void)
{
soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
}
static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
}
static const struct pad_config padcfgs[] = {
/* Board build id bits 1:0 */
PAD_CFG_GPIO_INPUT(KB_COL4, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE),
};
void bootblock_mainboard_init(void)
{
set_clock_sources();
/* Set up controllers and pads to load romstage. */
soc_configure_funits(funits, ARRAY_SIZE(funits));
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
i2c_init(I2CPWR_BUS);
pmic_init(I2CPWR_BUS);
}
static const struct pad_config uart_console_pads[] = {
/* UARTA: tx and rx. */
PAD_CFG_SFIO(KB_ROW9, PINMUX_PULL_NONE, UA3),
PAD_CFG_SFIO(KB_ROW10, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UA3),
/*
* Disable UART2 pads as they are default connected to UARTA controller.
*/
PAD_CFG_UNUSED(UART2_RXD),
PAD_CFG_UNUSED(UART2_TXD),
PAD_CFG_UNUSED(UART2_RTS_N),
PAD_CFG_UNUSED(UART2_CTS_N),
};
static const struct pad_config padcfgs[] = {
/* Board ID bits 3:0 */
PAD_CFG_GPIO_INPUT(GPIO_X4_AUD, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(GPIO_X1_AUD, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_ROW17, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE),
/* Power Button */
PAD_CFG_GPIO_INPUT(KB_COL0, PINMUX_PULL_NONE),
/* Lid Open Switch */
PAD_CFG_GPIO_INPUT(KB_ROW4, PINMUX_PULL_UP),
};
static const struct pad_config i2cpad[] = {
/* PMIC i2C bus */
PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
#include <soc/spi.h>
#include <soc/nvidia/tegra/dc.h>
#include <soc/display.h>
static const struct pad_config sdmmc3_pad[] = {
/* MMC3(SDCARD) */
PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3),
PAD_CFG_SFIO(SDMMC3_CMD, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
PAD_CFG_SFIO(SDMMC3_DAT0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
PAD_CFG_SFIO(SDMMC3_DAT1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
PAD_CFG_SFIO(SDMMC3_DAT2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
PAD_CFG_SFIO(SDMMC3_DAT3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
PAD_CFG_SFIO(SDMMC3_CLK_LB_IN, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
PAD_CFG_SFIO(SDMMC3_CLK_LB_OUT, PINMUX_INPUT_ENABLE | PINMUX_PULL_DOWN, SDMMC3),
/* MMC3 Card Detect pin */
PAD_CFG_GPIO_INPUT(SDMMC3_CD_N, PINMUX_PULL_UP),
/* Disable SD card reader power so it can be reset even on warm boot.
Payloads must enable power before accessing SD card slots. */
PAD_CFG_GPIO_OUT0(KB_ROW0, PINMUX_PULL_NONE),
};
static const struct pad_config sdmmc4_pad[] = {
/* MMC4 (eMMC) */
PAD_CFG_SFIO(SDMMC4_CLK, PINMUX_INPUT_ENABLE, SDMMC4),
PAD_CFG_SFIO(SDMMC4_CMD, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT4, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT5, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
#include <soc/spi.h>
#include <soc/nvidia/tegra/dc.h>
#include <soc/display.h>
#include <vendorcode/google/chromeos/chromeos.h>
static const struct pad_config sdmmc1_pad[] = {
/* MMC1(SDCARD) */
PAD_CFG_SFIO(SDMMC1_CLK, PINMUX_INPUT_ENABLE, SDMMC1),
PAD_CFG_SFIO(SDMMC1_CMD, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC1),
PAD_CFG_SFIO(SDMMC1_DAT0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC1),
PAD_CFG_SFIO(SDMMC1_DAT1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC1),
PAD_CFG_SFIO(SDMMC1_DAT2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC1),
PAD_CFG_SFIO(SDMMC1_DAT3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC1),
/* MMC1 Card Detect pin */
PAD_CFG_GPIO_INPUT(GPIO_PZ1, PINMUX_PULL_UP),
/* Disable SD card reader power so it can be reset even on warm boot.
Payloads must enable power before accessing SD card slots. */
PAD_CFG_GPIO_OUT0(GPIO_PZ4, PINMUX_PULL_NONE),
};
static const struct pad_config audio_codec_pads[] = {
/* GPIO_X1_AUD(BB3) is AUDIO_LDO_EN (->CODEC RESET_N pin) */
PAD_CFG_GPIO_OUT1(GPIO_X1_AUD, PINMUX_PULL_DOWN),
};
static const struct pad_config padcfgs[] = {
/* We pull the USB VBUS signals up but keep them as inputs since the
* voltage source likes to drive them low on overcurrent conditions */
PAD_CFG_GPIO_INPUT(USB_VBUS_EN1, PINMUX_PULL_NONE | PINMUX_PARKED |
PINMUX_INPUT_ENABLE | PINMUX_LPDR | PINMUX_IO_HV),
void bootblock_mainboard_early_init(void)
{
soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
}
static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
}
/********************* PADs ***********************************/
static const struct pad_config padcfgs[] = {
/* Board build id bits 1:0 */
PAD_CFG_GPIO_INPUT(GPIO_PK1, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(GPIO_PK0, PINMUX_PULL_NONE),
};
void bootblock_mainboard_init(void)
{
set_clock_sources();
/* Set up the pads required to load romstage. */
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
soc_configure_funits(funits, ARRAY_SIZE(funits));
/* PMIC */
i2c_init(I2CPWR_BUS);
pmic_init(I2CPWR_BUS);
