int board_early_init_f(void) { #ifdef CONFIG_FSL_SERDES immap_t *immr = (immap_t *)CFG_IMMR; u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ switch (PARTID_NO_E(spridr)) { case SPR_8377: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; default: printf("serdes not configured: unknown CPU part number: " "%04x\n", spridr >> 16); break; } #endif /* CONFIG_FSL_SERDES */ return 0; }
int board_early_init_f(void) { u8 *bcsr = (u8 *)CFG_BCSR; /* Enable flash write */ bcsr[0x9] &= ~0x04; /* Clear all of the interrupt of BCSR */ bcsr[0xe] = 0xff; #ifdef CONFIG_FSL_SERDES immap_t *immr = (immap_t *)CFG_IMMR; u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ switch (PARTID_NO_E(spridr)) { case SPR_8377: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; default: printf("serdes not configured: unknown CPU part number: " "%04x\n", spridr >> 16); break; } #endif /* CONFIG_FSL_SERDES */ return 0; }