/*
* Description: Read a byte from EEPROM, by MAC I2C
*
* Parameters:
* In:
* dwIoBase - I/O base address
* byContntOffset - address of EEPROM
* Out:
* none
*
* Return Value: data read
*
*/
BYTE SROMbyReadEmbedded(DWORD_PTR dwIoBase, BYTE byContntOffset)
{
WORD wDelay, wNoACK;
BYTE byWait;
BYTE byData;
BYTE byOrg;
byData = 0xFF;
VNSvInPortB(dwIoBase + MAC_REG_I2MCFG, &byOrg);
// turn off hardware retry for getting NACK
VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, (byOrg & (~I2MCFG_NORETRY)));
for (wNoACK = 0; wNoACK < W_MAX_I2CRETRY; wNoACK++) {
VNSvOutPortB(dwIoBase + MAC_REG_I2MTGID, EEP_I2C_DEV_ID);
VNSvOutPortB(dwIoBase + MAC_REG_I2MTGAD, byContntOffset);
// issue read command
VNSvOutPortB(dwIoBase + MAC_REG_I2MCSR, I2MCSR_EEMR);
// wait DONE be set
for (wDelay = 0; wDelay < W_MAX_TIMEOUT; wDelay++) {
VNSvInPortB(dwIoBase + MAC_REG_I2MCSR, &byWait);
if (byWait & (I2MCSR_DONE | I2MCSR_NACK))
break;
PCAvDelayByIO(CB_DELAY_LOOP_WAIT);
}
if ((wDelay < W_MAX_TIMEOUT) &&
( !(byWait & I2MCSR_NACK))) {
break;
}
}
VNSvInPortB(dwIoBase + MAC_REG_I2MDIPT, &byData);
VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, byOrg);
return byData;
}
/*
* Description: Read a byte from EEPROM, by MAC I2C
*
* Parameters:
* In:
* dwIoBase - I/O base address
* byContntOffset - address of EEPROM
* Out:
* none
*
* Return Value: data read
*
*/
unsigned char SROMbyReadEmbedded(unsigned long dwIoBase, unsigned char byContntOffset)
{
unsigned short wDelay, wNoACK;
unsigned char byWait;
unsigned char byData;
unsigned char byOrg;
byData = 0xFF;
VNSvInPortB(dwIoBase + MAC_REG_I2MCFG, &byOrg);
/* turn off hardware retry for getting NACK */
VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, (byOrg & (~I2MCFG_NORETRY)));
for (wNoACK = 0; wNoACK < W_MAX_I2CRETRY; wNoACK++) {
VNSvOutPortB(dwIoBase + MAC_REG_I2MTGID, EEP_I2C_DEV_ID);
VNSvOutPortB(dwIoBase + MAC_REG_I2MTGAD, byContntOffset);
/* issue read command */
VNSvOutPortB(dwIoBase + MAC_REG_I2MCSR, I2MCSR_EEMR);
/* wait DONE be set */
for (wDelay = 0; wDelay < W_MAX_TIMEOUT; wDelay++) {
VNSvInPortB(dwIoBase + MAC_REG_I2MCSR, &byWait);
if (byWait & (I2MCSR_DONE | I2MCSR_NACK))
break;
PCAvDelayByIO(CB_DELAY_LOOP_WAIT);
}
if ((wDelay < W_MAX_TIMEOUT) &&
( !(byWait & I2MCSR_NACK))) {
break;
}
}
VNSvInPortB(dwIoBase + MAC_REG_I2MDIPT, &byData);
VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, byOrg);
return byData;
}
/*--------------------- Export Functions --------------------------*/
BOOL
ADPbBind(
PSAdapterInfo pAdapter
)
{
/* build RDR/TDR */
if (!ALCbAllocateRdrMemory(pAdapter)) {
printf("allocate Buffer or RD fail!\n");
return FALSE;
}
if (!ALCbAllocateTdrMemory(pAdapter)) {
printf("allocate Buffer or TD fail!\n");
return FALSE;
}
ALCvChainRdrMemory(pAdapter);
ALCvChainTdrMemory(pAdapter);
/* Mac init & mii init */
if (!ADPbInitializeEx(pAdapter)) {
printf("init ex fail\n");
return FALSE;
}
/* Hook Interrupt Service Routine on IRQ */
/* set_irq_handlers(pAdapter->byIrqLevel, pAdapter->pvAdapterIsr); */
/* Enable Interrupt Mask */
/* unmask_interrupt(pAdapter->byIrqLevel); */
/* MacDump(MACDBG_INFO, ("[ADPbBind] - Hook ISR on IRQ%d\n", pAdapter->byIrqLevel)); */
/* Start ISR */
MACvIntEnable(pAdapter->dwIoBase, pAdapter->byRevId, IMR_MASK_VALUE);
/* Wait MAUTO to poll twice, then MIISR_LNKFL will be correct status */
/* kevin???? */
PCAvDelayByIO(CB_DELAY_MII_STABLE * 20000);
/* Update link status */
pAdapter->bLinkPass = MACbIsCableLinkOk(pAdapter->dwIoBase);
if (pAdapter->bLinkPass) {
MacDump(MACDBG_INFO, ("[ADPbBind]- Link Pass\n"));
/* update duplex status */
/* NOTE.... here we don't call MIIbIsInFullDuplexMode(), because */
/* we won't turn on/off MAUTO */
MACvIsInFullDuplexMode(&pAdapter->bFullDuplex, pAdapter->dwIoBase);
/* Update speed status */
pAdapter->bSpeed100M = MACbIsIn100MMode(pAdapter->dwIoBase, pAdapter->byRevId);
} else
MacDump(MACDBG_INFO, ("[ADPbBind]- Fail\n"));
pAdapter->pbyTmpBuff = (PBYTE)mALLOc(CB_MAX_BUF_SIZE);
MacDump(MACDBG_INFO, ("[ADPbBind]- Exit!\n"));
return TRUE;
}
BOOL GMACbIsIn1GMode(DWORD dwIoBase, BYTE byRevId)
{
UINT ii;
for (ii = 0; ii < 30; ii++)
PCAvDelayByIO(CB_DELAY_LOOP_WAIT);
/* NOTE.... */
/* when link fail, MAC will report in 1G mode, */
return GMACbIsRegBitsOn(dwIoBase, MAC_REG_PHYSR0, PHYSR0_SPDG);
}
BOOL GMACbSafeTxOff(DWORD dwIoBase, BYTE byRevId)
{
WORD ww;
/* clear RUN Tx */
VNSvOutPortW(dwIoBase + MAC_REG_TDCSR_CLR, 0x1111);
/* try to safe shutdown TX */
MACvTxOff(dwIoBase);
/* safe delay time */
PCAvDelayByIO(CB_DELAY_SOFT_RESET);
/* W_MAX_TIMEOUT is the timeout period */
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_CR0_SET, (BYTE)CR0_TXON))
break;
}
if (ww == W_MAX_TIMEOUT)
return FALSE;
return TRUE;
}
BOOL GMACbSafeRxOff(DWORD dwIoBase, BYTE byRevId)
{
WORD ww;
/* clear RUN Rx */
VNSvOutPortB(dwIoBase + MAC_REG_RDCSR_CLR, TRDCSR_RUN);
MACvRxOff(dwIoBase);
/* safe delay time */
PCAvDelayByIO(CB_DELAY_SOFT_RESET);
/* W_MAX_TIMEOUT is the timeout period */
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_CR0_SET, (BYTE)CR0_RXON))
break;
}
if (ww == W_MAX_TIMEOUT)
return FALSE;
return TRUE;
}
BOOL SROMbWriteEmbedded(DWORD_PTR dwIoBase, BYTE byContntOffset, BYTE byData)
{
WORD wDelay, wNoACK;
BYTE byWait;
BYTE byOrg;
VNSvInPortB(dwIoBase + MAC_REG_I2MCFG, &byOrg);
/* turn off hardware retry for getting NACK */
VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, (byOrg & (~I2MCFG_NORETRY)));
for (wNoACK = 0; wNoACK < W_MAX_I2CRETRY; wNoACK++) {
VNSvOutPortB(dwIoBase + MAC_REG_I2MTGID, EEP_I2C_DEV_ID);
VNSvOutPortB(dwIoBase + MAC_REG_I2MTGAD, byContntOffset);
VNSvOutPortB(dwIoBase + MAC_REG_I2MDOPT, byData);
/* issue write command */
VNSvOutPortB(dwIoBase + MAC_REG_I2MCSR, I2MCSR_EEMW);
/* wait DONE be set */
for (wDelay = 0; wDelay < W_MAX_TIMEOUT; wDelay++) {
VNSvInPortB(dwIoBase + MAC_REG_I2MCSR, &byWait);
if (byWait & (I2MCSR_DONE | I2MCSR_NACK))
break;
PCAvDelayByIO(CB_DELAY_LOOP_WAIT);
}
if ((wDelay < W_MAX_TIMEOUT) &&
( !(byWait & I2MCSR_NACK))) {
break;
}
}
if (wNoACK == W_MAX_I2CRETRY) {
VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, byOrg);
return FALSE;
}
VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, byOrg);
return TRUE;
}
VOID GMACvInitialize(PSAdapterInfo pAdapter, DWORD dwIoBase, BYTE byRevId)
{
BYTE byTemp;
BYTE check;
/* clear sticky bits */
MACvClearStckDS(dwIoBase);
/* disable force PME-enable */
VNSvOutPortB(dwIoBase + MAC_REG_WOLCFG_CLR, WOLCFG_PMEOVR);
/* disable power-event config bit */
MACvPwrEvntDisable(dwIoBase);
/* clear power status */
VNSvOutPortW(dwIoBase + MAC_REG_WOLSR0_CLR, 0xFFFF);
/* do reset */
GMACbSoftwareReset(dwIoBase, byRevId);
/* for AUTOLD be effect, safe delay time */
PCAvDelayByIO(CB_DELAY_SOFT_RESET);
VNSvInPortB(dwIoBase + MAC_REG_JMPSR1, &check);
/* VNSvInPortB(pAdapter->dwIoBase+Gmac_Jumper_Strapping3, &check) */
/* if (!(check & JMPSR1_J_VEESEL))
GMACLoadVEE(dwIoBase);
else { */
if (check & JMPSR1_J_VEESEL) {
/* issue RELOAD in EECSR to reload eeprom */
MACvRegBitsOn(dwIoBase, MAC_REG_EECSR, EECSR_RELOAD);
/* wait until EEPROM loading complete */
while (TRUE) {
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_EECSR, EECSR_RELOAD))
break;
}
}
/* EEPROM reloaded will cause bit 0 in MAC_REG_CFGA turned on. */
/* it makes MAC receive magic packet automatically. So, driver turn it off. */
MACvRegBitsOff(dwIoBase, MAC_REG_CFGA, CFGA_PACPI);
/* set rx-FIFO/DMA threshold */
/* set rx threshold, 128 bytes */
/*GMACvSetRxThreshold(dwIoBase, 3);*/
/* set DMA length, 16 DWORDs = 64 bytes */
/*GMACvSetDmaLength(dwIoBase, 1);*/
/* suspend-well accept broadcast, multicast */
VNSvOutPortB(dwIoBase + MAC_REG_WOLCFG_SET, WOLCFG_SAM | WOLCFG_SAB);
/* back off algorithm use original IEEE standard */
MACvRegBitsOff(dwIoBase, MAC_REG_CFGB, CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT);
/* set packet filter */
/* receive directed and broadcast address */
GMACvSetPacketFilter(dwIoBase, PKT_TYPE_DIRECTED | PKT_TYPE_BROADCAST);
/* Eric */
#if defined(__USE_GMASK1__)
VNSvOutPortD(dwIoBase + MAC_REG_IMR, IMR_MASK_VALUE);
#else
/* Turn on GenIntMask1 */
VNSvOutPortB(dwIoBase + MAC_REG_CR3_SET, CR3_GINTMSK1);
#endif
#if 0
VNSvInPortB(dwIoBase, &byTemp);
printf("address0 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 1, &byTemp);
printf("address1 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 2, &byTemp);
printf("address2 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 3, &byTemp);
printf("address3 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 4, &byTemp);
printf("address4 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 5, &byTemp);
printf("address6 = %x\n ", byTemp);
#endif
/* Adaptive Interrupt: Init is disabled */
/* Select page to interrupt hold timer */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp &= ~(CAMCR_PS0 | CAMCR_PS1);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* Set Interrupt hold timer = 0 */
VNSvOutPortB(dwIoBase + MAC_REG_ISR_HOTMR, 0x00);
/* Select Page to Tx-sup threshold */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp = (BYTE)((byTemp | CAMCR_PS0) & ~CAMCR_PS1);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* Set Tx interrupt suppression threshold = 0 */
VNSvOutPortB(dwIoBase + MAC_REG_ISR_TSUPTHR, 0x00);
/* Select Page to Rx-sup threshold */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp = (BYTE)((byTemp | CAMCR_PS1) & ~CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* Set Rx interrupt suppression threshold = 0 */
VNSvOutPortB(dwIoBase + MAC_REG_ISR_RSUPTHR, 0x00);
/* Select page to interrupt hold timer */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp &= ~(CAMCR_PS0 | CAMCR_PS1);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* enable MIICR_MAUTO */
GMACvEnableMiiAutoPoll(dwIoBase);
}
