/* * FIXME: This is only here to "make it work". This will move * to a ibm_pcix.c which will contain a generic IBM PCIX bridge * configuration library. -Matt */ static void __init ebony_setup_pcix(void) { void *pcix_reg_base; pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); /* Disable all windows */ PCIX_WRITEL(0, PCIX0_POM0SA); PCIX_WRITEL(0, PCIX0_POM1SA); PCIX_WRITEL(0, PCIX0_POM2SA); PCIX_WRITEL(0, PCIX0_PIM0SA); PCIX_WRITEL(0, PCIX0_PIM1SA); PCIX_WRITEL(0, PCIX0_PIM2SA); /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */ PCIX_WRITEL(0x00000003, PCIX0_POM0LAH); PCIX_WRITEL(0x80000000, PCIX0_POM0LAL); PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL); PCIX_WRITEL(0x80000001, PCIX0_POM0SA); /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); PCIX_WRITEL(0x80000007, PCIX0_PIM0SA); eieio(); }
static void __init ppc440spe_setup_pcix(struct pci_controller *hose) { void *pcix_reg_base; pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); /* Disable all windows */ PCIX_WRITEL(0, PCIX0_POM0SA); PCIX_WRITEL(0, PCIX0_POM1SA); PCIX_WRITEL(0, PCIX0_POM2SA); PCIX_WRITEL(0, PCIX0_PIM0SA); PCIX_WRITEL(0, PCIX0_PIM0SAH); PCIX_WRITEL(0, PCIX0_PIM1SA); PCIX_WRITEL(0, PCIX0_PIM2SA); PCIX_WRITEL(0, PCIX0_PIM2SAH); /* * Setup 512MB PLB->PCI outbound mem window * (a_n000_0000->0_n000_0000) * */ PCIX_WRITEL(0x0000000d, PCIX0_POM0LAH); PCIX_WRITEL(hose->mem_space.start, PCIX0_POM0LAL); PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); PCIX_WRITEL(hose->mem_space.start, PCIX0_POM0PCIAL); PCIX_WRITEL(~(hose->mem_space.end - hose->mem_space.start) | 1 , PCIX0_POM0SA); /* Setup 1GB PCI->PLB inbound memory window at 0, enable MSIs */ PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); PCIX_WRITEL(0xc0000007, PCIX0_PIM0SA); PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH); /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); iounmap(pcix_reg_base); eieio(); }
/* * FIXME: This is only here to "make it work". This will move * to a ibm_pcix.c which will contain a generic IBM PCIX bridge * configuration library. -Matt */ static void __init ocotea_setup_pcix(void) { void *pcix_reg_base; pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); /* Disable all windows */ PCIX_WRITEL(0, PCIX0_POM0SA); PCIX_WRITEL(0, PCIX0_POM1SA); PCIX_WRITEL(0, PCIX0_POM2SA); PCIX_WRITEL(0, PCIX0_PIM0SA); PCIX_WRITEL(0, PCIX0_PIM0SAH); PCIX_WRITEL(0, PCIX0_PIM1SA); PCIX_WRITEL(0, PCIX0_PIM2SA); PCIX_WRITEL(0, PCIX0_PIM2SAH); /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */ PCIX_WRITEL(0x00000003, PCIX0_POM0LAH); PCIX_WRITEL(0x80000000, PCIX0_POM0LAL); PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL); PCIX_WRITEL(0x80000001, PCIX0_POM0SA); /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA); eieio(); }
static void __init luan_setup_pcix(void) { int i; void *pcix_reg_base; for (i=0;i<3;i++) { pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE); /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); /* Disable all windows */ PCIX_WRITEL(0, PCIX0_POM0SA); PCIX_WRITEL(0, PCIX0_POM1SA); PCIX_WRITEL(0, PCIX0_POM2SA); PCIX_WRITEL(0, PCIX0_PIM0SA); PCIX_WRITEL(0, PCIX0_PIM0SAH); PCIX_WRITEL(0, PCIX0_PIM1SA); PCIX_WRITEL(0, PCIX0_PIM2SA); PCIX_WRITEL(0, PCIX0_PIM2SAH); /* * Setup 512MB PLB->PCI outbound mem window * (a_n000_0000->0_n000_0000) * */ PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH); PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL); PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL); PCIX_WRITEL(0xe0000001, PCIX0_POM0SA); /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA); PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH); iounmap(pcix_reg_base); } eieio(); }