pcireg_t
pci_conf_read( pci_chipset_tag_t pc, pcitag_t tag,
int reg)
{
pcireg_t data;
int s;
KASSERT((reg & 0x3) == 0);
#if defined(__i386__) && defined(XBOX)
if (arch_i386_is_xbox) {
int bus, dev, fn;
pci_decompose_tag(pc, tag, &bus, &dev, &fn);
if (bus == 0 && dev == 0 && (fn == 1 || fn == 2))
return (pcireg_t)-1;
}
#endif
#ifndef PCI_CONF_MODE
switch (pci_mode) {
case 1:
goto mode1;
case 2:
goto mode2;
default:
panic("pci_conf_read: mode not configured");
}
#endif
#if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1)
#ifndef PCI_CONF_MODE
mode1:
#endif
PCI_CONF_LOCK(s);
outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
data = inl(PCI_MODE1_DATA_REG);
outl(PCI_MODE1_ADDRESS_REG, 0);
PCI_CONF_UNLOCK(s);
return data;
#endif
#if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2)
#ifndef PCI_CONF_MODE
mode2:
#endif
PCI_CONF_LOCK(s);
outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
data = inl(tag.mode2.port | reg);
outb(PCI_MODE2_ENABLE_REG, 0);
PCI_CONF_UNLOCK(s);
return data;
#endif
}
pcireg_t
i80321_pci_conf_read(void *v, pcitag_t tag, int offset)
{
struct i80321_softc *sc = v;
struct pciconf_state ps;
vaddr_t va;
uint32_t isr;
pcireg_t rv;
u_int s;
if (i80321_pci_conf_setup(sc, tag, offset, &ps))
return ((pcireg_t) -1);
PCI_CONF_LOCK(s);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
ps.ps_addr_val);
va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh);
if (badaddr_read((void *) (va + ATU_OCCDR), sizeof(rv), &rv)) {
isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR,
isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM|
ATUISR_PTAT|ATUISR_PMPE));
#if 0
printf("conf_read: %d/%d/%d bad address\n",
ps.ps_b, ps.ps_d, ps.ps_f);
#endif
rv = (pcireg_t) -1;
}
PCI_CONF_UNLOCK(s);
return (rv);
}
pcireg_t
pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
{
pcireg_t data;
int bus;
KASSERT((reg & 0x3) == 0);
if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) {
pci_decompose_tag(pc, tag, &bus, NULL, NULL);
if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) {
pci_mcfg_map_bus(bus);
data = bus_space_read_4(pci_mcfgt, pci_mcfgh[bus],
(tag & 0x000ff00) << 4 | reg);
return data;
}
}
PCI_CONF_LOCK();
outl(PCI_MODE1_ADDRESS_REG, tag | reg);
data = inl(PCI_MODE1_DATA_REG);
outl(PCI_MODE1_ADDRESS_REG, 0);
PCI_CONF_UNLOCK();
return data;
}
static void
gt_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data)
{
int bus, dev, func, s;
gt_decompose_tag(NULL /* XXX */, tag, &bus, &dev, &func);
/* The galileo has problems accessing device 31. */
if (bus == 0 && dev == 31)
return;
/* XXX: no support for bus > 0 yet */
if (bus > 0)
return;
PCI_CONF_LOCK(s);
/* Clear cause register bits. */
GT_REGVAL(GT_INTR_CAUSE) = 0;
GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset;
GT_REGVAL(GT_PCI0_CFG_DATA) = data;
PCI_CONF_UNLOCK(s);
}
static pcireg_t
gt_conf_read(void *v, pcitag_t tag, int offset)
{
pcireg_t data;
int bus, dev, func, s;
gt_decompose_tag(NULL /* XXX */, tag, &bus, &dev, &func);
/* The galileo has problems accessing device 31. */
if (bus == 0 && dev == 31)
return ((pcireg_t) -1);
/* XXX: no support for bus > 0 yet */
if (bus > 0)
return ((pcireg_t) -1);
PCI_CONF_LOCK(s);
/* Clear cause register bits. */
GT_REGVAL(GT_INTR_CAUSE) = 0;
GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset;
data = GT_REGVAL(GT_PCI0_CFG_DATA);
/* Check for master abort. */
if (GT_REGVAL(GT_INTR_CAUSE) & (GTIC_MASABORT0 | GTIC_TARABORT0))
data = (pcireg_t) -1;
PCI_CONF_UNLOCK(s);
return (data);
}
void
empb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)
{
uint32_t bus, dev, func;
struct empb_softc *sc;
int s;
sc = pc->cookie;
pci_decompose_tag(pc, tag, &bus, &dev, &func);
PCI_CONF_LOCK(s);
empb_switch_bridge(sc, BRIDGE_CONF);
bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah,
EMPB_CONF_DEV_STRIDE*dev + EMPB_CONF_FUNC_STRIDE*func + reg, val);
#ifdef EMPB_DEBUG_CONF
aprint_normal("empb conf write va: %lx, bus: %d, dev: %d, "
"func: %d, reg: %d -w-> data %x\n",
pc->pci_conf_datah, bus, dev, func, reg, val);
#endif /* EMPB_DEBUG_CONF */
empb_switch_bridge(sc, BRIDGE_IO);
PCI_CONF_UNLOCK(s);
}
pcireg_t
pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
{
pcireg_t data;
int s;
PCI_CONF_LOCK(s);
switch (pci_mode) {
case 1:
outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
data = inl(PCI_MODE1_DATA_REG);
outl(PCI_MODE1_ADDRESS_REG, 0);
break;
case 2:
outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
data = inl(tag.mode2.port | reg);
outb(PCI_MODE2_ENABLE_REG, 0);
break;
default:
panic("pci_conf_read: mode not configured");
}
PCI_CONF_UNLOCK(s);
return data;
}
void
pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
{
int bus;
if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) {
pci_decompose_tag(pc, tag, &bus, NULL, NULL);
if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) {
pci_mcfg_map_bus(bus);
bus_space_write_4(pci_mcfgt, pci_mcfgh[bus],
(tag.mode1 & 0x000ff00) << 4 | reg, data);
return;
}
}
PCI_CONF_LOCK();
switch (pci_mode) {
case 1:
outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
outl(PCI_MODE1_DATA_REG, data);
outl(PCI_MODE1_ADDRESS_REG, 0);
break;
case 2:
outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
outl(tag.mode2.port | reg, data);
outb(PCI_MODE2_ENABLE_REG, 0);
break;
default:
panic("pci_conf_write: mode not configured");
}
PCI_CONF_UNLOCK();
}
void
irongate_conf_write(void *ipv, pcitag_t tag, int offset, pcireg_t data)
{
int s;
PCI_CONF_LOCK(s);
REGVAL(PCI_CONF_ADDR) = (CONFADDR_ENABLE | tag | (offset & 0xff));
alpha_mb();
REGVAL(PCI_CONF_DATA) = data;
alpha_mb();
REGVAL(PCI_CONF_ADDR) = 0;
alpha_mb();
PCI_CONF_UNLOCK(s);
}
void
_pci_io_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off,
uint32_t val)
{
int s;
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_WRITE);
CSR_WRITE_4(PCI_NP_WDATA, val);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
}
uint32_t
_pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off)
{
uint32_t data;
int s;
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ);
data = CSR_READ_4(PCI_NP_RDATA);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
return data;
}
pcireg_t
irongate_conf_read0(void *ipv, pcitag_t tag, int offset)
{
pcireg_t data;
int s;
PCI_CONF_LOCK(s);
REGVAL(PCI_CONF_ADDR) = (CONFADDR_ENABLE | tag | (offset & 0xff));
alpha_mb();
data = REGVAL(PCI_CONF_DATA);
REGVAL(PCI_CONF_ADDR) = 0;
alpha_mb();
PCI_CONF_UNLOCK(s);
return (data);
}
void
i80321_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
{
struct i80321_softc *sc = v;
struct pciconf_state ps;
u_int s;
if (i80321_pci_conf_setup(sc, tag, offset, &ps))
return;
PCI_CONF_LOCK(s);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
ps.ps_addr_val);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, val);
PCI_CONF_UNLOCK(s);
}
uint16_t
_pci_io_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off)
{
uint32_t data, n, be;
int s;
n = (ioh + off) % 4;
be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
data = CSR_READ_4(PCI_NP_RDATA);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
return data >> (8 * n);
}
void
_pci_io_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off,
uint16_t val)
{
uint32_t data, n, be;
int s;
n = (ioh + off) % 4;
be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
data = val << (8 * n);
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE);
CSR_WRITE_4(PCI_NP_WDATA, data);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
}
pcireg_t
becc_pci_conf_read(void *v, pcitag_t tag, int offset)
{
struct becc_softc *sc = v;
struct pciconf_state ps;
vaddr_t va;
pcireg_t rv;
u_int s;
if (becc_pci_conf_setup(sc, tag, offset, &ps))
return ((pcireg_t) -1);
/*
* Skip device 0 (the BECC itself). We don't want it
* to appear as part of the PCI device space.
*/
if (ps.ps_b == 0 && ps.ps_d == 0)
return ((pcireg_t) -1);
PCI_CONF_LOCK(s);
va = sc->sc_pci_cfg_base + ps.ps_offset;
BECC_CSR_WRITE(BECC_POCR, ps.ps_type);
if (badaddr_read((void *) va, sizeof(rv), &rv)) {
/* XXX Check master/target abort? */
#if 0
printf("conf_read: %d/%d/%d bad address\n",
ps.ps_b, ps.ps_d, ps.ps_f);
#endif
rv = (pcireg_t) -1;
}
if (becc_pci_conf_cleanup(sc))
rv = (pcireg_t) -1;
PCI_CONF_UNLOCK(s);
return (rv);
}
void
becc_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
{
struct becc_softc *sc = v;
struct pciconf_state ps;
vaddr_t va;
u_int s;
if (becc_pci_conf_setup(sc, tag, offset, &ps))
return;
PCI_CONF_LOCK(s);
BECC_CSR_WRITE(BECC_POCR, ps.ps_type);
va = sc->sc_pci_cfg_base + ps.ps_offset;
*(volatile pcireg_t *)va = val;
becc_pci_conf_cleanup(sc);
PCI_CONF_UNLOCK(s);
}
pcireg_t
i80312_pci_conf_read(void *v, pcitag_t tag, int offset)
{
struct i80312_softc *sc = v;
struct pciconf_state ps;
vaddr_t va;
pcireg_t rv;
u_int s;
if (i80312_pci_conf_setup(sc, tag, offset, &ps))
return ((pcireg_t) -1);
PCI_CONF_LOCK(s);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg,
ps.ps_addr_val);
va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh);
if (badaddr_read((void *) (va + ps.ps_data_reg), sizeof(rv), &rv)) {
/*
* Clear the Master Abort by reading the PCI
* Status Register.
*/
(void) bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
ps.ps_csr_reg);
#if 0
printf("conf_read: %d/%d/%d bad address\n",
ps.ps_b, ps.ps_d, ps.ps_f);
#endif
rv = (pcireg_t) -1;
}
PCI_CONF_UNLOCK(s);
return (rv);
}
