void pci_mcf5445x_init(struct pci_controller *hose)
{
pci_t *pci = (pci_t *)MMAP_PCI;
pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u32 barEn = 0;
out_be32(&pciarb->acr, 0x001f001f);
/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
PCIREQ2, PCIGNT2 */
out_be16(&gpio->par_pci,
GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
/* Assert reset bit */
setbits_be32(&pci->gscr, PCI_GSCR_PR);
setbits_be32(&pci->tcr1, PCI_TCR1_P);
/* Initiator windows */
out_be32(&pci->iw0btar,
CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
out_be32(&pci->iw1btar,
CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
out_be32(&pci->iw2btar,
CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
out_be32(&pci->iwcr,
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
out_be32(&pci->icr, 0);
/* Enable bus master and mem access */
out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
/* Cache line size and master latency */
out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
out_be32(&pci->cr2, 0);
#ifdef CONFIG_SYS_PCI_BAR0
out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B0E;
#endif
#ifdef CONFIG_SYS_PCI_BAR1
out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B1E;
#endif
#ifdef CONFIG_SYS_PCI_BAR2
out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B2E;
#endif
#ifdef CONFIG_SYS_PCI_BAR3
out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B3E;
#endif
#ifdef CONFIG_SYS_PCI_BAR4
out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B4E;
#endif
#ifdef CONFIG_SYS_PCI_BAR5
out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B5E;
#endif
out_be32(&pci->tcr2, barEn);
/* Deassert reset bit */
clrbits_be32(&pci->gscr, PCI_GSCR_PR);
udelay(1000);
/* Enable PCI bus master support */
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
pci_write_cfg_dword);
/* Hose scan */
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
void pci_mcf547x_8x_init(struct pci_controller *hose)
{
volatile pci_t *pci = (volatile pci_t *) MMAP_PCI;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Port configuration */
gpio->par_pcibg =
GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
GPIO_PAR_PCIBG_PCIBG4(3);
gpio->par_pcibr =
GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
GPIO_PAR_PCIBR_PCIBR4(3);
/* Assert reset bit */
pci->gscr |= PCI_GSCR_PR;
pci->tcr1 = PCI_TCR1_P;
/* Initiator windows */
pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
pci->iwcr =
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
pci->icr = 0;
/* Enable bus master and mem access */
pci->scr = PCI_SCR_B | PCI_SCR_M;
/* Cache line size and master latency */
pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
pci->cr2 = 0;
#ifdef CFG_PCI_BAR0
pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
pci->tbatr0a = CFG_PCI_TBATR0 | PCI_TBATR_EN;
#endif
#ifdef CFG_PCI_BAR1
pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
pci->tbatr1a = CFG_PCI_TBATR1 | PCI_TBATR_EN;
#endif
/* Deassert reset bit */
pci->gscr &= ~PCI_GSCR_PR;
udelay(1000);
/* Enable PCI bus master support */
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
CFG_PCI_IO_SIZE, PCI_REGION_IO);
pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
pci_write_cfg_dword);
/* Hose scan */
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
void pci_mcf5445x_init(struct pci_controller *hose)
{
volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u32 barEn = 0;
pciarb->acr = 0x001F001F;
/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
PCIREQ2, PCIGNT2 */
gpio->par_pci =
GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
/* Assert reset bit */
pci->gscr |= PCI_GSCR_PR;
pci->tcr1 |= PCI_TCR1_P;
/* Initiator windows */
pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
pci->iwcr =
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
pci->icr = 0;
/* Enable bus master and mem access */
pci->scr = PCI_SCR_B | PCI_SCR_M;
/* Cache line size and master latency */
pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
pci->cr2 = 0;
#ifdef CFG_PCI_BAR0
pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B0E;
#endif
#ifdef CFG_PCI_BAR1
pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B1E;
#endif
#ifdef CFG_PCI_BAR2
pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2);
pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B2E;
#endif
#ifdef CFG_PCI_BAR3
pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3);
pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B3E;
#endif
#ifdef CFG_PCI_BAR4
pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4);
pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B4E;
#endif
#ifdef CFG_PCI_BAR5
pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5);
pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN;
barEn |= PCI_TCR2_B5E;
#endif
pci->tcr2 = barEn;
/* Deassert reset bit */
pci->gscr &= ~PCI_GSCR_PR;
udelay(1000);
/* Enable PCI bus master support */
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
CFG_PCI_IO_SIZE, PCI_REGION_IO);
pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
pci_write_cfg_dword);
/* Hose scan */
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}