/**
* Read IO port
*
*
* @param[in] AccessWidth Access width
* @param[in] IoAddress IO port address
* @param[in] Value Pointer to save data
* @param[in] StdHeader Standard configuration header
*
*/
VOID
LibAmdIoRead (
IN ACCESS_WIDTH AccessWidth,
IN UINT16 IoAddress,
OUT VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
EFI_PEI_SERVICES **PeiServices;
PEI_CPU_IO_PPI *CpuIo;
PeiServices = (EFI_PEI_SERVICES**) (StdHeader->AltImageBasePtr);
CpuIo = (*PeiServices)->CpuIo;
switch (AccessWidth) {
case AccessWidth8:
*(UINT8 *) Value = CpuIo->IoRead8 (PeiServices, CpuIo, IoAddress);
break;
case AccessWidth16:
*(UINT16 *) Value = CpuIo->IoRead16 (PeiServices, CpuIo, IoAddress);
break;
case AccessWidth32:
*(UINT32 *) Value = CpuIo->IoRead32 (PeiServices, CpuIo, IoAddress);
break;
default:
PEI_ASSERT (PeiServices, FALSE);
}
}
/**
* Write memory/MMIO
*
*
* @param[in] AccessWidth Access width
* @param[in] MemAddress Memory address
* @param[in] Value Pointer to data
* @param[in] StdHeader Standard configuration header
*
*/
VOID
LibAmdMemWrite (
IN ACCESS_WIDTH AccessWidth,
IN UINT64 MemAddress,
IN VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
EFI_PEI_SERVICES **PeiServices;
PEI_CPU_IO_PPI *CpuIo;
PeiServices = (EFI_PEI_SERVICES**) (StdHeader->AltImageBasePtr);
CpuIo = (*PeiServices)->CpuIo;
switch (AccessWidth) {
case AccessWidth8:
CpuIo->MemWrite8 (PeiServices, CpuIo, MemAddress, *(UINT8 *) Value);
break;
case AccessWidth16:
CpuIo->MemWrite16 (PeiServices, CpuIo, MemAddress, *(UINT16 *) Value);
break;
case AccessWidth32:
CpuIo->MemWrite32 (PeiServices, CpuIo, MemAddress, *(UINT32 *) Value);
break;
default:
PEI_ASSERT (PeiServices, FALSE);
}
}
/**
* PCI read modify write
*
*
* @param[in] AccessWidth Access width
* @param[in] PciAddress Pci address
* @param[in] Data SetBits, to bitwise-OR with read value
* @param[in] DataMask ClearBits, to negate and bitwise-AND with read value
* @param[in] StdHeader Standard configuration header
*
*/
VOID
LibAmdPciRMW (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR PciAddress,
IN VOID *Data,
IN VOID *DataMask,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
EFI_PEI_SERVICES **PeiServices;
#if (PI_SPECIFICATION_VERSION < 0x00010000)
PEI_PCI_CFG_PPI *PciCfg;
#else
EFI_PEI_PCI_CFG2_PPI *PciCfg;
#endif
PEI_PCI_CFG_PPI_WIDTH PciWidth;
PeiServices = (EFI_PEI_SERVICES**) (StdHeader->AltImageBasePtr);
PciCfg = (*PeiServices)->PciCfg;
switch (AccessWidth) {
case AccessWidth8:
PciWidth = PeiPciCfgWidthUint8;
break;
case AccessWidth16:
PciWidth = PeiPciCfgWidthUint16;
break;
case AccessWidth32:
PciWidth = PeiPciCfgWidthUint32;
break;
default:
PciWidth = PeiPciCfgWidthUint32;
PEI_ASSERT (PeiServices, FALSE);
}
#if (PI_SPECIFICATION_VERSION < 0x00010000)
PciCfg->Modify (
PeiServices,
PciCfg,
PciWidth,
ConvertPciAddress (PciAddress),
*(UINTN *) Data,
*(UINTN *) DataMask
);
#else
PciCfg->Modify (
PeiServices,
PciCfg,
PciWidth,
ConvertPciAddress (PciAddress),
Data,
DataMask
);
#endif
}
EFI_STATUS
PeiBuildHobFv (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
)
/*++
Routine Description:
Builds a Firmware Volume HOB
Arguments:
PeiServices - The PEI core services table.
BaseAddress - The base address of the Firmware Volume
Length - The size of the Firmware Volume in bytes
Returns:
EFI_SUCCESS - Hob is successfully built.
Others - Errors occur while creating new Hob
--*/
{
EFI_STATUS Status;
EFI_HOB_FIRMWARE_VOLUME *Hob;
//
// Check FV Signature
//
PEI_ASSERT (PeiServices, ((EFI_FIRMWARE_VOLUME_HEADER*)((UINTN)BaseAddress))->Signature == EFI_FVH_SIGNATURE);
Status = (*PeiServices)->CreateHob (
PeiServices,
EFI_HOB_TYPE_FV,
sizeof (EFI_HOB_FIRMWARE_VOLUME),
&Hob
);
if (EFI_ERROR (Status)) {
return Status;
}
Hob->BaseAddress = BaseAddress;
Hob->Length = Length;
return EFI_SUCCESS;
}
VOID
EFIAPI
BuildFvHob2 (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN EFI_GUID *FvNameGuid,
IN EFI_GUID *FileNameGuid
)
/*++
Routine Description:
Build FvHob2.
Arguments:
BaseAddress - Fv base address.
Length - Fv length.
FvNameGuid - Fv name.
FileNameGuid - File name which contians encapsulated Fv.
Returns:
NONE.
--*/
{
EFI_STATUS Status;
EFI_HOB_FIRMWARE_VOLUME2 *Hob;
EFI_PEI_SERVICES **PeiServices;
PeiServices = GetPeiServicesTablePointer();
//
// Check FV Signature
//
PEI_ASSERT (PeiServices, ((EFI_FIRMWARE_VOLUME_HEADER*)((UINTN)BaseAddress))->Signature == EFI_FVH_SIGNATURE);
Status = (*PeiServices)->CreateHob (
PeiServices,
EFI_HOB_TYPE_FV2,
sizeof (EFI_HOB_FIRMWARE_VOLUME2),
&Hob
);
Hob->BaseAddress = BaseAddress;
Hob->Length = Length;
CopyMem ((VOID*)&Hob->FvName, FvNameGuid, sizeof(EFI_GUID));
CopyMem ((VOID*)&Hob->FileName, FileNameGuid, sizeof(EFI_GUID));
}
VOID
EFIAPI
BuildFvHob (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
)
/*++
Routine Description:
Build FvHob.
Arguments:
BaseAddress - Fv base address.
Length - Fv Length.
Returns:
NONE.
--*/
{
EFI_STATUS Status;
EFI_HOB_FIRMWARE_VOLUME *Hob;
EFI_PEI_SERVICES **PeiServices;
PeiServices = GetPeiServicesTablePointer();
//
// Check FV Signature
//
PEI_ASSERT (PeiServices, ((EFI_FIRMWARE_VOLUME_HEADER*)((UINTN)BaseAddress))->Signature == EFI_FVH_SIGNATURE);
Status = (*PeiServices)->CreateHob (
PeiServices,
EFI_HOB_TYPE_FV,
sizeof (EFI_HOB_FIRMWARE_VOLUME),
&Hob
);
Hob->BaseAddress = BaseAddress;
Hob->Length = Length;
}
EFI_STATUS
EFIAPI
GetDimmState (
IN EFI_PEI_SERVICES **PeiServices,
IN PEI_PLATFORM_DIMM_PPI *This,
IN UINT8 Dimm,
OUT PEI_PLATFORM_DIMM_STATE *State
)
{
EFI_STATUS Status;
UINT8 Buffer;
PEI_ASSERT (PeiServices, (Dimm < This->DimmSockets));
//
// A failure here does not necessarily mean that no DIMM is present.
// Read a single byte. All we care about is the return status.
//
Status = ReadSpd (
PeiServices,
This,
Dimm,
0,
1,
&Buffer
);
if (EFI_ERROR (Status)) {
State->Present = 0;
} else {
State->Present = 1;
}
//
// BUGBUG: Update to check platform variable when it is available
//
State->Disabled = 0;
State->Reserved = 0;
return EFI_SUCCESS;
}
EFIAPI
InvalidateInstructionCacheRange (
IN VOID *Address,
IN UINTN Length
)
/*++
Routine Description:
Invalidates a range of instruction cache lines in the cache coherency domain
of the calling CPU.
Invalidates the instruction cache lines specified by Address and Length. If
Address is not aligned on a cache line boundary, then entire instruction
cache line containing Address is invalidated. If Address + Length is not
aligned on a cache line boundary, then the entire instruction cache line
containing Address + Length -1 is invalidated. This function may choose to
invalidate the entire instruction cache if that is more efficient than
invalidating the specified range. If Length is 0, the no instruction cache
lines are invalidated. Address is returned.
If Length is greater than (EFI_MAX_ADDRESS - Address + 1), then ASSERT().
Arguments:
Address - The base address of the instruction cache lines to
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
Length - The number of bytes to invalidate from the instruction cache.
Returns:
Address
**/
{
PEI_ASSERT(GetPeiServicesTablePointer() , (Length <= EFI_MAX_ADDRESS - (UINTN)Address + 1));
return Address;
}
