/* ===================================================================*/
LDD_TDeviceData* BitIoLdd8_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
BitIoLdd8_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Configure pin as output */
/* GPIOB_PDDR: PDD|=4 */
GPIOB_PDDR |= GPIO_PDDR_PDD(0x04);
/* Set initialization value */
/* GPIOB_PDOR: PDO&=~4 */
GPIOB_PDOR &= (uint32_t)~(uint32_t)(GPIO_PDOR_PDO(0x04));
/* Initialization of Port Control register */
/* PORTB_PCR2: ISF=0,MUX=1 */
PORTB_PCR2 = (uint32_t)((PORTB_PCR2 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x06)
)) | (uint32_t)(
PORT_PCR_MUX(0x01)
));
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_BitIoLdd8_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* BitIoLdd8_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
BitIoLdd8_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Enable device clock gate */
/* SIM_SCGC5: PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* Configure pin as output */
/* GPIOA_PDDR: PDD|=2 */
GPIOA_PDDR |= GPIO_PDDR_PDD(0x02);
/* Set initialization value */
/* GPIOA_PDOR: PDO&=~2 */
GPIOA_PDOR &= (uint32_t)~(uint32_t)(GPIO_PDOR_PDO(0x02));
/* Initialization of pin routing */
/* PORTA_PCR1: ISF=0,MUX=1 */
PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x06)
)) | (uint32_t)(
PORT_PCR_MUX(0x01)
));
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_BitIoLdd8_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* AS2_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
AS2_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Allocate interrupt vectors */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_UART1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* SIM_SCGC4: UART1=1 */
SIM_SCGC4 |= SIM_SCGC4_UART1_MASK;
/* PORTE_PCR1: ISF=0,MUX=3 */
PORTE_PCR1 = (uint32_t)((PORTE_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
/* PORTE_PCR0: ISF=0,MUX=3 */
PORTE_PCR0 = (uint32_t)((PORTE_PCR0 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
/* NVIC_IPR3: PRI_13=0x80 */
NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_13(0x7F)
)) | (uint32_t)(
NVIC_IP_PRI_13(0x80)
));
/* NVIC_ISER: SETENA|=0x2000 */
NVIC_ISER |= NVIC_ISER_SETENA(0x2000);
UART_PDD_EnableTransmitter(UART1_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
UART_PDD_EnableReceiver(UART1_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
/* UART1_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=1,WAKE=0,ILT=0,PE=1,PT=1 */
UART1_C1 = (UART_C1_M_MASK | UART_C1_PE_MASK | UART_C1_PT_MASK); /* Set the C1 register */
/* UART1_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART1_C3 = 0x00U; /* Set the C3 register */
/* UART1_S2: LBKDIF=0,RXEDGIF=0,??=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART1_S2 = 0x00U; /* Set the S2 register */
UART_PDD_SetBaudRate(UART1_BASE_PTR, 8191U); /* Set the baud rate register. */
UART_PDD_EnableTransmitter(UART1_BASE_PTR, PDD_ENABLE); /* Enable transmitter */
UART_PDD_EnableReceiver(UART1_BASE_PTR, PDD_ENABLE); /* Enable receiver */
UART_PDD_EnableInterrupt(UART1_BASE_PTR, ( UART_PDD_INTERRUPT_RECEIVER )); /* Enable interrupts */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_AS2_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* SystemTimer1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
SystemTimer1_TDeviceData *DeviceDataPrv;
/* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Interrupt vector(s) allocation */
/* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */
/* Note: Exception handler for interrupt is not saved, because it is not modified */
DeviceDataPrv->SavedISRSettings_TUInterrupt.isrData = _int_get_isr_data(LDD_ivIndex_INT_SysTick);
DeviceDataPrv->SavedISRSettings_TUInterrupt.isrFunction = _int_install_isr(LDD_ivIndex_INT_SysTick, SystemTimer1_Interrupt, DeviceDataPrv);
/* SYST_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNTFLAG=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CLKSOURCE=0,TICKINT=0,ENABLE=0 */
SYST_CSR = 0x00U; /* Clear control register */
/* SYST_RVR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RELOAD=0x00B71AFF */
SYST_RVR = SysTick_RVR_RELOAD(0x00B71AFF); /* Setup reload value */
/* SYST_CVR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CURRENT=0 */
SYST_CVR = SysTick_CVR_CURRENT(0x00); /* Clear current value */
/* SCB_SHPR3: PRI_15&=~0x80,PRI_15|=0x70 */
SCB_SHPR3 = (uint32_t)((SCB_SHPR3 & (uint32_t)~(uint32_t)(
SCB_SHPR3_PRI_15(0x80)
)) | (uint32_t)(
SCB_SHPR3_PRI_15(0x70)
));
/* SYST_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNTFLAG=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CLKSOURCE=1,TICKINT=1,ENABLE=0 */
SYST_CSR = (SysTick_CSR_CLKSOURCE_MASK | SysTick_CSR_TICKINT_MASK); /* Set up control register */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SystemTimer1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* ===================================================================*/
LDD_TDeviceData* UART_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
UART_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Allocate interrupt vectors */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_UART0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* SIM_SCGC4: UART0=1 */
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
/* PORTA_PCR1: ISF=0,MUX=2 */
PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTA_PCR2: ISF=0,MUX=2 */
PORTA_PCR2 = (uint32_t)((PORTA_PCR2 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* NVIC_IPR3: PRI_12=0x80 */
NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_12(0x7F)
)) | (uint32_t)(
NVIC_IP_PRI_12(0x80)
));
/* NVIC_ISER: SETENA|=0x1000 */
NVIC_ISER |= NVIC_ISER_SETENA(0x1000);
UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
/* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
UART0_C1 = 0x00U; /* Set the C1 register */
/* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART0_C3 = 0x00U; /* Set the C3 register */
/* UART0_C4: MAEN1=0,MAEN2=0,M10=0,OSR=0 */
UART0_C4 = UART0_C4_OSR(0x00); /* Set the C4 register */
/* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART0_S2 = 0x00U; /* Set the S2 register */
UART_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Initial speed CPU mode is high */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_UART_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* CI2C1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate HAL device structure */
CI2C1_TDeviceData *DeviceDataPrv;
/* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
/* Allocate interrupt vector */
/* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */
/* Note: Exception handler for interrupt is not saved, because it is not modified */
DeviceDataPrv->SavedISRSettings.isrData = _int_get_isr_data(LDD_ivIndex_INT_I2C0);
DeviceDataPrv->SavedISRSettings.isrFunction = _int_install_isr(LDD_ivIndex_INT_I2C0, CI2C1_Interrupt, DeviceDataPrv);
DeviceDataPrv->SerFlag = 0x00U; /* Reset all flags */
DeviceDataPrv->SendStop = LDD_I2C_SEND_STOP; /* Set variable for sending stop condition (for master mode) */
DeviceDataPrv->InpLenM = 0x00U; /* Set zero counter of data of reception */
DeviceDataPrv->OutLenM = 0x00U; /* Set zero counter of data of transmission */
/* SIM_SCGC4: I2C0=1 */
SIM_SCGC4 |= SIM_SCGC4_I2C0_MASK;
/* I2C0_C1: IICEN=0,IICIE=0,MST=0,TX=0,TXAK=0,RSTA=0,WUEN=0,DMAEN=0 */
I2C0_C1 = 0x00U; /* Clear control register */
/* I2C0_S: TCF=0,IAAS=0,BUSY=0,ARBL=0,RAM=0,SRW=0,IICIF=1,RXAK=0 */
I2C0_S = I2C_S_IICIF_MASK; /* Clear interrupt flag */
/* PORTB_PCR1: ISF=0,MUX=2 */
PORTB_PCR1 = (uint32_t)((PORTB_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
PORT_PDD_SetPinOpenDrain(PORTB_BASE_PTR, 0x01u, PORT_PDD_OPEN_DRAIN_ENABLE); /* Set SDA pin as open drain */
/* PORTB_PCR0: ISF=0,MUX=2 */
PORTB_PCR0 = (uint32_t)((PORTB_PCR0 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
PORT_PDD_SetPinOpenDrain(PORTB_BASE_PTR, 0x00u, PORT_PDD_OPEN_DRAIN_ENABLE); /* Set SCL pin as open drain */
/* NVICIP24: PRI24=0x80 */
NVICIP24 = NVIC_IP_PRI24(0x80);
/* NVICISER0: SETENA|=0x01000000 */
NVICISER0 |= NVIC_ISER_SETENA(0x01000000);
/* I2C0_C2: GCAEN=0,ADEXT=0,HDRS=0,SBRC=0,RMEN=0,AD=0 */
I2C0_C2 = I2C_C2_AD(0x00);
/* I2C0_FLT: ??=0,??=0,??=0,FLT=0 */
I2C0_FLT = I2C_FLT_FLT(0x00); /* Set glitch filter register */
/* I2C0_SMB: FACK=0,ALERTEN=0,SIICAEN=0,TCKSEL=0,SLTF=1,SHTF1=0,SHTF2=0,SHTF2IE=0 */
I2C0_SMB = I2C_SMB_SLTF_MASK;
/* I2C0_F: MULT=1,ICR=0x17 */
I2C0_F = (I2C_F_MULT(0x01) | I2C_F_ICR(0x17)); /* Set prescaler bits */
I2C_PDD_EnableDevice(I2C0_BASE_PTR, PDD_ENABLE); /* Enable device */
I2C_PDD_EnableInterrupt(I2C0_BASE_PTR); /* Enable interrupt */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_CI2C1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
/* ===================================================================*/
LDD_TDeviceData* DMAT_S_SPI_RX_Init(LDD_TUserData *UserDataPtr)
{
DMAT_S_SPI_RX_TDeviceData *DeviceDataPtr; /* LDD device structure */
LDD_DMA_TTransferDescriptor *DescriptorPtr; /* Transfer descriptor structure */
/* Allocate LDD device structure */
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPtr = &DeviceDataPtr__DEFAULT_RTOS_ALLOC;
/* Allocate Transfer descriptor structure */
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DescriptorPtr = &DescriptorPtr__DEFAULT_RTOS_ALLOC;
DeviceDataPtr->DescriptorPtr = DescriptorPtr; /* Store pointer to the descriptor structure */
/* Transfer descriptor initialization */
DeviceDataPtr->DescriptorPtr->UserDataPtr = UserDataPtr; /* User device data structure pointer to be returned by the DMA_LDD component's ISR to the dynamic callback of this Descriptor */
/* Source settings */
DeviceDataPtr->DescriptorPtr->SourceAddress = (LDD_DMA_TAddress)(&SPI1_D); /* Address of a DMA transfer source data */
DeviceDataPtr->DescriptorPtr->SourceTransferSize = (LDD_DMA_TTransferSize)DMA_PDD_8_BIT; /* 8-bit source data transfer size. */
DeviceDataPtr->DescriptorPtr->SourceModuloSize = (LDD_DMA_TModuloSize)DMA_PDD_CIRCULAR_BUFFER_DISABLED; /* Circular buffer size. */
DeviceDataPtr->DescriptorPtr->SourceAddressIncrement = FALSE; /* Address not incremented. */
/* Destination settings */
DeviceDataPtr->DescriptorPtr->DestinationAddress = (LDD_DMA_TAddress)SPI1RxDMADataDestinationBuffer; /* Address of a DMA transfer destination data */
DeviceDataPtr->DescriptorPtr->DestinationTransferSize = (LDD_DMA_TTransferSize)DMA_PDD_8_BIT; /* 8-bit destination data transfer size. */
DeviceDataPtr->DescriptorPtr->DestinationModuloSize = (LDD_DMA_TModuloSize)DMA_PDD_CIRCULAR_BUFFER_DISABLED; /* Circular buffer size. */
DeviceDataPtr->DescriptorPtr->DestinationAddressIncrement = TRUE; /* Address incremented after each elemental read operation. */
/* Byte count value */
DeviceDataPtr->DescriptorPtr->ByteCount = (LDD_DMA_TByteCount)SPI1RxDMAByteCount; /* Size of data to be transferred. */
/* Trigger settings */
DeviceDataPtr->DescriptorPtr->TriggerType = LDD_DMA_HW_TRIGGER; /* External peripheral trigger is used */
DeviceDataPtr->DescriptorPtr->TriggerSource = (LDD_DMA_TTriggerSource)0x12U; /* External peripheral trigger source number */
DeviceDataPtr->DescriptorPtr->PeriodicTrigger = FALSE; /* Periodic trigger mode is not used */
DeviceDataPtr->DescriptorPtr->ChannelAutoSelection = FALSE; /* DMA channel fixed value */
DeviceDataPtr->DescriptorPtr->ChannelNumber = (LDD_DMA_TChannelNumber)0x03U; /* DMA channel number */
DeviceDataPtr->DescriptorPtr->AsynchronousRequests = FALSE; /* DMA channel asynchronous requests disabled. */
/* Inner and outer loop linking settings */
DeviceDataPtr->DescriptorPtr->ChannelLinkingMode = LDD_DMA_LINKING_DISABLED; /* Channel linking disabled. */
DeviceDataPtr->DescriptorPtr->InnerLoopLinkedChannel = 0x00U; /* Linked DMA channel number not used. */
DeviceDataPtr->DescriptorPtr->OuterLoopLinkedChannel = 0x00U; /* Linked DMA channel number not used. */
/* Transfer control settings */
DeviceDataPtr->DescriptorPtr->TransferMode = LDD_DMA_CYCLE_STEAL_TRANSFERS; /* Cycle-steal transfers - one elementary read-write transfer per request. */
DeviceDataPtr->DescriptorPtr->DisableAfterRequest = TRUE; /* Disable after request. */
/* Interrupts and events settings */
DeviceDataPtr->DescriptorPtr->Interrupts = TRUE; /* Interrupts are requested. */
DeviceDataPtr->DescriptorPtr->OnComplete = TRUE; /* Event enabled in initialization code. */
DeviceDataPtr->DescriptorPtr->OnError = TRUE; /* Event enabled in initialization code. */
DeviceDataPtr->DescriptorPtr->OnCompleteEventPtr = &DMAT_S_SPI_RX_OnComplete; /* Pointer to the OnTransferComplete event */
DeviceDataPtr->DescriptorPtr->OnErrorEventPtr = &DMAT_S_SPI_RX_OnError; /* Pointer to the OnError event */
DeviceDataPtr->DescriptorPtr->ChannelEnabled = FALSE; /* Descriptor is not allocating nor using any channel. */
if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_DMA_CTRL_ID] == NULL) {
DeviceDataPtr->DMA_LDD_DeviceDataPtr = DMA_CTRL_Init(NULL);
}
else {
DeviceDataPtr->DMA_LDD_DeviceDataPtr = PE_LDD_DeviceDataList[PE_LDD_COMPONENT_DMA_CTRL_ID];
}
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_DMAT_S_SPI_RX_ID,DeviceDataPtr);
return ((LDD_TDeviceData *)DeviceDataPtr); /* Return pointer to the data data structure. */
}
/* ===================================================================*/
LDD_TDeviceData* ASerialLdd2_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
ASerialLdd2_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* SIM_SCGC4: UART0=1 */
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
/* PORTB_PCR16: ISF=0,MUX=3 */
PORTB_PCR16 = (uint32_t)((PORTB_PCR16 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
/* PORTB_PCR17: ISF=0,MUX=3 */
PORTB_PCR17 = (uint32_t)((PORTB_PCR17 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
UART_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
UART_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
DeviceDataPrv->ErrFlag = 0x00U; /* Reset error flags */
/* UART0_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
UART0_C1 = 0x00U; /* Set the C1 register */
/* UART0_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART0_C3 = 0x00U; /* Set the C3 register */
/* UART0_C4: MAEN1=0,MAEN2=0,M10=0,BRFA=0 */
UART0_C4 = UART_C4_BRFA(0x00); /* Set the C4 register */
/* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART0_S2 = 0x00U; /* Set the S2 register */
/* UART0_MODEM: ??=0,??=0,??=0,??=0,RXRTSE=0,TXRTSPOL=0,TXRTSE=0,TXCTSE=0 */
UART0_MODEM = 0x00U; /* Set the MODEM register */
UART_PDD_SetBaudRateFineAdjust(UART0_BASE_PTR, 18u); /* Set baud rate fine adjust */
UART_PDD_SetBaudRate(UART0_BASE_PTR, 13U); /* Set the baud rate register. */
UART_PDD_EnableFifo(UART0_BASE_PTR, (UART_PDD_TX_FIFO_ENABLE | UART_PDD_RX_FIFO_ENABLE)); /* Enable RX and TX FIFO */
UART_PDD_FlushFifo(UART0_BASE_PTR, (UART_PDD_TX_FIFO_FLUSH | UART_PDD_RX_FIFO_FLUSH)); /* Flush RX and TX FIFO */
UART_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_ENABLE); /* Enable transmitter */
UART_PDD_EnableReceiver(UART0_BASE_PTR, PDD_ENABLE); /* Enable receiver */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ASerialLdd2_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* IO1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
IO1_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* SIM_SCGC4: UART0=1 */
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
/* PORTA_PCR1: ISF=0,MUX=2 */
PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTA_PCR2: ISF=0,MUX=2 */
PORTA_PCR2 = (uint32_t)((PORTA_PCR2 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
DeviceDataPrv->EventMask = 0x00u; /* Initialization of the event mask variable */
DeviceDataPrv->EnUser = TRUE; /* Enable device */
/* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
UART0_C1 = 0x00U; /* Set the C1 register */
/* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART0_C3 = 0x00U; /* Set the C3 register */
/* UART0_C4: MAEN1=0,MAEN2=0,M10=0,OSR=0 */
UART0_C4 = UART0_C4_OSR(0x00); /* Set the C4 register */
/* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART0_S2 = 0x00U; /* Set the S2 register */
UART0_PDD_SetClockSource(UART0_BASE_PTR, UART0_PDD_PLL_FLL_CLOCK);
UART0_PDD_SetBaudRate(UART0_BASE_PTR, 52U); /* Set the baud rate register. */
UART0_PDD_SetOversamplingRatio(UART0_BASE_PTR, 3U);
UART0_PDD_EnableSamplingOnBothEdges(UART0_BASE_PTR, PDD_ENABLE);
UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_ENABLE); /* Enable transmitter */
UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_ENABLE); /* Enable receiver */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_IO1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* DMA1_Init(void)
{
DMA1_TDeviceData *DevDataPtr; /* LDD device structure */
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DevDataPtr = &DevDataPtr__DEFAULT_RTOS_ALLOC;
/* {Default RTOS Adapter} Driver memory allocation: Fill the allocated memory by zero value */
PE_FillMemory(DevDataPtr, 0U, sizeof(DMA1_TDeviceData));
/* Transfer complete interrupt vector(INT_DMA0) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_DMA0__DEFAULT_RTOS_ISRPARAM = DevDataPtr;
/* Transfer error interrupt vector(INT_DMA_Error) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_DMA_Error__DEFAULT_RTOS_ISRPARAM = DevDataPtr;
/* Transfer complete interrupt vector(INT_DMA0) priority setting */
/* NVIC_IPR0: PRI_0=1 */
NVIC_IPR0 = (uint32_t)((NVIC_IPR0 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_0(0x02)
)) | (uint32_t)(
NVIC_IP_PRI_0(0x01)
));
/* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=0,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=0,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=0,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=0,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=1 */
NVIC_ISER = NVIC_ISER_SETENA0_MASK;
/* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
NVIC_ICER = 0x00U;
/* Transfer error interrupt vector(INT_DMA_Error) priority setting */
/* NVIC_IPR1: PRI_4=1 */
NVIC_IPR1 = (uint32_t)((NVIC_IPR1 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_4(0x02)
)) | (uint32_t)(
NVIC_IP_PRI_4(0x01)
));
/* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=0,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=0,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=0,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=1,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=0 */
NVIC_ISER = NVIC_ISER_SETENA4_MASK;
/* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
NVIC_ICER = 0x00U;
/* Enable clock gates */
#ifdef SIM_PDD_CLOCK_GATE_DMA
SIM_PDD_SetClockGate(SIM_BASE_PTR, SIM_PDD_CLOCK_GATE_DMA, PDD_ENABLE);
#endif
#ifdef SIM_PDD_CLOCK_GATE_DMAMUX
SIM_PDD_SetClockGate(SIM_BASE_PTR, SIM_PDD_CLOCK_GATE_DMAMUX, PDD_ENABLE);
#endif
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_DMA1_ID,DevDataPtr);
/* Discard previous setting */
DMA_PDD_ClearRequestEnable(DMA_BASE_PTR, DMA_PDD_ALL_CHANNELS, 0x00U); /* Disable all request from peripheral */
DMA_PDD_ClearErrorInterruptEnable(DMA_BASE_PTR, DMA_PDD_ALL_CHANNELS, 0x00U); /* Disable all error interrupts */
DMA_PDD_CancelTransfer(DMA_BASE_PTR); /* Cancel transfer (if any in progress) */
DMA_PDD_ClearInterruptFlags(DMA_BASE_PTR, DMA_PDD_ALL_CHANNELS, 0x00U); /* Clear all channel interrupt flags */
DMA_PDD_InitChannelsPriority(DMA_BASE_PTR,DMA1_DevConst.ChnPriorities); /* Initialize channel TCD (channel registers) */
DMA_CR = 0x00U; /* initialize Control register */
return DevDataPtr;
}
/* ===================================================================*/
LDD_TDeviceData* TU2_Init(LDD_TUserData *UserDataPtr)
{
TU2_TDeviceData *DeviceDataPrv;
if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID] == NULL) {
/* Allocate device structure */
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->InitCntr = 1U; /* First initialization */
}
else {
/* Memory is already allocated */
DeviceDataPrv = (TU2_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID];
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->InitCntr++; /* Increment counter of initialization */
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* Interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_FTM1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* SIM_SCGC6: FTM1=1 */
SIM_SCGC6 |= SIM_SCGC6_FTM1_MASK;
/* FTM1_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */
FTM1_MODE = (FTM_MODE_FAULTM(0x00) | FTM_MODE_WPDIS_MASK); /* Set up mode register */
/* FTM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */
FTM1_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00)); /* Clear status and control register */
/* FTM1_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */
FTM1_CNTIN = FTM_CNTIN_INIT(0x00); /* Clear counter initial register */
/* FTM1_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */
FTM1_CNT = FTM_CNT_COUNT(0x00); /* Reset counter register */
/* FTM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,ICRST=0,DMA=0 */
FTM1_C0SC = 0x00U; /* Clear channel status and control register */
/* FTM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,ICRST=0,DMA=0 */
FTM1_C1SC = 0x00U; /* Clear channel status and control register */
/* FTM1_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0x8C9B */
FTM1_MOD = FTM_MOD_MOD(0x8C9B); /* Set up modulo register */
DeviceDataPrv->EnEvents = 0x0100U; /* Enable selected events */
/* NVIC_IPR4: PRI_18=1 */
NVIC_IPR4 = (uint32_t)((NVIC_IPR4 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_18(0x02)
)) | (uint32_t)(
NVIC_IP_PRI_18(0x01)
));
/* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=1,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=0,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=0,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=0,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=0 */
NVIC_ISER = NVIC_ISER_SETENA18_MASK;
/* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
NVIC_ICER = 0x00U;
/* FTM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=1,CPWMS=0,CLKS=1,PS=1 */
FTM1_SC = (FTM_SC_TOIE_MASK | FTM_SC_CLKS(0x01) | FTM_SC_PS(0x01)); /* Set up status and control register */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU2_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* ===================================================================*/
LDD_TDeviceData* MB_UART_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
MB_UART_TDeviceDataPtr DeviceDataPrv;
/* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Allocate interrupt vectors */
/* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */
/* Note: Exception handler for interrupt is not saved, because it is not modified */
DeviceDataPrv->SavedISRSettings.isrData = _int_get_isr_data(LDD_ivIndex_INT_UART2);
DeviceDataPrv->SavedISRSettings.isrFunction = _int_install_isr(LDD_ivIndex_INT_UART2, MB_UART_Interrupt, DeviceDataPrv);
/* SIM_SCGC: UART2=1 */
SIM_SCGC |= SIM_SCGC_UART2_MASK;
/* SIM_PINSEL1: UART2PS=0 */
SIM_PINSEL1 &= (uint32_t)~(uint32_t)(SIM_PINSEL1_UART2PS_MASK);
/* NVIC_IPR3: PRI_14=1 */
NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_14(0x02)
)) | (uint32_t)(
NVIC_IP_PRI_14(0x01)
));
/* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=0,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=1,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=0,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=0,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=0 */
NVIC_ISER = NVIC_ISER_SETENA14_MASK;
/* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
NVIC_ICER = 0x00U;
UART_PDD_EnableTransmitter(UART2_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
UART_PDD_EnableReceiver(UART2_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
/* UART2_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
UART2_C1 = 0x00U; /* Set the C1 register */
/* UART2_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART2_C3 = 0x00U; /* Set the C3 register */
/* UART2_S2: LBKDIF=0,RXEDGIF=0,??=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART2_S2 = 0x00U; /* Set the S2 register */
UART_PDD_SetBaudRate(UART2_BASE_PTR, 52U); /* Set the baud rate register. */
UART_PDD_EnableTransmitter(UART2_BASE_PTR, PDD_ENABLE); /* Enable transmitter */
UART_PDD_EnableReceiver(UART2_BASE_PTR, PDD_ENABLE); /* Enable receiver */
UART_PDD_EnableInterrupt(UART2_BASE_PTR, ( UART_PDD_INTERRUPT_RECEIVER )); /* Enable interrupts */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_MB_UART_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* SS_SPI1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
SS_SPI1_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->EnUser = FALSE; /* Disable device */
DeviceDataPrv->ErrFlag = 0x00U; /* Clear error flags */
/* SIM_SCGC4: SPI1=1 */
SIM_SCGC4 |= SIM_SCGC4_SPI1_MASK;
/* SPI1_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=0,CPOL=0,CPHA=1,SSOE=0,LSBFE=0 */
SPI1_C1 = SPI_C1_CPHA_MASK; /* Clear control register */
/* PORTD_PCR6: ISF=0,MUX=2 */
PORTD_PCR6 = (uint32_t)((PORTD_PCR6 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTD_PCR7: ISF=0,MUX=2 */
PORTD_PCR7 = (uint32_t)((PORTD_PCR7 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTD_PCR5: ISF=0,MUX=2 */
PORTD_PCR5 = (uint32_t)((PORTD_PCR5 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTD_PCR4: ISF=0,MUX=2 */
PORTD_PCR4 = (uint32_t)((PORTD_PCR4 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* SPI1_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=0,CPOL=0,CPHA=1,SSOE=0,LSBFE=0 */
SPI1_C1 = SPI_C1_CPHA_MASK; /* Set Configuration register */
/* SPI1_C2: SPMIE=0,??=0,TXDMAE=0,MODFEN=0,BIDIROE=0,RXDMAE=0,SPISWAI=0,SPC0=0 */
SPI1_C2 = 0x00U; /* Set Configuration register */
/* SPI1_BR: ??=0,SPPR=0,SPR=0 */
SPI1_BR = (SPI_BR_SPPR(0x00) | SPI_BR_SPR(0x00)); /* Set baud rate register */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SS_SPI1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
/* ===================================================================*/
LDD_TDeviceData* TU2_Init(LDD_TUserData *UserDataPtr)
{
TU2_TDeviceData *DeviceDataPrv;
if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID] == NULL) {
/* Allocate device structure */
/* {FreeRTOS RTOS Adapter} Driver memory allocation: RTOS function call is defined by FreeRTOS RTOS Adapter property */
DeviceDataPrv = (TU2_TDeviceData *)pvPortMalloc(sizeof(TU2_TDeviceData));
#if FreeRTOS_CHECK_MEMORY_ALLOCATION_ERRORS
if (DeviceDataPrv == NULL) {
return (NULL);
}
#endif
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->InitCntr = 1U; /* First initialization */
}
else {
/* Memory is already allocated */
DeviceDataPrv = (TU2_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID];
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->InitCntr++; /* Increment counter of initialization */
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* SIM_SCGC6: TPM1=1 */
SIM_SCGC6 |= SIM_SCGC6_TPM1_MASK;
/* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=0,CPWMS=0,CMOD=0,PS=0 */
TPM1_SC = (TPM_SC_CMOD(0x00) | TPM_SC_PS(0x00)); /* Clear status and control register */
/* TPM1_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */
TPM1_CNT = TPM_CNT_COUNT(0x00); /* Reset counter register */
/* TPM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
TPM1_C0SC = 0x00U; /* Clear channel status and control register */
/* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
TPM1_C1SC = 0x00U; /* Clear channel status and control register */
/* TPM1_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0x02B3 */
TPM1_MOD = TPM_MOD_MOD(0x02B3); /* Set up modulo register */
/* TPM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */
TPM1_C0SC = (TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_ELSA_MASK); /* Set up channel status and control register */
/* TPM1_C0V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0 */
TPM1_C0V = TPM_CnV_VAL(0x00); /* Set up channel value register */
/* PORTE_PCR20: ISF=0,MUX=3 */
PORTE_PCR20 = (uint32_t)((PORTE_PCR20 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
DeviceDataPrv->Source = TPM_PDD_SYSTEM; /* Store clock source */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU2_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* ===================================================================*/
LDD_TDeviceData* ASerialLdd1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
ASerialLdd1_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Allocate interrupt vectors */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_UART2__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* SIM_SCGC: UART2=1 */
SIM_SCGC |= SIM_SCGC_UART2_MASK;
/* SIM_PINSEL1: UART2PS=1 */
SIM_PINSEL1 |= SIM_PINSEL1_UART2PS_MASK;
/* NVIC_IPR3: PRI_14=1 */
NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_14(0x02)
)) | (uint32_t)(
NVIC_IP_PRI_14(0x01)
));
/* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=0,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=1,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=0,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=0,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=0 */
NVIC_ISER = NVIC_ISER_SETENA14_MASK;
/* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
NVIC_ICER = 0x00U;
UART_PDD_EnableTransmitter(UART2_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
UART_PDD_EnableReceiver(UART2_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
DeviceDataPrv->ErrFlag = 0x00U; /* Reset error flags */
/* UART2_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
UART2_C1 = 0x00U; /* Set the C1 register */
/* UART2_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART2_C3 = 0x00U; /* Set the C3 register */
/* UART2_S2: LBKDIF=0,RXEDGIF=0,??=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART2_S2 = 0x00U; /* Set the S2 register */
UART_PDD_SetBaudRate(UART2_BASE_PTR, 13U); /* Set the baud rate register. */
UART_PDD_EnableTransmitter(UART2_BASE_PTR, PDD_ENABLE); /* Enable transmitter */
UART_PDD_EnableReceiver(UART2_BASE_PTR, PDD_ENABLE); /* Enable receiver */
UART_PDD_EnableInterrupt(UART2_BASE_PTR, ( UART_PDD_INTERRUPT_RECEIVER | UART_PDD_INTERRUPT_PARITY_ERROR | UART_PDD_INTERRUPT_FRAMING_ERROR | UART_PDD_INTERRUPT_NOISE_ERROR | UART_PDD_INTERRUPT_OVERRUN_ERROR )); /* Enable interrupts */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ASerialLdd1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* DMA1_Init(LDD_TUserData *UserDataPtr)
{
uint8_t i;
DMA1_TDeviceData *DeviceDataPtr; /* LDD device structure */
DMA1_TDescriptorRecord *DescriptorRecordPtr; /* Auxiliary local pointer to internal descriptor records. */
/* Allocate HAL device structure */
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPtr = &DeviceDataPtr__DEFAULT_RTOS_ALLOC;
DeviceDataPtr->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Enable device clock gate */
/* SIM_SCGC7: DMA=1 */
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
/* SIM_SCGC6: DMAMUX=1 */
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
/* Transfer compete interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_DMA2__DEFAULT_RTOS_ISRPARAM = DeviceDataPtr;
/* Transfer compete interrupt vector(s) priority setting */
/* NVIC_IPR0: PRI_2=0x80 */
NVIC_IPR0 = (uint32_t)((NVIC_IPR0 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_2(0x7F)
)) | (uint32_t)(
NVIC_IP_PRI_2(0x80)
));
/* NVIC_ISER: SETENA|=4 */
NVIC_ISER |= NVIC_ISER_SETENA(0x04);
for (i = 0U; i < DMA1_DMA_CHANNELS_NUMBER; i++) {
DMA_PDD_WriteControlReg(DMA_BASE_PTR, i, 0U); /* Clear control register. Disable all interrupts and HW requests. */
DMA_PDD_ClearInterruptFlags(DMA_BASE_PTR, i, DMA_PDD_TRANSFER_COMPLETE_FLAG); /* Clear request interrupt flags */
}
/* Initialization of channels record field. */
memset(DeviceDataPtr->ChannelRecord, 0, DMA1_DMA_CHANNELS_NUMBER * sizeof(DeviceDataPtr->ChannelRecord[0]));
//for(i = 0U; i < DMA1_DMA_CHANNELS_NUMBER; i++) {
// DeviceDataPtr->ChannelRecord[i] = NULL; /* Clear pointer to descriptor record of all channels. */
//}
/* Initialization of channel and descriptor record fields. */
for(i = 0U; i < DMA1_CONFIGURED_CHANNELS_NUMBER; i++) {
DescriptorRecordPtr = &(DeviceDataPtr->DescriptorRecord[i]); /* Store local pointer to descriptor record. */
DescriptorRecordPtr->ChannelNumber = DMA1_ChannelNumbers[i]; /* Store associated channel number. */
DescriptorRecordPtr->DescriptorPtr = NULL; /* Set channel as free. */
DescriptorRecordPtr->Interrupts = DMA1_ChannelInterrupts[i]; /* Store associated channel interrupts enabled/disabled status. */
DescriptorRecordPtr->Initialized = FALSE; /* Set channel as not initialized. */
DescriptorRecordPtr->Enabled = FALSE; /* Set channel as disabled. */
DeviceDataPtr->ChannelRecord[DMA1_ChannelNumbers[i]] = DescriptorRecordPtr; /* Store pointers to descriptor records of fixed channels. */
DeviceDataPtr->EventMask[DMA1_ChannelNumbers[i]] = 0U; /* Clear channel event mask. */
}
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_DMA1_ID,DeviceDataPtr);
return ((LDD_TDeviceData *)DeviceDataPtr); /* Return pointer to the data structure */
}
/* ===================================================================*/
LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr)
{
TU1_TDeviceData *DeviceDataPrv;
if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID] == NULL) {
/* Allocate device structure */
/* {FreeRTOS RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->InitCntr = 1U; /* First initialization */
}
else {
/* Memory is already allocated */
DeviceDataPrv = (TU1_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID];
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->InitCntr++; /* Increment counter of initialization */
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* SIM_SCGC6: TPM1=1 */
SIM_SCGC6 |= SIM_SCGC6_TPM1_MASK;
/* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=0,CPWMS=0,CMOD=0,PS=0 */
TPM1_SC = (TPM_SC_CMOD(0x00) | TPM_SC_PS(0x00)); /* Clear status and control register */
/* TPM1_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */
TPM1_CNT = TPM_CNT_COUNT(0x00); /* Reset counter register */
/* TPM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
TPM1_C0SC = 0x00U; /* Clear channel status and control register */
/* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
TPM1_C1SC = 0x00U; /* Clear channel status and control register */
/* TPM1_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0xCCCC */
TPM1_MOD = TPM_MOD_MOD(0xCCCC); /* Set up modulo register */
/* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */
TPM1_C1SC = (TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_ELSA_MASK); /* Set up channel status and control register */
/* TPM1_C1V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0x0F5C */
TPM1_C1V = TPM_CnV_VAL(0x0F5C); /* Set up channel value register */
/* PORTA_PCR13: ISF=0,MUX=3 */
PORTA_PCR13 = (uint32_t)((PORTA_PCR13 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
DeviceDataPrv->Source = TPM_PDD_SYSTEM; /* Store clock source */
/* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=0,CPWMS=0,CMOD=1,PS=3 */
TPM1_SC = (TPM_SC_CMOD(0x01) | TPM_SC_PS(0x03)); /* Set up status and control register */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* ===================================================================*/
LDD_TDeviceData* BitsIoLdd2_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
BitsIoLdd2_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Configure pin directions */
/* GPIOE_PDDR: PDD&=~0x3C */
GPIOE_PDDR &= (uint32_t)~(uint32_t)(GPIO_PDDR_PDD(0x3C));
/* Initialization of Port Control register */
/* PORTE_PCR2: ISF=0,MUX=1 */
PORTE_PCR2 = (uint32_t)((PORTE_PCR2 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x06)
)) | (uint32_t)(
PORT_PCR_MUX(0x01)
));
/* PORTE_PCR3: ISF=0,MUX=1 */
PORTE_PCR3 = (uint32_t)((PORTE_PCR3 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x06)
)) | (uint32_t)(
PORT_PCR_MUX(0x01)
));
/* PORTE_PCR4: ISF=0,MUX=1 */
PORTE_PCR4 = (uint32_t)((PORTE_PCR4 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x06)
)) | (uint32_t)(
PORT_PCR_MUX(0x01)
));
/* PORTE_PCR5: ISF=0,MUX=1 */
PORTE_PCR5 = (uint32_t)((PORTE_PCR5 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x06)
)) | (uint32_t)(
PORT_PCR_MUX(0x01)
));
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_BitsIoLdd2_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* SUB_BTN_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
SUB_BTN_TDeviceDataPtr DeviceDataPrv;
/* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Configure pin as input */
/* GPIOB_PDDR: PDD&=~0x10000000 */
GPIOB_PDDR &= (uint32_t)~(uint32_t)(GPIO_PDDR_PDD(0x10000000));
/* GPIOB_PIDR: PID&=~0x10000000 */
GPIOB_PIDR &= (uint32_t)~(uint32_t)(GPIO_PIDR_PID(0x10000000));
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SUB_BTN_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* TU2_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
TU2_TDeviceData *DeviceDataPrv;
/* {FreeRTOS RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Interrupt vector(s) allocation */
/* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_TPM1__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv;
/* SIM_SCGC6: TPM1=1 */
SIM_SCGC6 |= SIM_SCGC6_TPM1_MASK;
/* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=0,CPWMS=0,CMOD=0,PS=0 */
TPM1_SC = (TPM_SC_CMOD(0x00) | TPM_SC_PS(0x00)); /* Clear status and control register */
/* TPM1_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */
TPM1_CNT = TPM_CNT_COUNT(0x00); /* Reset counter register */
/* TPM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
TPM1_C0SC = 0x00U; /* Clear channel status and control register */
/* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
TPM1_C1SC = 0x00U; /* Clear channel status and control register */
/* TPM1_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0xFFFF */
TPM1_MOD = TPM_MOD_MOD(0xFFFF); /* Set up modulo register */
/* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=1,MSB=0,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */
TPM1_C1SC = (TPM_CnSC_CHIE_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_ELSA_MASK); /* Set up channel status and control register */
/* PORTA_PCR13: ISF=0,MUX=3 */
PORTA_PCR13 = (uint32_t)((PORTA_PCR13 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x04)
)) | (uint32_t)(
PORT_PCR_MUX(0x03)
));
DeviceDataPrv->EnEvents = 0x0101U; /* Enable selected events */
/* NVIC_IPR4: PRI_18=0x80 */
NVIC_IPR4 = (uint32_t)((NVIC_IPR4 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_18(0x7F)
)) | (uint32_t)(
NVIC_IP_PRI_18(0x80)
));
/* NVIC_ISER: SETENA|=0x00040000 */
NVIC_ISER |= NVIC_ISER_SETENA(0x00040000);
/* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=1,CPWMS=0,CMOD=1,PS=4 */
TPM1_SC = (TPM_SC_TOIE_MASK | TPM_SC_CMOD(0x01) | TPM_SC_PS(0x04)); /* Set up status and control register */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU2_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* ===================================================================*/
LDD_TDeviceData* GPIO1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
GPIO1_TDeviceData *DeviceDataPrv;
/* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Save RTOS Device structure */
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
/* GPIOB_PDOR: PDO&=~0x00200000 */
GPIOB_PDOR &= (uint32_t)~(uint32_t)(GPIO_PDOR_PDO(0x00200000));
/* GPIOB_PDDR: PDD|=0x00200000 */
GPIOB_PDDR |= GPIO_PDDR_PDD(0x00200000);
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_GPIO1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr)
{
TU1_TDeviceData *DeviceDataPrv;
if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID] == NULL) {
/* Allocate device structure */
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->InitCntr = 1U; /* First initialization */
}
else {
/* Memory is already allocated */
DeviceDataPrv = (TU1_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID];
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->InitCntr++; /* Increment counter of initialization */
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* Interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_LPTimer__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* SIM_SCGC5: LPTMR=1 */
SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;
/* LPTMR0_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF=1,TIE=0,TPS=0,TPP=0,TFC=0,TMS=0,TEN=0 */
LPTMR0_CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00)); /* Clear control register */
/* LPTMR0_CMR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COMPARE=0xFFFF */
LPTMR0_CMR = LPTMR_CMR_COMPARE(0xFFFF); /* Set up compare register */
/* LPTMR0_PSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,PRESCALE=0,PBYP=1,PCS=0 */
LPTMR0_PSR = LPTMR_PSR_PRESCALE(0x00) |
LPTMR_PSR_PBYP_MASK |
LPTMR_PSR_PCS(0x00); /* Set up prescaler register */
/* NVIC_IPR7: PRI_28=0x80 */
NVIC_IPR7 = (uint32_t)((NVIC_IPR7 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_28(0x7F)
)) | (uint32_t)(
NVIC_IP_PRI_28(0x80)
));
/* NVIC_ISER: SETENA|=0x10000000 */
NVIC_ISER |= NVIC_ISER_SETENA(0x10000000);
/* LPTMR0_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF=0,TIE=1,TPS=0,TPP=0,TFC=0,TMS=0,TEN=1 */
LPTMR0_CSR = (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TPS(0x00) | LPTMR_CSR_TEN_MASK); /* Set up control register */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* ===================================================================*/
LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr)
{
TU1_TDeviceData *DeviceDataPrv;
if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID] == NULL) {
/* Allocate device structure */
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->InitCntr = 1U; /* First initialization */
}
else {
/* Memory is already allocated */
DeviceDataPrv = (TU1_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID];
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->InitCntr++; /* Increment counter of initialization */
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* Interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_PIT__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* SIM_SCGC6: PIT=1 */
SIM_SCGC6 |= SIM_SCGC6_PIT_MASK;
/* PIT_MCR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MDIS=0,FRZ=0 */
PIT_MCR = 0x00U; /* Enable device clock */
/* PIT_TCTRL0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHN=0,TIE=0,TEN=0 */
PIT_TCTRL0 = 0x00U; /* Clear control register */
/* PIT_TFLG0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TIF=1 */
PIT_TFLG0 = PIT_TFLG_TIF_MASK; /* Clear timer flag register */
/* PIT_LDVAL0: TSV=0x4E1F */
PIT_LDVAL0 = PIT_LDVAL_TSV(0x4E1F); /* Set up load register */
/* NVIC_IPR5: PRI_22=0x80 */
NVIC_IPR5 = (uint32_t)((NVIC_IPR5 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_22(0x7F)
)) | (uint32_t)(
NVIC_IP_PRI_22(0x80)
));
/* NVIC_ISER: SETENA|=0x00400000 */
NVIC_ISER |= NVIC_ISER_SETENA(0x00400000);
/* PIT_TCTRL0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHN=0,TIE=1,TEN=1 */
PIT_TCTRL0 = (PIT_TCTRL_TIE_MASK | PIT_TCTRL_TEN_MASK); /* Set up control register */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* ===================================================================*/
LDD_TDeviceData* MB_DTR_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
MB_DTR_TDeviceDataPtr DeviceDataPrv;
/* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Configure pin as output */
/* GPIOA_PDDR: PDD|=0x20000000 */
GPIOA_PDDR |= GPIO_PDDR_PDD(0x20000000);
/* Set initialization value */
/* GPIOA_PDOR: PDO&=~0x20000000 */
GPIOA_PDOR &= (uint32_t)~(uint32_t)(GPIO_PDOR_PDO(0x20000000));
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_MB_DTR_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* ExtIntLdd2_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
ExtIntLdd2_TDeviceData *DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Store the UserData pointer */
DeviceDataPrv->UserData = UserDataPtr;
/* Interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_PORTA__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* Enable device clock gate */
/* SIM_SCGC5: PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* Initialization of pin routing */
/* PORTA_PCR4: ISF=0,MUX=1 */
PORTA_PCR4 = (uint32_t)((PORTA_PCR4 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x06)
)) | (uint32_t)(
PORT_PCR_MUX(0x01)
));
/* PORTA_PCR4: ISF=1,IRQC=0x0B */
PORTA_PCR4 = (uint32_t)((PORTA_PCR4 & (uint32_t)~(uint32_t)(
PORT_PCR_IRQC(0x04)
)) | (uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_IRQC(0x0B)
));
/* NVIC_IPR7: PRI_30=1 */
NVIC_IPR7 = (uint32_t)((NVIC_IPR7 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_30(0x02)
)) | (uint32_t)(
NVIC_IP_PRI_30(0x01)
));
/* NVIC_ISER: SETENA31=0,SETENA30=1,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=0,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=0,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=0,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=0,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=0 */
NVIC_ISER = NVIC_ISER_SETENA30_MASK;
/* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
NVIC_ICER = 0x00U;
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ExtIntLdd2_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* IntFlashLdd1_Init(LDD_TUserData *UserDataPtr)
{
IntFlashLdd1_TDeviceDataPtr DeviceDataPrv;
/* Allocate LDD device structure */
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->CurrentOperationStatus = LDD_FLASH_IDLE; /* Initialization of the Current operation status item */
DeviceDataPrv->CurrentOperation = LDD_FLASH_NO_OPERATION; /* Initialization of the Current operation type item */
DeviceDataPrv->CurrentErrorFlags = 0U; /* Initialization of the Current error flags item */
DeviceDataPrv->CurrentDataPtr = NULL; /* Initialization of the Current data pointer item */
/* Copy of the safe routine to a buffer for execution */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store a pointer to the User data structure */
/* SIM_SCGC6: FTF=1 */
SIM_SCGC6 |= SIM_SCGC6_FTF_MASK;
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_IntFlashLdd1_ID,DeviceDataPrv);
return DeviceDataPrv;
}
/*
** ===================================================================
** Method : PwmLdd1_Init (component PWM_LDD)
**
** Description :
** Initializes the device. Allocates memory for the device data
** structure, allocates interrupt vectors and sets interrupt
** priority, sets pin routing, sets timing, etc. If the
** property <"Enable in init. code"> is set to "yes" value then
** the device is also enabled (see the description of the
** <Enable> method). In this case the <Enable> method is not
** necessary and needn't to be generated. This method can be
** called only once. Before the second call of Init the <Deinit>
** must be called first.
** Parameters :
** NAME - DESCRIPTION
** * UserDataPtr - Pointer to the user or
** RTOS specific data. This pointer will be
** passed as an event or callback parameter.
** Returns :
** --- - Pointer to the dynamically allocated
** private structure or NULL if there was an
** error.
** ===================================================================
*/
LDD_TDeviceData* PwmLdd1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
PwmLdd1_TDeviceData *DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->EnUser = TRUE; /* Set the flag "device enabled" */
DeviceDataPrv->RatioStore = 0x01U; /* Ratio after initialization */
DeviceDataPrv->LinkedDeviceDataPtr = TU1_Init((LDD_TUserData *)NULL);
if (DeviceDataPrv->LinkedDeviceDataPtr == NULL) { /* Is initialization of TimerUnit unsuccessful? */
/* Deallocation of the device structure */
/* {Default RTOS Adapter} Driver memory deallocation: Dynamic allocation is simulated, no deallocation code is generated */
return NULL; /* If so, then the PWM initialization is also unsuccessful */
}
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_PwmLdd1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* ===================================================================*/
LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
TU1_TDeviceData *DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* SIM_SCGC6: FTM0=1 */
SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK;
/* FTM0_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */
FTM0_MODE = (FTM_MODE_FAULTM(0x00) | FTM_MODE_WPDIS_MASK); /* Set up mode register */
/* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */
FTM0_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00)); /* Clear status and control register */
/* FTM0_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */
FTM0_CNTIN = FTM_CNTIN_INIT(0x00); /* Clear counter initial register */
/* FTM0_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */
FTM0_CNT = FTM_CNT_COUNT(0x00); /* Reset counter register */
/* FTM0_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
FTM0_C0SC = 0x00U; /* Clear channel status and control register */
/* FTM0_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
FTM0_C1SC = 0x00U; /* Clear channel status and control register */
/* FTM0_C2SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
FTM0_C2SC = 0x00U; /* Clear channel status and control register */
/* FTM0_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
FTM0_C3SC = 0x00U; /* Clear channel status and control register */
/* FTM0_C4SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
FTM0_C4SC = 0x00U; /* Clear channel status and control register */
/* FTM0_C5SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
FTM0_C5SC = 0x00U; /* Clear channel status and control register */
/* FTM0_C6SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
FTM0_C6SC = 0x00U; /* Clear channel status and control register */
/* FTM0_C7SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */
FTM0_C7SC = 0x00U; /* Clear channel status and control register */
/* FTM0_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0xFFFF */
FTM0_MOD = FTM_MOD_MOD(0xFFFF); /* Set up modulo register */
/* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=1,PS=1 */
FTM0_SC = (FTM_SC_CLKS(0x01) | FTM_SC_PS(0x01)); /* Set up status and control register */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* ===================================================================*/
LDD_TDeviceData* TimerIntLdd3_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
TimerIntLdd3_TDeviceData *DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->EnUser = TRUE; /* Set the flag "device enabled" */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TimerIntLdd3_ID,DeviceDataPrv);
DeviceDataPrv->LinkedDeviceDataPtr = TU3_Init((LDD_TUserData *)NULL);
if (DeviceDataPrv->LinkedDeviceDataPtr == NULL) { /* Is initialization of TimerUnit unsuccessful? */
/* Unregistration of the device structure */
PE_LDD_UnregisterDeviceStructure(PE_LDD_COMPONENT_TimerIntLdd3_ID);
/* Deallocation of the device structure */
/* {Default RTOS Adapter} Driver memory deallocation: Dynamic allocation is simulated, no deallocation code is generated */
return NULL; /* If so, then the TimerInt initialization is also unsuccessful */
}
TimerIntLdd3_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Set Initial according clock configuration */
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
/* ===================================================================*/
LDD_TDeviceData* ExtIntLdd1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
ExtIntLdd1_TDeviceData *DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Store the UserData pointer */
DeviceDataPrv->UserData = UserDataPtr;
/* Interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_PORTC_PORTD__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* Initialization of Port Control registers */
/* PORTC_PCR3: ISF=0,MUX=1 */
PORTC_PCR3 = (uint32_t)((PORTC_PCR3 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x06)
)) | (uint32_t)(
PORT_PCR_MUX(0x01)
));
/* PORTC_PCR3: ISF=1,IRQC=0x0A */
PORTC_PCR3 = (uint32_t)((PORTC_PCR3 & (uint32_t)~(uint32_t)(
PORT_PCR_IRQC(0x05)
)) | (uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_IRQC(0x0A)
));
/* NVIC_IPR7: PRI_31=0x80 */
NVIC_IPR7 = (uint32_t)((NVIC_IPR7 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_31(0x7F)
)) | (uint32_t)(
NVIC_IP_PRI_31(0x80)
));
/* NVIC_ISER: SETENA|=0x80000000 */
NVIC_ISER |= NVIC_ISER_SETENA(0x80000000);
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ExtIntLdd1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}
