/** * PHY set the correct termination value for the unused lanes * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieSetReciverTerminationTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 Phy; UINT8 PhyLaneIndex; UINT8 Lane; UINT32 LaneBitmap; IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetReciverTerminationTN Enter\n"); if ((Wrapper->WrapId == GFX_WRAP_ID) || (Wrapper->WrapId == GPP_WRAP_ID)) { LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, Wrapper); for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) { if ((LaneBitmap & (1 << Lane)) != 0) { Phy = Lane / MAX_NUM_LANE_PER_PHY; PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY; PcieRegisterRMW ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_C005_ADDRESS + PhyLaneIndex * 0x80), D0F0xE4_PHY_C005_TermMode_MASK, (0x2 << D0F0xE4_PHY_C005_TermMode_OFFSET), FALSE, Pcie ); } } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetReciverTerminationTN Exit\n"); }
/** * PHY lane parameter Init * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Buffer Pointer to buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS PciePhyLaneInitInitCallbackTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 Phy; UINT8 PhyLaneIndex; UINT8 Lane; UINT32 LaneBitmap; IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper); for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) { if ((LaneBitmap & (1 << Lane)) != 0) { Phy = Lane / MAX_NUM_LANE_PER_PHY; PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY; PcieRegisterRMW ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_400A_ADDRESS + PhyLaneIndex * 0x80), D0F0xE4_PHY_400A_BiasDisInLs2_MASK | D0F0xE4_PHY_400A_Ls2ExitTime_MASK, (1 << D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET) | (1 << D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET), FALSE, Pcie ); PcieRegisterRMW ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4002_ADDRESS + PhyLaneIndex * 0x80), D0F0xE4_PHY_4002_LfcMax_MASK, (8 << D0F0xE4_PHY_4002_LfcMax_OFFSET), FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Exit\n"); return AGESA_SUCCESS; }
*/ /*---------------------------------------------------------------------------------------- * T A B L E S *---------------------------------------------------------------------------------------- */ STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { { WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS), D0F0xE4_WRAP_8016_CalibAckLatency_MASK, 0 }, { PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), D0F0xE4_PHY_2008_VdDetectEn_MASK, 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET }, { PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), D0F0xE4_PHY_2008_VdDetectEn_MASK, 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET }, { PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS), D0F0xE4_PHY_2008_VdDetectEn_MASK, 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET }, { PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
/** * PHY lane parameter Init * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Buffer Pointer to buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS STATIC PciePhyLaneInitInitCallbackCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 Phy; UINT8 PhyLaneIndex; UINT8 Lane; UINT32 LaneBitmap; UINTN Index; IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackCZ Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_CORE_ALLOC, 0, Wrapper); if (LaneBitmap == 0) { IDS_HDT_CONSOLE (GNB_TRACE, "No device allocated in this wrapper\n"); return AGESA_SUCCESS; } LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper); for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) { Phy = Lane / MAX_NUM_LANE_PER_PHY; PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY; if ((LaneBitmap & (1 << Lane)) != 0) { for (Index = 0; Index < PhyLaneInitEarlyTableCZ.Length; Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyLaneInitEarlyTableCZ.Table[Index].Reg + (PhyLaneIndex * 0x100)), Pcie ); Value &= (~PhyLaneInitEarlyTableCZ.Table[Index].Mask); Value |= PhyLaneInitEarlyTableCZ.Table[Index].Data; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyLaneInitEarlyTableCZ.Table[Index].Reg + (PhyLaneIndex * 0x100)), Value, FALSE, Pcie ); } } } for (Lane = 0; Lane < Wrapper->NumberOfLanes; Lane += MAX_NUM_LANE_PER_PHY) { Phy = Lane / MAX_NUM_LANE_PER_PHY; for (Index = 0; Index < PhyWrapperInitEarlyTableCZ.Length; Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyWrapperInitEarlyTableCZ.Table[Index].Reg), Pcie ); Value &= (~PhyWrapperInitEarlyTableCZ.Table[Index].Mask); Value |= PhyWrapperInitEarlyTableCZ.Table[Index].Data; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyWrapperInitEarlyTableCZ.Table[Index].Reg), Value, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackCZ Exit\n"); return AGESA_SUCCESS; }
/** * Set Dll Cap based on fuses * * * * @param[in] Wrapper Pointer to Wrapper configuration data area * @param[in] Pcie Pointer to PCIe configuration data area */ VOID PcieSetDllCapTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D18F3x1FC_STRUCT D18F3x1FC; D0F0xE4_PHY_500F_STRUCT D0F0xE4_PHY_500F; D0F0xE4_PHY_4010_STRUCT D0F0xE4_PHY_4010; D0F0xE4_PHY_4011_STRUCT D0F0xE4_PHY_4011; UINT32 Gen1Index; UINT32 Gen2Index; CPU_LOGICAL_ID LogicalId; GNB_HANDLE *GnbHandle; IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Enter\n"); D0F0xE4_PHY_500F.Value = 0; GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie)); ASSERT (GnbHandle != NULL); GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Pcie)); //Read SWDllCapTableEn GnbRegisterReadTN (D18F3x1FC_TYPE, D18F3x1FC_ADDRESS, &D18F3x1FC, 0, GnbLibGetHeader (Pcie)); IDS_HDT_CONSOLE (GNB_TRACE, "Read D18F3x1FC value %x\n", D18F3x1FC.Value); if ((D18F3x1FC.Field.SWDllCapTableEn != 0) || ((LogicalId.Revision & AMD_F15_TN_A0) != AMD_F15_TN_A0 )) { IDS_HDT_CONSOLE (GNB_TRACE, "Executing DLL configuration\n"); // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]0 Phy Receiver Functional Fuse Control (FuseFuncDllProcessCompCtl[1:0]) IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4010 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS)); D0F0xE4_PHY_4010.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS), Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "Read 4010 value = %x\n", D0F0xE4_PHY_4010.Value); // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]1 Phy Receiver Process Fuse Control (FuseProcDllProcessComp[2:0]) IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4011 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS)); D0F0xE4_PHY_4011.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS), Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "Read 4011 value = %x\n", D0F0xE4_PHY_4011.Value); // If FuseProcDllProcessCompCtl[1:0] == 2'b11 Then Gen1Index[3:0] = FuseProcDllProcessComp[2:0], 0 // Else... // If FuseProcDllProcessComp[2:0] == 3'b000 Then Gen1Index[3:0] =4'b1101 //Typical // If FuseProcDllProcessComp[2:0] == 3'b001 Then Gen1Index[3:0] =4'b1111 //Fast // If FuseProcDllProcessComp[2:0] == 3'b010 Then Gen1Index[3:0] =4'b1010 //Slow IDS_HDT_CONSOLE (GNB_TRACE, "FuseFuncDllProcessCompCtl %x\n", D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl); if (D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl == 3) { IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from FuseFuncDllProcessComp %x\n", D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp); Gen1Index = D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp << 1; } else { IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from switch case..."); switch (D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp) { case 0: IDS_HDT_CONSOLE (GNB_TRACE, "case 0 - using 0xd\n"); Gen1Index = 0xd; break; case 1: IDS_HDT_CONSOLE (GNB_TRACE, "case 1 - using 0xf\n"); Gen1Index = 0xf; break; case 2: IDS_HDT_CONSOLE (GNB_TRACE, "case 2 - using 0xa\n"); Gen1Index = 0xa; break; default: IDS_HDT_CONSOLE (GNB_TRACE, "default - using 0xd\n"); Gen1Index = 0xd; //Use typical for default case break; } } D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex1 = Gen1Index; IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen1Index to %x\n", Gen1Index); // Bits 3:0 = Gen1Index[3:0] // Bits 10:7 = DllProcessFreqCtlIndex2Rate50[3:0] if (D18F3x1FC.Field.SWDllCapTableEn != 0) { IDS_HDT_CONSOLE (GNB_TRACE, "Gen2Index - using DllProcFreqCtlIndex2Rate50 = %x\n", D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50); Gen2Index = D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50; } else { Gen2Index = 0x03; // Hard coded default } D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex2 = Gen2Index; IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen2Index to %x\n", Gen2Index); PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS), D0F0xE4_PHY_500F.Value, FALSE, Pcie ); // Set DllProcessFreqCtlOverride on second write D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS), D0F0xE4_PHY_500F.Value, FALSE, Pcie ); if (Wrapper->WrapId == 1) { // For Wrapper 1, configure PHY0 and PHY1 D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 0; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS), D0F0xE4_PHY_500F.Value, FALSE, Pcie ); // Set DllProcessFreqCtlOverride on second write D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS), D0F0xE4_PHY_500F.Value, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Exit\n"); }
IN PCIe_PLATFORM_CONFIG *Pcie ); AGESA_STATUS PcieOnGetGppConfigurationValue ( IN UINT64 ConfigurationSignature, OUT UINT8 *ConfigurationValue ); /*---------------------------------------------------------------------------------------- * T A B L E S *---------------------------------------------------------------------------------------- */ PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = { { PHY_SPACE (0, 0, D0F0xE4_PHY_6440_ADDRESS), D0F0xE4_PHY_6440_RxInCalForce_MASK, 0x1 << D0F0xE4_PHY_6440_RxInCalForce_OFFSET }, { PHY_SPACE (0, 0, D0F0xE4_PHY_6480_ADDRESS), D0F0xE4_PHY_6480_RxInCalForce_MASK, 0x1 << D0F0xE4_PHY_6480_RxInCalForce_OFFSET }, { PHY_SPACE (0, 0, D0F0xE4_PHY_6500_ADDRESS), D0F0xE4_PHY_6500_RxInCalForce_MASK, 0x1 << D0F0xE4_PHY_6500_RxInCalForce_OFFSET }, { PHY_SPACE (0, 0, D0F0xE4_PHY_6600_ADDRESS),