GPIO222_GPIO | PIN_OUTPUT_LOW, /* BT_VREG_EN */
GPIO223_GPIO | PIN_OUTPUT_HIGH, /* MEM_LDO_EN */
GPIO224_GPIO | PIN_INPUT_PULLDOWN, /* NC */
GPIO225_GPIO | PIN_INPUT_PULLDOWN, /* NC */
GPIO226_GPIO | PIN_INPUT_PULLDOWN, /* NC */
GPIO227_GPIO | PIN_INPUT_PULLDOWN, /* NC */
GPIO228_GPIO | PIN_OUTPUT_LOW, /* CAM_MCLK */
GPIO229_GPIO | PIN_INPUT_PULLDOWN, /* TSP_SDA_1V8 */
GPIO230_GPIO | PIN_INPUT_PULLDOWN, /* TSP_SCL_1V8 */
};
/* STM trace or SD Card pin configurations */
static pin_cfg_t golden_bringup_ape_trace[] = {
GPIO22_GPIO | PIN_INPUT_NOPULL, /* CLK-f */
PIN_CFG(23, ALT_C), /* APE CLK */
PIN_CFG(25, ALT_C), /* APE DAT0 */
PIN_CFG(26, ALT_C), /* APE DAT1 */
PIN_CFG(27, ALT_C), /* APE DAT2 */
PIN_CFG(28, ALT_C), /* APE DAT3 */
};
static pin_cfg_t golden_bringup_modem_trace[] = {
GPIO22_GPIO | PIN_INPUT_NOPULL, /* CLK-f */
GPIO23_STMMOD_CLK | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM CLK */
GPIO24_UARTMOD_RXD | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM UART RXD */
GPIO25_STMMOD_DAT0 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
GPIO26_STMMOD_DAT1 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
GPIO27_STMMOD_DAT2 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
GPIO28_STMMOD_DAT3 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
GPIO262_USB_DAT5,
GPIO263_USB_DAT4,
GPIO264_USB_DAT3,
GPIO265_USB_DAT2,
GPIO266_USB_DAT1,
GPIO267_USB_DAT0,
};
/* STM trace or SD Card pin configurations */
static pin_cfg_t gavini_r0_0_ape_trace[] = {
GPIO18_GPIO | PIN_OUTPUT_LOW, /* CMD.Dir */
GPIO19_GPIO | PIN_OUTPUT_HIGH, /* DAT0.Dir */
GPIO20_GPIO | PIN_OUTPUT_HIGH, /* DAT123.Dir */
GPIO22_GPIO | PIN_INPUT_NOPULL, /* CLK-f */
PIN_CFG(23, ALT_C), /* APE CLK */
PIN_CFG(25, ALT_C), /* APE DAT0 */
PIN_CFG(26, ALT_C), /* APE DAT1 */
PIN_CFG(27, ALT_C), /* APE DAT2 */
PIN_CFG(28, ALT_C), /* APE DAT3 */
};
static pin_cfg_t gavini_r0_0_modem_trace[] = {
GPIO18_GPIO | PIN_OUTPUT_LOW, /* CMD.Dir */
GPIO19_GPIO | PIN_OUTPUT_HIGH, /* DAT0.Dir */
GPIO20_GPIO | PIN_OUTPUT_HIGH, /* DAT123.Dir */
GPIO22_GPIO | PIN_INPUT_NOPULL, /* CLK-f */
GPIO23_STMMOD_CLK | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM CLK */
GPIO24_UARTMOD_RXD | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM UART RXD */
GPIO25_STMMOD_DAT0 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
GPIO26_STMMOD_DAT1 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
/* independent module, the terms and conditions of the license of that module. */
/* An independent module is a module which is not derived from this software. The special */
/* exception does not apply to any modifications of the software. */
/* */
/* Notwithstanding the above, under no circumstances may you combine this software in any */
/* way with any other Broadcom software provided under a license other than the GPL, */
/* without Broadcom's express prior written consent. */
/* */
/************************************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <mach/pinmux.h>
static struct __init pin_config board_pin_config[] = {
/* STM trace - PTI */
PIN_CFG(TRACECLK, PTI_CLK, 0, OFF, OFF, 0, 0, 16MA),
PIN_CFG(TRACEDT07, UARTB2_URXD, 0, OFF, OFF, 0, 0, 16MA),
PIN_CFG(TRACEDT00, PTI_DAT0, 0, OFF, OFF, 0, 0, 16MA),
PIN_CFG(TRACEDT01, PTI_DAT1, 0, OFF, OFF, 0, 0, 16MA),
PIN_CFG(TRACEDT02, PTI_DAT2, 0, OFF, OFF, 0, 0, 16MA),
PIN_CFG(TRACEDT03, PTI_DAT3, 0, OFF, OFF, 0, 0, 16MA),
PIN_CFG(ULPI0_DATA_3, UARTB3_URTSN, 0, OFF, OFF, 0, 0, 16MA),
PIN_CFG(ULPI0_DATA_4, UARTB3_UCTSN, 0, OFF, OFF, 0, 0, 16MA),
PIN_CFG(ULPI0_DATA_5, UARTB3_URXD, 0, OFF, OFF, 0, 0, 16MA),
PIN_CFG(ULPI0_DATA_6, UARTB3_UTXD, 0, OFF, OFF, 0, 0, 16MA),
/* PMU INT */
PIN_CFG(PMU_INT, GPIO, 0, OFF, ON, 0, 0, 8MA),
/* Touchscreen uses this for reset pin with GPIO selected */
/* exception does not apply to any modifications of the software. */
/* */
/* Notwithstanding the above, under no circumstances may you combine this software in any */
/* way with any other Broadcom software provided under a license other than the GPL, */
/* without Broadcom's express prior written consent. */
/* */
/************************************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include "mach/pinmux.h"
#include <mach/rdb/brcm_rdb_padctrlreg.h>
static struct __init pin_config board_pin_config[] = {
//@HW
PIN_CFG(GPIO18, UB2TX, 0, OFF, OFF, 0, 0, 8MA), // Console TX
PIN_CFG(SSPDI, RXD, 0, OFF, ON, 0, 0, 8MA), // Console RX
PIN_CFG(ICUSBDP, GPIO121, 0, ON, OFF, 0, 0, 8MA), // UART_SEL
/* PMU BSC */
PIN_BSC_CFG(PMBSCCLK, PMBSCCLK, 0x20), // PMU_SCL
PIN_BSC_CFG(PMBSCDAT, PMBSCDAT, 0x20), // PMU_SDA
/*
* Note:- For eMMC, Enable Slew-rate, Increase pin drive strength to 10mA.
* This is to fix the random eMMC timeout errors due to data crc error
* seen on few rhea edn11 hardware, where eMMC is on a daughter-card.
*
* We may need to revisit these settings for other platforms where the
* pin drive requirements can change.
*
// PIN_CFG(PMUINT, GPIO29, 0, OFF, ON, 1, 0, 8MA), // PMU_IRQ
// PIN_CFG(UBRX, UB1_IF_UART_RX, 0, OFF, ON, 0, 0, 8MA), // UB1_IF_UART_RX
// PIN_CFG(UBTX, UB1_IF_UART_TX, 0, OFF, ON, 0, 0, 8MA), // UB1_IF_UART_TX
// PIN_CFG(ADCSYN, GPEN09, 0, OFF, ON, 0, 0, 8MA), // ADCSYNC_PMU
/*
* Note:- For eMMC, Enable Slew-rate, Increase pin drive strength to 10mA.
* This is to fix the random eMMC timeout errors due to data crc error
* seen on few rhea edn11 hardware, where eMMC is on a daughter-card.
*
* We may need to revisit these settings for other platforms where the
* pin drive requirements can change.
*
*/
/* eMMC */
PIN_CFG(MMC0CK, MMC0CK, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0CMD, MMC0CMD, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0RST, MMC0RST, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT7, MMC0DAT7, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT6, MMC0DAT6, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT5, MMC0DAT5, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT4, MMC0DAT4, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT3, MMC0DAT3, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT2, MMC0DAT2, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT1, MMC0DAT1, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT0, MMC0DAT0, 0, OFF, ON, 1, 0, 10MA),
/* Micro SD - SDIO0 4 bit interface */
PIN_CFG(SDCK, SDCK, 0, OFF, OFF, 0, 0, 8MA),
PIN_CFG(SDCMD, SDCMD, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(SDDAT3, SDDAT3, 0, OFF, ON, 0, 0, 8MA),
/* PMU BSC */
PIN_BSC_CFG(PMBSCCLK, PMBSCCLK, 0x20),
PIN_BSC_CFG(PMBSCDAT, PMBSCDAT, 0x20),
/*
* Note:- For eMMC, Enable Slew-rate, Increase pin drive strength to 10mA.
* This is to fix the random eMMC timeout errors due to data crc error
* seen on few rhea edn11 hardware, where eMMC is on a daughter-card.
*
* We may need to revisit these settings for other platforms where the
* pin drive requirements can change.
*
*/
/* eMMC */
PIN_CFG(MMC0CK, MMC0CK, 0, OFF, OFF, 1, 0, 10MA),
PIN_CFG(MMC0CMD, MMC0CMD, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0RST, MMC0RST, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT7, MMC0DAT7, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT6, MMC0DAT6, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT5, MMC0DAT5, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT4, MMC0DAT4, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT3, MMC0DAT3, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT2, MMC0DAT2, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT1, MMC0DAT1, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT0, MMC0DAT0, 0, OFF, ON, 1, 0, 10MA),
/* Micro SD - SDIO0 4 bit interface */
PIN_CFG(SDCK, SDCK, 0, OFF, OFF, 0, 0, 8MA),
PIN_CFG(SDCMD, SDCMD, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(SDDAT3, SDDAT3, 0, OFF, ON, 0, 0, 8MA),
GPIO222_GPIO | PIN_OUTPUT_LOW, /* BT_VREG_EN */
GPIO223_GPIO | PIN_OUTPUT_HIGH, /* MEM_LDO_EN */
GPIO224_GPIO | PIN_INPUT_PULLDOWN, /* NC */
GPIO225_GPIO | PIN_INPUT_PULLDOWN, /* NC */
GPIO226_GPIO | PIN_INPUT_PULLDOWN, /* VGA_CAM_ID */
GPIO227_GPIO | PIN_INPUT_PULLDOWN, /* NC */
GPIO228_GPIO | PIN_OUTPUT_LOW, /* CAM_MCLK */
GPIO229_GPIO | PIN_INPUT_PULLDOWN, /* TSP_SDA_1V8 */
GPIO230_GPIO | PIN_INPUT_PULLDOWN, /* TSP_SCL_1V8 */
};
/* STM trace or SD Card pin configurations */
static pin_cfg_t kyle_ape_trace[] = {
GPIO22_GPIO | PIN_INPUT_NOPULL, /* CLK-f */
PIN_CFG(23, ALT_C), /* APE CLK */
PIN_CFG(25, ALT_C), /* APE DAT0 */
PIN_CFG(26, ALT_C), /* APE DAT1 */
PIN_CFG(27, ALT_C), /* APE DAT2 */
PIN_CFG(28, ALT_C), /* APE DAT3 */
};
static pin_cfg_t kyle_modem_trace[] = {
GPIO22_GPIO | PIN_INPUT_NOPULL, /* CLK-f */
GPIO23_STMMOD_CLK | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM CLK */
GPIO24_UARTMOD_RXD | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM UART RXD */
GPIO25_STMMOD_DAT0 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
GPIO26_STMMOD_DAT1 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
GPIO27_STMMOD_DAT2 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
GPIO28_STMMOD_DAT3 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
/* Enable Evatronix 'patch'. Set GPIO59 and GPIO63 */
gpio_set_value(59, 1);
gpio_set_value(63, 1);
return 0;
}
#else /* #if defined(CONFIG_MACH_CAPRI_FPGA) */
static int bcm_usbh_hsic_init(struct usbh_cfg *hw_cfg)
{
int ret;
struct usbh_hsic_priv *drv_hsic_data = &usbh_hsic_data;
int retries;
uint32_t tmp;
int i;
#if defined(HSIC_TEST)
for (i = 0; i < hw_cfg->num_ports; i++) {
struct usbh_port_cfg *port = &hw_cfg->port[i];
dbg_printk("%s: HSIC.%d - reset_gpio=%d\n",
__func__, i, port->reset_gpio);
if (port->reset_gpio >= 0) {
/* Enable second port and setup pinmux. */
gpio_free(port->reset_gpio);
if (i == 1) {
struct pin_config pin_cfg =
PIN_CFG(SRI_E, GPIO_032,
0, ON, OFF, 0, 0, 8MA);
/* Configure GPIO04 for port1
* power & enable MIC2015
*/
pinmux_set_pin_config(&pin_cfg);
}
ret = gpio_request(port->reset_gpio,
"HSIC reset");
if (ret < 0) {
dbg_printk("GPIO%d request failed\n",
port->reset_gpio);
goto err_hsic_init_cleanup;
}
gpio_direction_output(port->reset_gpio, 0);
}
}
#endif /* #if defined(CONFIG_MACH_CAPRI_FPGA) */
/* Enable 48MHz reference clock to PHY */
tmp = readl(&drv_hsic_data->ctrl_regs->clkrst_ctrl);
writel(tmp | HSIC_PHY_CLKRST_CTRL_CLK48_REQ_MASK,
&drv_hsic_data->ctrl_regs->clkrst_ctrl);
dbg_printk("Change PHY Clock & Reset Control from 0x%08x to 0x%08x\n",
tmp, readl(&drv_hsic_data->ctrl_regs->clkrst_ctrl));
/* Enable LDO */
tmp = readl(&drv_hsic_data->ctrl_regs->hsic_ldo_ctrl);
writel(tmp | HSIC_PHY_HSIC_LDO_CTRL_LDO_EN_MASK,
&drv_hsic_data->ctrl_regs->hsic_ldo_ctrl);
dbg_printk("Change PHY AFE Control from 0x%08x to 0x%08x\n",
tmp, readl(&drv_hsic_data->ctrl_regs->hsic_ldo_ctrl));
mdelay(1);
/* Deassert power downs */
tmp = readl(&drv_hsic_data->ctrl_regs->hsic_phy_ctrl);
writel(tmp | HSIC_PHY_HSIC_PHY_CTRL_UTMI_PWRDNB_MASK |
HSIC_PHY_HSIC_PHY_CTRL_PHY_PWRDNB_MASK,
&drv_hsic_data->ctrl_regs->hsic_phy_ctrl);
dbg_printk("Change HSIC PHY Control from 0x%08x to 0x%08x\n", tmp,
readl(&drv_hsic_data->ctrl_regs->hsic_phy_ctrl));
mdelay(1);
/* Deassert PLL power down */
tmp = readl(&drv_hsic_data->ctrl_regs->hsic_pll_ctrl);
writel(tmp | HSIC_PHY_HSIC_PLL_CTRL_PLL_POWERDOWNB_MASK,
&drv_hsic_data->ctrl_regs->hsic_pll_ctrl);
dbg_printk("Change HSIC PLL Control from 0x%08x to 0x%08x\n",
tmp, readl(&drv_hsic_data->ctrl_regs->hsic_pll_ctrl));
/* Deassert ISO */
tmp = readl(&drv_hsic_data->ctrl_regs->hsic_phy_ctrl);
writel(tmp & ~HSIC_PHY_HSIC_PHY_CTRL_PHY_ISO_MASK,
&drv_hsic_data->ctrl_regs->hsic_phy_ctrl);
dbg_printk("Change HSIC PHY Control from 0x%08x to 0x%08x\n",
tmp, readl(&drv_hsic_data->ctrl_regs->hsic_phy_ctrl));
mdelay(1);
/* Pull PHY out of reset */
tmp = readl(&drv_hsic_data->ctrl_regs->hsic_phy_ctrl);
writel(tmp | HSIC_PHY_HSIC_PHY_CTRL_RESETB_MASK,
&drv_hsic_data->ctrl_regs->hsic_phy_ctrl);
dbg_printk("Change HSIC PHY Control from 0x%08x to 0x%08x\n",
tmp, readl(&drv_hsic_data->ctrl_regs->hsic_phy_ctrl));
/* Pull PLL out of reset */
tmp = readl(&drv_hsic_data->ctrl_regs->hsic_pll_ctrl);
writel(tmp & ~HSIC_PHY_HSIC_PLL_CTRL_PLL_RESET_MASK,
&drv_hsic_data->ctrl_regs->hsic_pll_ctrl);
dbg_printk("Change HSIC PLL Control from 0x%08x to 0x%08x\n",
tmp, readl(&drv_hsic_data->ctrl_regs->hsic_pll_ctrl));
/* Wait for PLL lock */
retries = 100;
while ((!(readl(&drv_hsic_data->ctrl_regs->hsic_pll_ctrl) &
HSIC_PHY_HSIC_PLL_CTRL_PLL_LOCK_MASK)) && retries--) {
schedule_timeout_interruptible(HZ / 1000);
}
if (retries == 0)
dbg_printk("ERROR: HSIC PLL Lock failed!\n");
/* Deassert software reset for UTMI and port */
tmp = readl(&drv_hsic_data->ctrl_regs->clkrst_ctrl);
writel(tmp |
HSIC_PHY_CLKRST_CTRL_UTMIRESETN_SW_MASK |
HSIC_PHY_CLKRST_CTRL_RESETN_SW_MASK,
&drv_hsic_data->ctrl_regs->clkrst_ctrl);
dbg_printk("Change HSIC Clock Reset Control from 0x%08x to 0x%08x\n",
tmp, readl(&drv_hsic_data->ctrl_regs->clkrst_ctrl));
/* Deassert soft resets to the PHY */
tmp = readl(&drv_hsic_data->ctrl_regs->hsic_phy_ctrl);
writel((tmp | HSIC_PHY_HSIC_PHY_CTRL_SOFT_RESETB_MASK) &
~HSIC_PHY_HSIC_PHY_CTRL_NON_DRIVING_MASK,
&drv_hsic_data->ctrl_regs->hsic_phy_ctrl);
dbg_printk("Change HSIC PHY Control from 0x%08x to 0x%08x\n",
tmp, readl(&drv_hsic_data->ctrl_regs->hsic_phy_ctrl));
#if defined(HSIC_TEST)
for (i = 0; i < hw_cfg->num_ports; i++) {
struct usbh_port_cfg *port = &hw_cfg->port[i];
dbg_printk("%s: HSIC.%d - Pull out of reset. reset_gpio=%d\n",
__func__, i, port->reset_gpio);
if (port->reset_gpio >= 0)
gpio_set_value(port->reset_gpio, 1);
}
return 0;
err_hsic_init_cleanup:
for (; i >= 0; i--) {
struct usbh_port_cfg *port = &hw_cfg->port[i];
dbg_printk("%s: HSIC.%d - Free reset_gpio=%d\n",
__func__, i, port->reset_gpio);
if (port->reset_gpio >= 0)
gpio_free(port->reset_gpio);
}
#endif /* #if defined(HSIC_TEST) */
return 0;
}
static struct __init pin_config board_pin_config[] = {
/* BSC1 */
PIN_BSC_CFG(BSC1CLK, BSC1CLK, 0x20),
PIN_BSC_CFG(BSC1DAT, BSC1DAT, 0x20),
/* BSC2 */
PIN_BSC_CFG(GPIO16, BSC2CLK, 0x20),
PIN_BSC_CFG(GPIO17, BSC2DAT, 0x20),
/* PMU BSC */
PIN_BSC_CFG(PMBSCCLK, PMBSCCLK, 0x20),
PIN_BSC_CFG(PMBSCDAT, PMBSCDAT, 0x20),
/* eMMC */
PIN_CFG(MMC0CK, MMC0CK, 0, OFF, OFF, 0, 0, 8MA),
PIN_CFG(MMC0CMD, MMC0CMD, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(MMC0RST, MMC0RST, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(MMC0DAT7, MMC0DAT7, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(MMC0DAT6, MMC0DAT6, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(MMC0DAT5, MMC0DAT5, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(MMC0DAT4, MMC0DAT4, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(MMC0DAT3, MMC0DAT3, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(MMC0DAT2, MMC0DAT2, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(MMC0DAT1, MMC0DAT1, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(MMC0DAT0, MMC0DAT0, 0, OFF, ON, 0, 0, 8MA),
/* Micro SD */
PIN_CFG(SDCK, SDCK, 0, OFF, OFF, 0, 0, 8MA),
PIN_CFG(SDCMD, SDCMD, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(SDDAT3, SDDAT3, 0, OFF, ON, 0, 0, 8MA),
GPIO262_USB_DAT5,
GPIO263_USB_DAT4,
GPIO264_USB_DAT3,
GPIO265_USB_DAT2,
GPIO266_USB_DAT1,
GPIO267_USB_DAT0,
};
/* STM trace or SD Card pin configurations */
static pin_cfg_t gti9060_r0_1_ape_trace[] = {
GPIO18_GPIO | PIN_OUTPUT_LOW, /* CMD.Dir */
GPIO19_GPIO | PIN_OUTPUT_HIGH, /* DAT0.Dir */
GPIO20_GPIO | PIN_OUTPUT_HIGH, /* DAT123.Dir */
GPIO22_GPIO | PIN_INPUT_NOPULL, /* CLK-f */
PIN_CFG(23, ALT_C), /* APE CLK */
PIN_CFG(25, ALT_C), /* APE DAT0 */
PIN_CFG(26, ALT_C), /* APE DAT1 */
PIN_CFG(27, ALT_C), /* APE DAT2 */
PIN_CFG(28, ALT_C), /* APE DAT3 */
};
static pin_cfg_t gti9060_r0_1_modem_trace[] = {
GPIO18_GPIO | PIN_OUTPUT_LOW, /* CMD.Dir */
GPIO19_GPIO | PIN_OUTPUT_HIGH, /* DAT0.Dir */
GPIO20_GPIO | PIN_OUTPUT_HIGH, /* DAT123.Dir */
GPIO22_GPIO | PIN_INPUT_NOPULL, /* CLK-f */
GPIO23_STMMOD_CLK | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM CLK */
GPIO24_UARTMOD_RXD | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM UART RXD */
GPIO25_STMMOD_DAT0 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
GPIO26_STMMOD_DAT1 | PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP, /* STM DAT0 */
/* PMU BSC */
PIN_BSC_CFG(PMBSCCLK, PMBSCCLK, 0x20),
PIN_BSC_CFG(PMBSCDAT, PMBSCDAT, 0x20),
/*
* Note:- For eMMC, Enable Slew-rate, Increase pin drive strength to 10mA.
* This is to fix the random eMMC timeout errors due to data crc error
* seen on few rhea edn11 hardware, where eMMC is on a daughter-card.
*
* We may need to revisit these settings for other platforms where the
* pin drive requirements can change.
*
*/
/* eMMC */
PIN_CFG(MMC0CK, MMC0CK, 0, OFF, OFF, 1, 0, 10MA),
PIN_CFG(MMC0CMD, MMC0CMD, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0RST, MMC0RST, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT7, MMC0DAT7, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT6, MMC0DAT6, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT5, MMC0DAT5, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT4, MMC0DAT4, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT3, MMC0DAT3, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT2, MMC0DAT2, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT1, MMC0DAT1, 0, OFF, ON, 1, 0, 10MA),
PIN_CFG(MMC0DAT0, MMC0DAT0, 0, OFF, ON, 1, 0, 10MA),
/* Micro SD - SDIO0 4 bit interface */
PIN_CFG(SDCK, SDCK, 0, OFF, OFF, 0, 0, 8MA),
PIN_CFG(SDCMD, SDCMD, 0, OFF, ON, 0, 0, 8MA),
PIN_CFG(SDDAT3, SDDAT3, 0, OFF, ON, 0, 0, 8MA),
