/*------------------------------------------------------------------------------*/
void sdramc_hw_init(void)
{
/*
* Configure PIOs
*/
/* const struct pio_desc sdramc_pio[] = {
{"D16", AT91C_PIN_PC(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D17", AT91C_PIN_PC(17), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D18", AT91C_PIN_PC(18), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D19", AT91C_PIN_PC(19), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D20", AT91C_PIN_PC(20), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D21", AT91C_PIN_PC(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D22", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D23", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D24", AT91C_PIN_PC(24), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D25", AT91C_PIN_PC(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D26", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D27", AT91C_PIN_PC(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D28", AT91C_PIN_PC(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D29", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D30", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D31", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
*/
/*
* Configure the SDRAMC PIO controller to output PCK0
*/
/* pio_setup(sdramc_pio); */
writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
}
static void sdramc_init(void)
{
struct sdramc_register sdramc_config;
sdramc_config.cr = AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7
| AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2
| AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8;
sdramc_config.tr = (MASTER_CLOCK * 7) / 1000000;
sdramc_config.mdr = AT91C_SDRAMC_MD_SDRAM;
/* configure sdramc pins */
writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
writel((1 << AT91C_ID_PIOC), (PMC_PCER + AT91C_BASE_PMC));
/* Initialize the matrix (memory voltage = 3.3) */
writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC,
AT91C_BASE_CCFG + CCFG_EBICSA);
sdramc_initialize(&sdramc_config, AT91C_BASE_CS1);
}
void at91_spi0_hw_init(void)
{
/* Configure the spi0 pins */
/* {"MISO", AT91C_PIN_PA(0), 0, PIO_DEFAULT, PIO_PERIPH_A}
{"MOSI", AT91C_PIN_PA(1), 0, PIO_DEFAULT, PIO_PERIPH_A}
{"SPCK", AT91C_PIN_PA(2), 0, PIO_DEFAULT, PIO_PERIPH_A}*/
writel(((0x01 << 0) | (0x01 << 1) | (0x01 << 2)), AT91C_BASE_PIOA + PIO_ASR(0));
writel(((0x01 << 0) | (0x01 << 1) | (0x01 << 2)), AT91C_BASE_PIOA + PIO_PDR(0));
#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
/* {"NPCS", AT91C_PIN_PA(3), 1, PIO_PULLUP, PIO_OUTPUT}, */
writel((0x01 << 3), AT91C_BASE_PIOA + PIO_IDR(0));
writel((0x01 << 3), AT91C_BASE_PIOA + PIO_PPUDR(0));
writel((0x01 << 3), AT91C_BASE_PIOA + PIO_SODR(0));
writel((0x01 << 3), AT91C_BASE_PIOA + PIO_OER(0));
writel((0x01 << 3), AT91C_BASE_PIOA + PIO_PER(0));
writel((1 << AT91C_ID_PIOA), (PMC_PCER + AT91C_BASE_PMC));
#endif
#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
/* {"NPCS", AT91C_PIN_PC(11), 1, PIO_PULLUP, PIO_OUTPUT}, */
writel((0x01 << 11), AT91C_BASE_PIOC + PIO_IDR(0));
writel((0x01 << 11), AT91C_BASE_PIOC + PIO_PPUDR(0));
writel((0x01 << 11), AT91C_BASE_PIOC + PIO_SODR(0));
writel((0x01 << 11), AT91C_BASE_PIOC + PIO_OER(0));
writel((0x01 << 11), AT91C_BASE_PIOC + PIO_PER(0));
writel(((1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOC)), (PMC_PCER + AT91C_BASE_PMC));
#endif
/* Enable the spi0 clock */
writel((1 << AT91C_ID_SPI0), (PMC_PCER + AT91C_BASE_PMC));
}
static void initialize_dbgu(void)
{
/* Configure DBGU pin */
/* {"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A}, */
/* {"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A}, */
writel(((0x01 << 14) | (0x01 << 15)), AT91C_BASE_PIOB + PIO_ASR(0));
writel(((0x01 << 14) | (0x01 << 15)), AT91C_BASE_PIOB + PIO_PDR(0));
writel((1 << AT91C_ID_PIOB), (PMC_PCER + AT91C_BASE_PMC));
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
}
static void initialize_dbgu(void)
{
/* const struct pio_desc dbgu_pins[] = {
{"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
}; */
/* Configure the dbgu pins */
writel(((0x01 << 9) | (0x01 << 10)), AT91C_BASE_PIOA + PIO_ASR(0));
writel(((0x01 << 9) | (0x01 << 10)), AT91C_BASE_PIOA + PIO_PDR(0));
writel((1 << AT91C_ID_PIOA), (PMC_PCER + AT91C_BASE_PMC));
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
}
static void sdramc_init(void)
{
struct sdramc_register sdramc_config;
unsigned int reg;
#if defined(CONFIG_CPU_CLK_200MHZ)
sdramc_config.cr = AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7
| AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2
| AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8;
#endif
#if defined(CONFIG_CPU_CLK_266MHZ)
sdramc_config.cr = AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3
| AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_9
| AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3
| AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10;
#endif
sdramc_config.tr = (MASTER_CLOCK * 7) / 1000000;
sdramc_config.mdr = AT91C_SDRAMC_MD_SDRAM;
/* configure sdramc pins */
writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
writel((1 << AT91C_ID_PIOC), (PMC_PCER + AT91C_BASE_PMC));
/* Initialize the matrix (memory voltage = 3.3) */
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS1A_SDRAMC;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
sdramc_initialize(&sdramc_config, AT91C_BASE_CS1);
}