int main() { int fd; ssize_t size; char buf[128]; fd = open("in", O_RDWR); // contents: hellomaomao assert(fd >= 0); PLL(lseek(fd, 0, SEEK_CUR)); // 0 size = pread(fd, buf, 6, 1); // file pos is not changed! assert(size >= 0); PL(size); print_str(buf, 6); PLL(lseek(fd, 0, SEEK_CUR)); // still 0 size = read(fd, buf, 6); assert(size >= 0); PL(size); print_str(buf, 6); PLL(lseek(fd, 0, SEEK_CUR)); // 6 close(fd); return 0; }
//#pragma CODE_SECTION(AquisitaCanal_1, "ramfuncs"); void AquisitaCanal_1() { static float seno1 = 0, seno2 = 0; Uint16 tempTensao; Uint16 tempCorrente; //SpiA_ConversaoAD(valor_amostrado); tempTensao = SpiA_AquisicaoTensao(); tempCorrente = SpiA_AquisicaoCorrente(); corrente_pu = Const_ADC_corrente*((float)tempCorrente-Adc_offset[0]); //Vo=Vref/4096*(Vi-2047) tensao_pu = Const_ADC_tensao*((float)tempTensao-Adc_offset[1]); //Vo=Vref/4096*(Vi-2047) temp_dac = corrente_pu/Const_ADC_corrente + 2048; // McBsp_DAC(ii*4, 2); // if(ii++ > 360) ii = 0; // McBsp_DAC(tensao_pu*2048 + 2048, 3); // McBsp_DAC(corrente_pu*4096 + 2048, 2); /* //Aquisita Dados do ADC interno AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1; //Inicia conversao AD; while (AdcRegs.ADCST.bit.INT_SEQ1== 0) {} // Wait for interrup AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; //Fim aquisicao interna //tensao_pu = Const_ADC_tensao*((float)(AdcRegs.ADCRESULT0>>4)-ADC_OffSet); //Vo=Vref/4096*(Vi-2047) //corrente_pu = Const_ADC_corrente*((float)(AdcRegs.ADCRESULT0>>4)-ADC_OffSet); */ seno2 = PLL(tensao_pu); if( (seno2>=0 && seno1<0) || (seno2<=0 && seno1>0)) { DetecaoZeroPLL(); } seno1 = seno2; EPwm2Regs.CMPA.half.CMPA = (seno2 * HalfPerDAC_PWM) + HalfPerDAC_PWM; //debug, dac de tensao // EPwm3Regs.CMPA.half.CMPA = ((float)(corrente_pu/2.0) * 1150) + 1150; //debug, dac de tensao EPwm3Regs.CMPA.half.CMPA = ((float)(tensao_pu) * HalfPerDAC_PWM) + HalfPerDAC_PWM; //debug, dac de tensao Rms.Tensao.in = tensao_pu; Rms.Tensao.Calcular(&Rms.Tensao); if(Solda.soldar) { Rms.FaseA.in = corrente_pu; Temp = Rms.FaseA.Calcular(&Rms.FaseA); // portA->GPIO23 = 0; //Inicia conversao // SpiA_DAC(Temp*100); // portA->GPIO23 = 1; //Termina conversao } MaquinaEstadoDetecaoRogowiski(tempCorrente); }
/** @see TUNER_FP_SET_RF_FREQ_HZ */ int e4000_SetRfFreqHz( TUNER_MODULE *pTuner, unsigned long RfFreqHz ) { E4000_EXTRA_MODULE *pExtra; int RfFreqKhz; int CrystalFreqKhz; // Get tuner extra module. pExtra = &(pTuner->Extra.E4000); // Set tuner RF frequency in KHz. // Note: 1. RfFreqKhz = round(RfFreqHz / 1000) // CrystalFreqKhz = round(CrystalFreqHz / 1000) // 2. Call E4000 source code functions. RfFreqKhz = (int)((RfFreqHz + 500) / 1000); CrystalFreqKhz = (int)((pExtra->CrystalFreqHz + 500) / 1000); if(Gainmanual(pTuner) != E4000_1_SUCCESS) goto error_status_execute_function; if(E4000_gain_freq(pTuner, RfFreqKhz) != E4000_1_SUCCESS) goto error_status_execute_function; if(PLL(pTuner, CrystalFreqKhz, RfFreqKhz) != E4000_1_SUCCESS) goto error_status_execute_function; if(LNAfilter(pTuner, RfFreqKhz) != E4000_1_SUCCESS) goto error_status_execute_function; if(freqband(pTuner, RfFreqKhz) != E4000_1_SUCCESS) goto error_status_execute_function; if(DCoffLUT(pTuner) != E4000_1_SUCCESS) goto error_status_execute_function; if(GainControlauto(pTuner) != E4000_1_SUCCESS) goto error_status_execute_function; // Set tuner RF frequency parameter. pTuner->RfFreqHz = RfFreqHz; pTuner->IsRfFreqHzSet = YES; return FUNCTION_SUCCESS; error_status_execute_function: return FUNCTION_ERROR; }
/** * @function readAndStore_PLL */ bool Tensor3D::readAndStore_PLL( std::fstream &_wstream ) { std::vector<Eigen::VectorXd> PLL(3); Eigen::VectorXd p(3); Eigen::VectorXd l(3); _wstream >> p(0); _wstream >> p(1); p(2) = 1; PLL[0] = p; _wstream >> l(0); _wstream >> l(1); _wstream >> l(2); PLL[1] = l; _wstream >> l(0); _wstream >> l(1); _wstream >> l(2); PLL[2] = l; mPLL.push_back( PLL ); return true; }
#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \ _pcw_reg, _pcw_shift, _div_rate) \ [_id] = { \ .reg = (void *)APMIXED_REG(_reg), \ .pwr_reg = (void *)APMIXED_REG(_pwr_reg), \ .rstb = _rstb, \ .pcwbits = _pcwbits, \ .div_reg = (void *)APMIXED_REG(_div_reg), \ .div_shift = _div_shift, \ .pcw_reg = (void *)APMIXED_REG(_pcw_reg), \ .pcw_shift = _pcw_shift, \ .div_rate = _div_rate, \ } static const struct pll plls[] = { PLL(APMIXED_ARMCA15PLL, armca15pll_con0, armca15pll_pwr_con0, 0, 21, armca15pll_con1, 24, armca15pll_con1, 0, pll_div_rate), PLL(APMIXED_ARMCA7PLL, armca7pll_con0, armca7pll_pwr_con0, PLL_RSTB, 21, armca7pll_con1, 24, armca7pll_con1, 0, pll_div_rate), PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0, PLL_RSTB, 21, mainpll_con0, 4, mainpll_con1, 0, pll_div_rate), PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0, PLL_RSTB, 7, univpll_con0, 4, univpll_con1, 14, univpll_div_rate), PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0, 0, 21, mmpll_con1, 24, mmpll_con1, 0, mmpll_div_rate), PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0, 0, 21, msdcpll_con0, 4, msdcpll_con1, 0, pll_div_rate), PLL(APMIXED_VENCPLL, vencpll_con0, vencpll_pwr_con0, 0, 21, vencpll_con0, 4, vencpll_con1, 0, pll_div_rate), PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0, 0, 21, tvdpll_con0, 4, tvdpll_con1, 0, pll_div_rate), PLL(APMIXED_MPLL, mpll_con0, mpll_pwr_con0, 0, 21,
GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll", ENABLE_SCLK_TOPC1, 13, 0, 0), GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll", ENABLE_SCLK_TOPC1, 12, 0, 0), GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll", ENABLE_SCLK_TOPC1, 5, 0, 0), GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll", ENABLE_SCLK_TOPC1, 4, 0, 0), GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll", ENABLE_SCLK_TOPC1, 1, 0, 0), GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll", ENABLE_SCLK_TOPC1, 0, 0, 0), }; static struct samsung_pll_clock topc_pll_clks[] __initdata = { PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, BUS0_PLL_CON0, NULL), PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, CC_PLL_CON0, NULL), PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, BUS1_DPLL_CON0, NULL), PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, MFC_PLL_CON0, NULL), PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, AUD_PLL_CON0, pll1460x_24mhz_tbl), }; static struct samsung_cmu_info topc_cmu_info __initdata = { .pll_clks = topc_pll_clks, .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), .mux_clks = topc_mux_clks, .nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
static struct clk clk_srcs[] = { #define GATE(x) (((x)<<24) | CLK_FLG_GATE) #define CPCCR(x) (((x)<<24) | CLK_FLG_CPCCR) #define CGU(no) (((no)<<24) | CLK_FLG_CGU) #define PLL(no) (((no)<<24) | CLK_FLG_PLL) #define PARENT(P) (((CLK_ID_##P)<<16) | CLK_FLG_PARENT) #define DEF_CLK(N,FLAG) \ [CLK_ID_##N] = { .name = CLK_NAME_##N, .flags = FLAG, } [CLK_ID_EXT] = {.name = "noclk", 1}, DEF_CLK(EXT0, 0), DEF_CLK(EXT1, 0), DEF_CLK(OTGPHY, 0), [CLK_ID_PLL] = {.name = "noclk", 1}, DEF_CLK(APLL, PLL(0)), DEF_CLK(MPLL, PLL(0)), DEF_CLK(SCLKA, PARENT(APLL)), [CLK_ID_CPPCR] = {.name = "noclk", 1}, DEF_CLK(CCLK, CPCCR(0)), DEF_CLK(L2CLK, CPCCR(0)), DEF_CLK(H0CLK, CPCCR(H0DIV)), DEF_CLK(H2CLK, CPCCR(H2DIV)), DEF_CLK(PCLK, CPCCR(PDIV)), [CLK_ID_DEVICES] = {.name = "noclk", 1}, DEF_CLK(EFUSE, GATE(1) | PARENT(H2CLK)), DEF_CLK(OTG, GATE(3)), DEF_CLK(MSC0, GATE(4) | PARENT(CGU_MSC_MUX)), DEF_CLK(MSC1, GATE(5) | PARENT(CGU_MSC_MUX)),
}; static const struct mtk_gate_regs peri0_cg_regs = { .set_ofs = 0x8, .clr_ofs = 0x10, .sta_ofs = 0x18, }; static const struct mtk_gate_regs peri1_cg_regs = { .set_ofs = 0xC, .clr_ofs = 0x14, .sta_ofs = 0x1C, }; static const struct mtk_pll_data plls[] = { PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 21, 0x0204, 24, 0, 0x0204, 0), PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001, HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001, HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001, 0, 21, 0x0300, 1, 0, 0x0304, 0), PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001, 0, 21, 0x0314, 1, 0, 0x0318, 0), PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001, 0, 21, 0x0358, 1, 0, 0x035C, 0), }; static const struct mtk_gate apmixed_clks[] = { GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), };
ALIAS(HCLK_USBH, NULL, "usb-host"), ALIAS(SCLK_USBH, NULL, "usb-bus-host"), ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"), ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"), ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"), ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"), ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"), ALIAS(SCLK_I2S0, NULL, "i2s-if"), ALIAS(HCLK_LCD, NULL, "lcd"), ALIAS(SCLK_FIMD, NULL, "sclk_fimd"), }; /* S3C2416 specific clocks */ static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = { PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL), PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL), }; PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" }; PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" }; PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" }; static struct clk_div_table armdiv_s3c2416_d[] = { { .val = 0, .div = 1 }, { .val = 1, .div = 2 }, { .val = 2, .div = 3 }, { .val = 3, .div = 4 }, { .val = 5, .div = 6 }, { .val = 7, .div = 8 }, { /* sentinel */ },
.id = _id, \ .reg = _reg, \ .pwr_reg = _pwr_reg, \ .en_mask = _en_mask, \ .rst_bar_mask = MT7629_CON0_RST_BAR, \ .fmax = MT7629_PLL_FMAX, \ .flags = _flags, \ .pcwbits = _pcwbits, \ .pd_reg = _pd_reg, \ .pd_shift = _pd_shift, \ .pcw_reg = _pcw_reg, \ .pcw_shift = _pcw_shift, \ } static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, 21, 0x204, 24, 0x204, 0), PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, 21, 0x214, 24, 0x214, 0), PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, 7, 0x224, 24, 0x224, 14), PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, 21, 0x300, 1, 0x304, 0), PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0, 21, 0x314, 1, 0x318, 0), PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0, 21, 0x358, 1, 0x35c, 0), }; /* topckgen */ #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
.reg = _reg, \ .pwr_reg = _pwr_reg, \ .en_mask = _en_mask, \ .flags = _flags, \ .rst_bar_mask = CON0_MT8590_RST_BAR, \ .fmax = MT8590_PLL_FMAX, \ .pcwbits = _pcwbits, \ .pd_reg = _pd_reg, \ .pd_shift = _pd_shift, \ .tuner_reg = _tuner_reg, \ .pcw_reg = _pcw_reg, \ .pcw_shift = _pcw_shift, \ } static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001, PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0), PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0), PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14), PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0, 21, 0x230, 4, 0x0, 0x234, 0), PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x240, 4, 0x0, 0x244, 0), PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0), PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0, 31, 0x270, 4, 0x0, 0x274, 0), PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0, 31, 0x280, 4, 0x0, 0x284, 0), PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
PLL_36XX_RATE(144000000, 96, 2, 3, 0), PLL_36XX_RATE(96000000, 128, 2, 4, 0), PLL_36XX_RATE(84000000, 112, 2, 4, 0), PLL_36XX_RATE(80750011, 107, 2, 4, 43691), PLL_36XX_RATE(73728004, 98, 2, 4, 19923), PLL_36XX_RATE(67987602, 271, 3, 5, 62285), PLL_36XX_RATE(65911004, 175, 2, 5, 49982), PLL_36XX_RATE(50000000, 200, 3, 5, 0), PLL_36XX_RATE(49152003, 131, 2, 5, 4719), PLL_36XX_RATE(48000000, 128, 2, 5, 0), PLL_36XX_RATE(45250000, 181, 3, 5, 0), { /* sentinel */ } }; static struct samsung_pll_clock exynos4415_plls[] __initdata = { PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, exynos4415_pll_rates), PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, EPLL_CON0, exynos4415_epll_rates), PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, exynos4415_pll_rates), PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll", ISP_PLL_LOCK, ISP_PLL_CON0, exynos4415_pll_rates), PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates), }; static struct samsung_cmu_info cmu_info __initdata = { .pll_clks = exynos4415_plls, .nr_pll_clks = ARRAY_SIZE(exynos4415_plls), .mux_clks = exynos4415_mux_clks, .nr_mux_clks = ARRAY_SIZE(exynos4415_mux_clks),
#define GATE(x) (((x)<<24) | CLK_FLG_GATE) #define CPCCR(x) (((x)<<24) | CLK_FLG_CPCCR) #define CGU(no) (((no)<<24) | CLK_FLG_CGU) #define CGU_AUDIO(no) (((no)<<24) | CLK_FLG_CGU_AUDIO) #define TCU_WDT(no) (((no)<<24) | CLK_FLG_WDT) #define PLL(no) (((no)<<24) | CLK_FLG_PLL) #define PARENT(P) (((CLK_ID_##P)<<16) | CLK_FLG_PARENT) #define RELATIVE(P) (((CLK_ID_##P)<<16) | CLK_FLG_RELATIVE) #define DEF_CLK(N,FLAG) \ [CLK_ID_##N] = { .name = CLK_NAME_##N, .flags = FLAG, } DEF_CLK(EXT0, CLK_FLG_NOALLOC), DEF_CLK(EXT1, CLK_FLG_NOALLOC), DEF_CLK(OTGPHY, CLK_FLG_NOALLOC), DEF_CLK(APLL, PLL(CPM_CPAPCR)), DEF_CLK(MPLL, PLL(CPM_CPMPCR)), DEF_CLK(SCLKA, CPCCR(SCLKA)), DEF_CLK(CCLK, CPCCR(CDIV)), DEF_CLK(L2CLK, CPCCR(L2CDIV)), DEF_CLK(H0CLK, CPCCR(H0DIV)), DEF_CLK(H2CLK, CPCCR(H2DIV)), DEF_CLK(PCLK, CPCCR(PDIV)), DEF_CLK(NEMC, GATE(0) | PARENT(H2CLK)), DEF_CLK(EFUSE, GATE(1) | PARENT(H2CLK)), DEF_CLK(SFC, GATE(2) | PARENT(CGU_SFC)), DEF_CLK(OTG, GATE(3)), DEF_CLK(MSC0, GATE(4) | PARENT(PCLK)), DEF_CLK(MSC1, GATE(5) | PARENT(PCLK)),
PLL_36XX_RATE(275000000, 275, 3, 3, 0), PLL_36XX_RATE(222750000, 148, 2, 3, 32768), PLL_36XX_RATE(222528007, 148, 2, 3, 23069), PLL_36XX_RATE(160000000, 160, 3, 3, 0), PLL_36XX_RATE(148500000, 99, 2, 3, 0), PLL_36XX_RATE(148352005, 98, 2, 3, 59070), PLL_36XX_RATE(108000000, 144, 2, 4, 0), PLL_36XX_RATE( 74250000, 99, 2, 4, 0), PLL_36XX_RATE( 74176002, 98, 3, 4, 59070), PLL_36XX_RATE( 54054000, 216, 3, 5, 14156), PLL_36XX_RATE( 54000000, 144, 2, 5, 0), { /* sentinel */ } }; static const struct samsung_pll_clock exynos3250_plls[] __initconst = { PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, exynos3250_pll_rates), PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates), PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates), PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll", UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates), }; static void __init exynos3_core_down_clock(void __iomem *reg_base) { unsigned int tmp; /* * Enable arm clock down (in idle) and set arm divider * ratios in WFI/WFE state.
}; static const struct mtk_gate_regs peri0_cg_regs = { .set_ofs = 0x8, .clr_ofs = 0x10, .sta_ofs = 0x18, }; static const struct mtk_gate_regs peri1_cg_regs = { .set_ofs = 0xC, .clr_ofs = 0x14, .sta_ofs = 0x1C, }; static const struct mtk_pll_data plls[] = { PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0), PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001, HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001, HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001, 0, 21, 0x0300, 1, 0, 0x0304, 0), PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001, 0, 21, 0x0314, 1, 0, 0x0318, 0), PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001, 0, 31, 0x0324, 1, 0, 0x0328, 0), PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001, 0, 31, 0x0334, 1, 0, 0x0338, 0), PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001, 0, 21, 0x0344, 1, 0, 0x0348, 0), PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
}; static const struct composite_conf mali_conf __initconst = { .mux_table = mux_table_mali, .mux_parm = PARM(0x00, 9, 3), .div_parm = PARM(0x00, 0, 7), .gate_parm = PARM(0x00, 8, 1), }; static const struct clk_conf meson8b_xtal_conf __initconst = FIXED_RATE_P(MESON8B_REG_CTL0_ADDR, CLKID_XTAL, "xtal", 0, PARM(0x00, 4, 7)); static const struct clk_conf meson8b_clk_confs[] __initconst = { FIXED_RATE(CLKID_ZERO, "zero", 0, 0), PLL(MESON8B_REG_PLL_FIXED, CLKID_PLL_FIXED, "fixed_pll", p_xtal, 0, &pll_confs), PLL(MESON8B_REG_PLL_VID, CLKID_PLL_VID, "vid_pll", p_xtal, 0, &pll_confs), PLL(MESON8B_REG_PLL_SYS, CLKID_PLL_SYS, "sys_pll", p_xtal, 0, &sys_pll_conf), FIXED_FACTOR_DIV(CLKID_FCLK_DIV2, "fclk_div2", p_fclk_div, 0, 2), FIXED_FACTOR_DIV(CLKID_FCLK_DIV3, "fclk_div3", p_fclk_div, 0, 3), FIXED_FACTOR_DIV(CLKID_FCLK_DIV4, "fclk_div4", p_fclk_div, 0, 4), FIXED_FACTOR_DIV(CLKID_FCLK_DIV5, "fclk_div5", p_fclk_div, 0, 5), FIXED_FACTOR_DIV(CLKID_FCLK_DIV7, "fclk_div7", p_fclk_div, 0, 7), CPU(MESON8B_REG_SYS_CPU_CNTL1, CLKID_CPUCLK, "a5_clk", p_cpu_clk, cpu_div_table), COMPOSITE(MESON8B_REG_HHI_MPEG, CLKID_CLK81, "clk81", p_clk81, CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED, &clk81_conf), COMPOSITE(MESON8B_REG_MALI, CLKID_MALI, "mali", p_mali, CLK_IGNORE_UNUSED, &mali_conf),