/**
* \brief Configure clock for coprocessor.
*/
static void sysclk_configure_cpclk(void)
{
#if ((CONFIG_CPCLK_PRES < CPCLK_PRES_MIN) || (CONFIG_CPCLK_PRES > CPCLK_PRES_MAX))
#error Invalid CONFIG_CPCLK_PRES setting.
#endif
/* Assert coprocessor reset and reset its peripheral */
RSTC->RSTC_CPMR = RSTC_CPMR_CPKEY(0x5Au);
#ifdef CONFIG_PLL0_SOURCE
if ((CONFIG_CPCLK_SOURCE == CPCLK_SRC_PLLACK) &&
(pll_is_locked(0) == 0)) {
struct pll_config pllcfg;
pll_enable_source(CONFIG_PLL0_SOURCE);
pll_config_defaults(&pllcfg, 0);
pll_enable(&pllcfg, 0);
pll_wait_for_lock(0);
}
#endif
#ifdef CONFIG_PLL1_SOURCE
if ((CONFIG_CPCLK_SOURCE == CPCLK_SRC_PLLBCK) &&
(pll_is_locked(1) == 0)) {
struct pll_config pllcfg;
pll_enable_source(CONFIG_PLL1_SOURCE);
pll_config_defaults(&pllcfg, 1);
pll_enable(&pllcfg, 1);
pll_wait_for_lock(1);
}
#endif
uint32_t read_reg;
/* Enables Coprocessor Bus Master Clock */
PMC->PMC_SCER = PMC_SCER_CPBMCK | PMC_SCER_CPKEY_PASSWD;
/* Enables the Coprocessor Clocks */
PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
/* Set coprocessor clock prescaler and source */
read_reg = REG_PMC_MCKR;
read_reg &= ~PMC_MCKR_CPPRES_Msk;
read_reg |= PMC_MCKR_CPPRES(CONFIG_CPCLK_PRES - 1);
REG_PMC_MCKR = read_reg;
/* Choose coprocessor main clock source */
read_reg = REG_PMC_MCKR;
read_reg &= ~PMC_MCKR_CPCSS_Msk;
read_reg |= (CONFIG_CPCLK_SOURCE << PMC_MCKR_CPCSS_Pos);
REG_PMC_MCKR = read_reg;
/* Release coprocessor peripheral reset */
RSTC->RSTC_CPMR |= (RSTC_CPMR_CPKEY(0x5Au) | RSTC_CPMR_CPEREN);
/* Enable Core 1 SRAM1 and SRAM2 memories */
pmc_enable_periph_clk(42); /* ID_SRAM1_2 */
}
/**
* \brief Set the prescaler for the Coprocessor Master Clock.
*
* \param ul_pres Prescaler value.
*/
void pmc_cpck_set_prescaler(uint32_t ul_pres)
{
PMC->PMC_MCKR =
(PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres);
}
