//------------------------------------------------------------------------------
/// Selection of Master Clock.
/// \param clockSource Master Clock source.
/// \param mckr MCKR configuration instance.
///
/// \note
/// The PMC_MCKR register must not be programmed in a single write
/// operation (see. Product Data Sheet).
//------------------------------------------------------------------------------
void PMC_SetMckSelection(unsigned int clockSource, mckrConfiguration *mckr)
{
switch ( clockSource )
{
case AT91C_PMC_CSS_SLOW_CLK :
PMC_SwitchMck2SlowClock();
_PMC_SetMckPrescaler(mckr->prescaler);
break;
case AT91C_PMC_CSS_MAIN_CLK :
_PMC_SwitchMck2MainClock();
_PMC_SetMckPrescaler(mckr->prescaler);
break;
#if defined ( AT91C_PMC_CSS_PLLA_CLK)
case AT91C_PMC_CSS_PLLA_CLK :
_PMC_SetMckPrescaler(mckr->prescaler);
_PMC_SwitchMck2PllaClock(mckr);
break ;
#endif
#if defined ( AT91C_PMC_CSS_PLL_CLK)
case AT91C_PMC_CSS_PLL_CLK :
_PMC_SetMckPrescaler(mckr->prescaler);
_PMC_SwitchMck2PllaClock(mckr);
break ;
#endif
}
}
//------------------------------------------------------------------------------
/// Performs the low-level initialization of the chip.
//------------------------------------------------------------------------------
void LowLevelInit(unsigned int clockConfigEnable)
{
unsigned char i;
pllConfiguration pll;
mckrConfiguration mckr;
if (clockConfigEnable)
{
// Switch MCK to Slow clock
PMC_SwitchMck2SlowClock();
// enable Main oscillator
PMC_EnableMainOsc();
// Then, cofigure PLLA and switch clock
// MCK = 18.432MHz * 73 / 14 / 1 / 2 = 48MHz -> 0x10483F0E
pll.mul = 0x49; pll.div = 0x0E; pll.usbdiv = 0; pll.pllout = 0;
mckr.prescaler = AT91C_PMC_PRES_CLK; mckr.mdiv = AT91C_PMC_MDIV_2; mckr.plldiv2 = 0;
PMC_ConfigureMckWithPlla(&pll, &mckr);
}
/* Initialize AIC */
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) defaultFiqHandler;
for (i = 1; i < 31; i++) {
AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) defaultIrqHandler;
}
AT91C_BASE_AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler;
// Unstack nested interrupts
for (i = 0; i < 8 ; i++) {
AT91C_BASE_AIC->AIC_EOICR = 0;
}
// Enable Debug mode
//AT91C_BASE_AIC->AIC_DCR = AT91C_AIC_DCR_PROT;
/* Watchdog initialization
*************************/
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
/* Remap
*******/
BOARD_RemapRam();
// Disable RTT and PIT interrupts (potential problem when program A
// configures RTT, then program B wants to use PIT only, interrupts
// from the RTT will still occur since they both use AT91C_ID_SYS)
AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN);
AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
#if defined(norflash)
BOARD_ConfigureNorFlash(BOARD_NORFLASH_DFT_BUS_SIZE);
#endif
}
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Performs the low-level initialization of the chip. Initialisation depends
/// on where the application is executed:
/// - in sdram: it means that sdram has previously been initialized. No further
/// initialization is required.
/// - in sram: PLL shall be initialized in LowLevelInit. Other initializations
/// can be done later by the application.
/// - in norflash: LowLevelInit can't be executed in norflash because SMC
/// settings can't be changed while executing in external flash.
/// LowLevelInit shall be executed in internal sram. It initializes
/// PLL and SMC.
/// This function also reset the AIC and disable RTT and PIT interrupts
//------------------------------------------------------------------------------
void LowLevelInit(unsigned int clockConfigEnable)
{
unsigned char i;
pllConfiguration pll;
mckrConfiguration mckr;
if (clockConfigEnable)
{
// Switch MCK to Slow clock
PMC_SwitchMck2SlowClock();
// enable Main oscillator
PMC_EnableMainOsc();
// Then, cofigure PLLA and switch clock
// MCK = 18.432MHz * 73 / 14 / 1 / 2 = 48MHz -> 0x10483F0E
pll.mul = 0x49; pll.div = 0x0E; pll.usbdiv = 0; pll.pllout = 0;
mckr.prescaler = AT91C_PMC_PRES_CLK; mckr.mdiv = AT91C_PMC_MDIV_2; mckr.plldiv2 = 0;
PMC_ConfigureMckWithPlla(&pll, &mckr);
}
/* Initialize AIC
****************/
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) defaultFiqHandler;
for (i = 1; i < 31; i++) {
AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) defaultIrqHandler;
}
AT91C_BASE_AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler;
// Unstack nested interrupts
for (i = 0; i < 8 ; i++) {
AT91C_BASE_AIC->AIC_EOICR = 0;
}
/* Watchdog initialization
*************************/
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
/* Remap
*******/
BOARD_RemapRam();
#if defined(norflash)
BOARD_ConfigureNorFlash(BOARD_NORFLASH_DFT_BUS_SIZE);
#endif
}