void Setup_Pin_Func(GPIO_HANDLES * GPIO_HANDLE, uint32_t Function)
{
PORTS PORT = GPIO_HANDLE->PORT;
uint32_t Pin_Number = GPIO_HANDLE->Pin;
switch(PORT)
{
case PORTA:
PORT_PCR_REG(PORTA_BASE_PTR,Pin_Number) = PORT_PCR_MUX(Function);
break;
case PORTB:
PORT_PCR_REG(PORTB_BASE_PTR,Pin_Number) = PORT_PCR_MUX(Function);
break;
case PORTC:
PORT_PCR_REG(PORTC_BASE_PTR,Pin_Number) = PORT_PCR_MUX(Function);
break;
case PORTD:
PORT_PCR_REG(PORTD_BASE_PTR,Pin_Number) = PORT_PCR_MUX(Function);
break;
case PORTE:
PORT_PCR_REG(PORTE_BASE_PTR,Pin_Number) = PORT_PCR_MUX(Function);
break;
default:
break;
}
}
void Enable_ESC_Outputs()
{
PORT_PCR_REG(PORTC_BASE_PTR,1) = PORT_PCR_MUX(4);
PORT_PCR_REG(PORTC_BASE_PTR,2) = PORT_PCR_MUX(4);
PORT_PCR_REG(PORTC_BASE_PTR,3) = PORT_PCR_MUX(4);
PORT_PCR_REG(PORTC_BASE_PTR,4) = PORT_PCR_MUX(4);
}
//遥控引脚初始化
//PTA4，PTA5,PTA14,PTA15
//使能中断，中断服务函数在 PredatorCamera.c 中
void RemoteControlInit(void)
{
PORT_PCR_REG(PORTA_BASE_PTR, 4) = (0
| PORT_PCR_MUX(1)
| 0x0003 //输入下拉
|PORT_PCR_IRQC(0) //下降沿中断
);
//设置端口方向为输入
GPIO_PDDR_REG(PTA_BASE_PTR) &= ~(1 << 4);
PORT_PCR_REG(PORTA_BASE_PTR, 5) = (0
| PORT_PCR_MUX(1)
| 0x0003//输入下拉
|PORT_PCR_IRQC(0) //下降沿中断
);
//设置端口方向为输入
GPIO_PDDR_REG(PTA_BASE_PTR) &= ~(1 << 5);
PORT_PCR_REG(PORTA_BASE_PTR, 14) = (0
| PORT_PCR_MUX(1)
| 0x03 //输入下拉
|PORT_PCR_IRQC(0) //下降沿中断
);
//设置端口方向为输入
GPIO_PDDR_REG(PTA_BASE_PTR) &= ~(1 << 14);
PORT_PCR_REG(PORTA_BASE_PTR, 15) = (0
| PORT_PCR_MUX(1)
| 0x03 //输入下拉
|PORT_PCR_IRQC(0) //下降沿中断
);
//设置端口方向为输入
GPIO_PDDR_REG(PTA_BASE_PTR) &= ~(1 << 15);
}
//Beep引脚初始化
//PTB2初始输出高电平
//
void BeepInit(void)
{
//指定该引脚功能为GPIO功能（即令引脚控制寄存器的MUX=0b001）
PORT_PCR_REG(PORTB_BASE_PTR, 2)= 0 ;
PORT_PCR_REG(PORTB_BASE_PTR, 2)= PORT_PCR_MUX(1);
GPIO_PDDR_REG(PTB_BASE_PTR) |= (1 << 2); //设置端口方向为输出
GPIO_PDOR_REG(PTB_BASE_PTR) |= (1 << 2); //设置输出为高电平
}
/**
Function Name : GPIO_Init
Parameters : uint32_t port, uint8_t bit, uint32_t func
Returns : Nada
Notes : Esta función permite inicializar el pin indicado y enviar
los distintos parámetros de configuración haciendo una OR
entre ellos.
*/
void GPIO_Init(uint32_t port, uint8_t bit, uint32_t func)
{
switch (port)
{
case PORTA_BASE: PORT_PCR_REG(PORTA_BASE_PTR, bit) |= func; break;
case PORTB_BASE: PORT_PCR_REG(PORTB_BASE_PTR, bit) |= func; break;
}
}
void Pull_ESC_Outputs_Low()
{
PORT_PCR_REG(PORTC_BASE_PTR,4) = OUTPUT_EN;
PORT_PCR_REG(PORTC_BASE_PTR,3) = OUTPUT_EN;
PORT_PCR_REG(PORTC_BASE_PTR,2) = OUTPUT_EN;
PORT_PCR_REG(PORTC_BASE_PTR,1) = OUTPUT_EN;
GPIOC_PDDR |= (0x0F<<1);
GPIOC_PCOR = (0x0F<<1);
}
void portInitialise(PortConfigPtr config)
{
PORT_MemMapPtr port = config->port;
uint32_t mask = config->pcr_mask;
uint32_t set = config->pcr_bits;
for (int i = 0; i < config->pin_count; i++) {
PORT_PCR_REG(port, config->pins[i]) = (PORT_PCR_REG(port, config->pins[i]) & mask) | set;
}
}
//按键引脚初始化
//PTB8
//PTB18
void KeyInit(void)
{
//指定该引脚功能为GPIO功能（即令引脚控制寄存器的MUX=0b001）
PORT_PCR_REG(PORTB_BASE_PTR, 8)= 0 ;
PORT_PCR_REG(PORTB_BASE_PTR, 8)= PORT_PCR_MUX(1);
GPIO_PDDR_REG(PTB_BASE_PTR) &= ~(1 << 8); //设置端口方向为输入
//指定该引脚功能为GPIO功能（即令引脚控制寄存器的MUX=0b001）
PORT_PCR_REG(PORTB_BASE_PTR, 18)= 0 ;
PORT_PCR_REG(PORTB_BASE_PTR, 18)= PORT_PCR_MUX(1);
GPIO_PDDR_REG(PTB_BASE_PTR) &= ~(1 << 18); //设置端口方向为输入
}
/*!
* @brief PORT初始化
* @param PTxn 端口
* @param cfg 端口属性配置，如触发选项和上拉下拉选项
* @since v5.0
* @note 与port_init不同的是，此函数不需要配置 MUX 复用功能（即使配置了也不生效），
MUX 保留 为原先寄存器配置的值
* Sample usage: port_init_NoALT (PTA8, IRQ_RISING | PF | PULLUP ); //初始化 PTA8 管脚，上升沿触发中断，带无源滤波器，保留原先复用功能，上拉电阻
*/
void port_init_NoALT(PTXn_e ptxn, uint32 cfg)
{
SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK << PTX(ptxn)); //开启PORTx端口
PORT_ISFR_REG(PORTX_BASE(ptxn)) = (1<<PTn(ptxn)); // 清空标志位
//清空cfg里的MUX，加载寄存器里的MUX
cfg &= ~PORT_PCR_MUX_MASK; //清了MUX 字段（即不需要配置ALT，保持原来的ALT）
cfg |= (PORT_PCR_REG(PORTX_BASE(ptxn), PTn(ptxn)) & PORT_PCR_MUX_MASK); //读取寄存器里配置的 MUX
PORT_PCR_REG(PORTX_BASE(ptxn), PTn(ptxn)) = cfg; // 复用功能 , 确定触发模式 ,开启上拉或下拉电阻
}
//拨码开关初始化
//PTC1-4输入上拉 ，不允许中断
void SwitchInit(void)
{
//PTC0输入上拉 ，不允许中断
PORT_PCR_REG(PORTC_BASE_PTR,0) = (0 | PORT_PCR_MUX(1) | 0x03|PORT_PCR_IRQC(0) );
GPIO_PDDR_REG(PTC_BASE_PTR) &= ~(1 << 0); //设置端口方向为输入
//PTC1输入上拉 ，不允许中断
PORT_PCR_REG(PORTC_BASE_PTR,1) = (0 | PORT_PCR_MUX(1) | 0x03|PORT_PCR_IRQC(0) );
GPIO_PDDR_REG(PTC_BASE_PTR) &= ~(1 << 1); //设置端口方向为输入
//PTC2输入上拉 ，不允许中断
PORT_PCR_REG(PORTC_BASE_PTR,2) = (0 | PORT_PCR_MUX(1) | 0x03|PORT_PCR_IRQC(0) );
GPIO_PDDR_REG(PTC_BASE_PTR) &= ~(1 << 2); //设置端口方向为输入
//PTC3输入上拉 ，不允许中断
PORT_PCR_REG(PORTC_BASE_PTR,3) = (0 | PORT_PCR_MUX(1) | 0x03|PORT_PCR_IRQC(0) );
GPIO_PDDR_REG(PTC_BASE_PTR) &= ~(1 << 3); //设置端口方向为输入
}
/**
* @brief 使能所选引脚时钟，将其配置成PWM功能
*
* @param port_id： 所选引脚
*/
static void port_init(uint16_t port_id)
{
PORT_MemMapPtr portptr;
ID port,pin;
port = PORT_NO_GET(port_id);
pin = PIN_NO_GET(port_id);
portptr = get_portptr(port);
SIM_SCGC5 |= (1 << (port + 9));
if(port>=PORT_NO_GET(PTC))
PORT_PCR_REG(portptr,pin) = PORT_PCR_MUX(4);
else
PORT_PCR_REG(portptr,pin) = PORT_PCR_MUX(3);
}
/**
* Routine to configure the blue LED
*
* Note: This procedure does not enable the port clock
*/
void ledBlueConfig(void) {
/* Configure bit LED_BLUE_PORTA_BIT of PORTA to be a GPIO pin. */
PORT_PCR_REG(PORTA_BASE_PTR, LED_BLUE_PORTA_BIT) =
PORT_PCR_MUX(PORT_PCR_MUX_GPIO);
/* Configure bit LED_BLUE_PORTA_BIT of PORTA to be a GPIO output. */
PTA_BASE_PTR->PDDR |= 1<<LED_BLUE_PORTA_BIT;
}
/*************************************************************************
* 野火嵌入式开发工作室
*
* 函数名称：gpio_init
* 功能说明：初始化gpio
* 参数说明：PORTx 端口号（PORTA,PORTB,PORTC,PORTD,PORTE）
* n 端口引脚
* IO 引脚方向,0=输入,1=输出
* data 输出初始状态,0=低电平,1=高电平 （对输入无效）
* 函数返回：无
* 修改时间：2012-1-15 已测试
* 备 注：PDDR引脚方向寄存器 PCR引脚控制寄存器每个引脚都有这样的独立的一个寄存器
*************************************************************************/
void gpio_init (PORTx portx, u8 n, GPIO_CFG cfg, u8 data)
{
ASSERT( (n < 32u) && (data < 2u) ); //使用断言检查输入、电平 是否为1bit
//选择功能脚 PORTx_PCRx ，每个端口都有个寄存器 PORTx_PCRx
PORT_PCR_REG(PORTX[portx], n) = (0 | PORT_PCR_MUX(1) | cfg);
// 选择为GPIO功能 cfg为是否上下拉使能
//端口方向控制输入还是输出
if( ( (cfg & 0x01) == GPI) || (cfg == GPI_UP) || (cfg == GPI_UP_PF) )
// 最低位为0则输入 || 输入上拉模式 || 输入上拉，带无源滤波器
{
GPIO_PDDR_REG(GPIOx[portx]) &= ~(1 << n); //设置端口方向为输入
}
else
{
GPIO_PDDR_REG(GPIOx[portx]) |= (1 << n); //设置端口方向为输出
if(data == 1)//output
{
GPIO_SET(portx, n, 1); //对端口输出控制，输出为1
}
else
{
GPIO_SET(portx, n, 0); //对端口输出控制，输出为0
}
}
}
/*************************************************************************
* 蓝宙电子科技有限公司
*
* 函数名称：gpio_Interrupt_init
* 功能说明：初始化gpio
* 参数说明：PTxn 端口号（PORTA,PORTD）
* IO 引脚方向,0=输入,1=输出，输入输出状态定义____________(修改：这个函数中只有定义为输入模式有效，否则不改变相关状态)
* mode 中断模式
* 函数返回：无
* 修改时间：2012-9-15 已测试
* 备 注：
*************************************************************************/
void gpio_Interrupt_init(PTxn ptxn, GPIO_CFG cfg, GPIO_INP mode)
{
ASSERT( (PTn(ptxn) < 32u) ); //使用断言检查输入、电平 是否为1bit
//选择功能脚 PORTx_PCRx ，每个端口都有个寄存器 PORTx_PCRx
PORT_PCR_REG(PORTX_BASE(ptxn), PTn(ptxn)) = (0 | PORT_PCR_MUX(1) | cfg | PORT_PCR_IRQC(mode) );
//选择功能脚 PORTx_PCRx ，每个端口都有中断模型
// PORT_DFER_REG(PORTX_BASE(ptxn)) = PORT_DFER_DFE( 1<<PTn(ptxn));
//端口方向控制输入还是输出
if( ( (cfg & 0x01) == GPI) || (cfg == GPI_UP) || (cfg == GPI_UP_PF)
|| (cfg == GPI_DOWN) || (cfg == GPI_DOWN_PF) )
// 最低位为0则输入 || 输入上拉模式 || 输入上拉，带无源滤波器
{
GPIO_PDDR_REG(GPIOX_BASE(ptxn)) &= ~(1 << PTn(ptxn)); //设置端口方向为输入
}
if(PTX(ptxn)==0)
enable_irq(PortA_irq_no);
else if(PTX(ptxn)==3)
enable_irq(PortD_irq_no);
}
/*!
* @brief PORT初始化
* @param PTxn 端口
* @param cfg 端口属性配置，如触发选项和上拉下拉选项
* @since v5.0
* @note 与port_init_NoALT不同的是，此函数需要配置 MUX 复用功能，
否则 MUX = ALT0
* Sample usage: port_init (PTA8, IRQ_RISING | PF | ALT1 | PULLUP ); //初始化 PTA8 管脚，上升沿触发中断，带无源滤波器，复用功能为GPIO ，上拉电阻
*/
void port_init(PTXn_e ptxn, uint32 cfg )
{
SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK << PTX(ptxn)); //开启PORTx端口
PORT_ISFR_REG(PORTX_BASE(ptxn)) = (1<<PTn(ptxn)); // 清空标志位
PORT_PCR_REG(PORTX_BASE(ptxn), PTn(ptxn)) = cfg; // 复用功能 , 确定触发模式 ,开启上拉或下拉电阻
}
_mqx_int _bsp_usb_io_init
(
void
)
{
#if PE_LDD_VERSION
/* USB clock is configured using CPU component */
/* Check if peripheral is not used by Processor Expert USB_LDD component */
if (PE_PeripheralUsed((uint32_t)USB0_BASE_PTR) == TRUE) {
/* IO Device used by PE Component*/
return IO_ERROR;
}
/**
* Workaround for Processor Expert as USB clock divider settings has been removed
* from __pe_initialize_hardware() and Cpu_SetClockConfiguration() functions
* Needs to be replaced by dynamic calculation of dividers.
* SIM_CLKDIV2: USBDIV=1,USBFRAC=0
*/
SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~0x0DUL) | (uint32_t)0x02UL); /* Update USB clock prescalers */
#endif
#if BSPCFG_USB_USE_IRC48M
/*
* Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0
*/
SIM_CLKDIV2 = (uint32_t)0x0UL; /* Update USB clock prescalers */
/* Configure USB to be clocked from IRC 48MHz */
SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(3);
/* Enable USB-OTG IP clocking */
SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK;
/* Enable IRC 48MHz for USB module */
USB0_CLK_RECOVER_IRC_EN = 0x03;
#else
/* Configure USB to be clocked from PLL */
SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(1);
/* Enable USB-OTG IP clocking */
SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK;
/* USB D+ and USB D- are standalone not multiplexed one-purpose pins */
/* VREFIN for device is standalone not multiplexed one-purpose pin */
#endif
#if BSP_USB_TWR_SER2
/* TWR-SER2 board has 2 connectors: on channel A, there is Micro-USB connector,
** which is not routed to TWRK64 board. On channel B, there is standard
** A-type host connector routed to the USB0 peripheral on TWRK64. To enable
** power to this connector, GPIO PB8 must be set as GPIO output
*/
PORT_PCR_REG(PORTB_BASE_PTR, 8) = PORT_PCR_MUX(0x01);
GPIO_PDDR_REG(PTB_BASE_PTR) |= 1 << 8; // PB8 as output
GPIO_PDOR_REG(PTB_BASE_PTR) |= 1 << 8; // PB8 in high level
#endif
return MQX_OK;
}
void DigitalEncoder::Initialize( FEHIO::FEHIOPin pin, FEHIO::FEHIOInterruptTrigger trigger )
{
// store selected pin number in class
_pin = pin;
unsigned char trig = (unsigned char)trigger;
switch( GPIOPorts[ (int)_pin ] )
{
case PortA:
{
PORT_PCR_REG( PORTA_BASE_PTR, GPIOPinNumbers[ (int)_pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_IRQC(trig) | PORT_PCR_PFE_MASK );
GPIOA_PDDR &= ~GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)_pin ] ) );
enable_irq(INT_PORTA);
break;
}
case PortB:
{
PORT_PCR_REG( PORTB_BASE_PTR, GPIOPinNumbers[ (int)_pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_IRQC(trig) | PORT_PCR_PFE_MASK );
GPIOB_PDDR &= ~GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)_pin ] ) );
enable_irq(INT_PORTB);
break;
}
case PortC:
{
PORT_PCR_REG( PORTC_BASE_PTR, GPIOPinNumbers[ (int)_pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_IRQC(trig) | PORT_PCR_PFE_MASK );
GPIOC_PDDR &= ~GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)_pin ] ) );
enable_irq(INT_PORTC);
break;
}
case PortD:
{
//Port D is already in use for power reset pin. Therefore Digital Encoders cannot be used on P3_6 and P3_7
//PORT_PCR_REG( PORTD_BASE_PTR, GPIOPinNumbers[ (int)_pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_IRQC(0xA) | PORT_PCR_PFE_MASK );
//GPIOD_PDDR &= ~GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)_pin ] ) );
//enable_irq(INT_PORTD);
break;
}
case PortE:
{
PORT_PCR_REG( PORTE_BASE_PTR, GPIOPinNumbers[ (int)_pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_IRQC(trig) | PORT_PCR_PFE_MASK );
GPIOE_PDDR &= ~GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)_pin ] ) );
enable_irq(INT_PORTE);
break;
}
}
}
/*FUNCTION*-------------------------------------------------------------------
*
* Function Name : _bsp_usb_otg_max3353_set_pin_int
* Returned Value : none
* Comments :
* This function enables/disables the pin interrupt associated with the max3353 interrupt pin
*
*END*----------------------------------------------------------------------*/
void _bsp_usb_otg_max3353_set_pin_int
(
bool level,
bool enable
)
{
#if (OS_ADAPTER_ACTIVE_OS == OS_ADAPTER_BM)
if (enable)
{
if (level)/* interrupt is triggered by low level */
{
HW_PORT_PCRn_WR(MAX_3353_INT_PORT,MAX3353_INT_PIN,0|PORT_PCR_MUX(1)|PORT_PCR_PE_MASK|PORT_PCR_PS_MASK|PORT_PCR_IRQC(0x08));
}
else/* interrupt is triggered by falling edge */
{
HW_PORT_PCRn_WR(MAX_3353_INT_PORT,MAX3353_INT_PIN,0|PORT_PCR_MUX(1)|PORT_PCR_PE_MASK|PORT_PCR_PS_MASK|PORT_PCR_IRQC(0x0A));
}
}
else
{
HW_PORT_PCRn_WR(MAX_3353_INT_PORT,MAX3353_INT_PIN,0|PORT_PCR_MUX(1)|PORT_PCR_PE_MASK|PORT_PCR_PS_MASK|PORT_PCR_IRQC(0x00));
}
#else
if (enable)
{
if (level)/* interrupt is triggered by low level */
{
PORT_PCR_REG(MAX_3353_INT_PORT,MAX3353_INT_PIN) |= 0|PORT_PCR_MUX(1)|PORT_PCR_PE_MASK|PORT_PCR_PS_MASK|PORT_PCR_IRQC(0x08);
}
else/* interrupt is triggered by falling edge */
{
PORT_PCR_REG(MAX_3353_INT_PORT,MAX3353_INT_PIN) |= 0|PORT_PCR_MUX(1)|PORT_PCR_PE_MASK|PORT_PCR_PS_MASK|PORT_PCR_IRQC(0x0A);
}
}
else
{
PORT_PCR_REG(MAX_3353_INT_PORT,MAX3353_INT_PIN) |= 0|PORT_PCR_MUX(1)|PORT_PCR_PE_MASK|PORT_PCR_PS_MASK|PORT_PCR_IRQC(0x00);
}
#endif
}
// Begin Functions for Digital Output Pin Type
DigitalOutputPin::DigitalOutputPin( FEHIO::FEHIOPin _pin )
{
// store selected pin number in class
pin = _pin;
switch( GPIOPorts[ (int)pin ] )
{
case PortA:
{
PORT_PCR_REG( PORTA_BASE_PTR, GPIOPinNumbers[ (int)pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) );
GPIOA_PDDR |= GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)pin ] ) );
break;
}
case PortB:
{
PORT_PCR_REG( PORTB_BASE_PTR, GPIOPinNumbers[ (int)pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) );
GPIOB_PDDR |= GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)pin ] ) );
break;
}
case PortC:
{
PORT_PCR_REG( PORTC_BASE_PTR, GPIOPinNumbers[ (int)pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) );
GPIOC_PDDR |= GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)pin ] ) );
break;
}
case PortD:
{
PORT_PCR_REG( PORTD_BASE_PTR, GPIOPinNumbers[ (int)pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) );
GPIOD_PDDR |= GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)pin ] ) );
break;
}
case PortE:
{
PORT_PCR_REG( PORTE_BASE_PTR, GPIOPinNumbers[ (int)pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) );
GPIOE_PDDR |= GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)pin ] ) );
break;
}
}
}
void DigitalInputPin::Initialize( FEHIO::FEHIOPin pin )
{
// store selected pin number in class
_pin = pin;
switch( GPIOPorts[ (int)_pin ] )
{
case PortA:
{
PORT_PCR_REG( PORTA_BASE_PTR, GPIOPinNumbers[ (int)_pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK );
GPIOA_PDDR &= ~GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)_pin ] ) );
break;
}
case PortB:
{
PORT_PCR_REG( PORTB_BASE_PTR, GPIOPinNumbers[ (int)_pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK );
GPIOB_PDDR &= ~GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)_pin ] ) );
break;
}
case PortC:
{
PORT_PCR_REG( PORTC_BASE_PTR, GPIOPinNumbers[ (int)_pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK );
GPIOC_PDDR &= ~GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)_pin ] ) );
break;
}
case PortD:
{
PORT_PCR_REG( PORTD_BASE_PTR, GPIOPinNumbers[ (int)_pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK );
GPIOD_PDDR &= ~GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)_pin ] ) );
break;
}
case PortE:
{
PORT_PCR_REG( PORTE_BASE_PTR, GPIOPinNumbers[ (int)_pin ] ) = ( 0 | PORT_PCR_MUX( 1 ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK );
GPIOE_PDDR &= ~GPIO_PDDR_PDD( GPIO_PIN( GPIOPinNumbers[ (int)_pin ] ) );
break;
}
}
}
/*************************************************************************
* 蓝宙电子工作室
*
* 函数名称：gpio_init
* 功能说明：初始化gpio
* 参数说明：port：端口号（gpio.h中宏定义，分别为PORTA~PORTE=0~4)
* dir：引脚方向（0=输入，1=输出）
* state：引脚初始状态（0=低电平，1=高电平）
* 函数返回：无
* 修改时间：2014-9-18 已测试
* 备 注：
*************************************************************************/
void gpio_init(PTxn ptxn, uint8_t dir, uint8_t state)
{
//根据带入参数pin,指定该引脚功能为GPIO功能（即令引脚控制寄存器的MUX=0b001）
PORT_PCR_REG(PORTX_BASE(ptxn), PTn(ptxn))= PORT_PCR_MUX(1);
//根据带入参数dir，决定引脚为输出还是输入
if (1 == dir) //希望为输出
{
GPIO_PDDR_REG(GPIOX_BASE(ptxn)) |= (1 << PTn(ptxn)); //设置端口方向为输出
gpio_set(ptxn , state); //调用gpio_set函数，设定引脚初始状态
}
else //希望为输入
GPIO_PDDR_REG(GPIOX_BASE(ptxn)) &= ~(1 << PTn(ptxn)); //设置端口方向为输入
}
void gpio_set_pin_mode(GPIO_MemMapPtr gpioMapPtr, uint8_t pin, uint8_t mode)
{
PORT_MemMapPtr portMapPtr;
if(gpioMapPtr == PTA)
{
portMapPtr = PORTA;
}else if(gpioMapPtr == PTB)
{
portMapPtr = PORTB;
}else if(gpioMapPtr == PTC)
{
portMapPtr = PORTC;
}else if(gpioMapPtr == PTD)
{
portMapPtr = PORTD;
}else if(gpioMapPtr == PTE)
{
portMapPtr = PORTE;
}
PORT_PCR_REG(portMapPtr, pin) |= PORT_PCR_MUX(0x01);
switch(mode)
{
case INPUT:
GPIO_PDDR_REG(gpioMapPtr) &= (~(1<<pin));
break;
case INPUT_PULLUP:
GPIO_PDDR_REG(gpioMapPtr) &= (~(1<<pin));
PORT_PCR_REG(portMapPtr, pin) |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK);
break;
case INPUT_PULLDWN:
GPIO_PDDR_REG(gpioMapPtr) &= (~(1<<pin));
PORT_PCR_REG(portMapPtr, pin) |= (PORT_PCR_PE_MASK);
PORT_PCR_REG(portMapPtr, pin) &= (~PORT_PCR_PS_MASK);
break;
case OUTPUT:
GPIO_PDDR_REG(gpioMapPtr) |= ((1<<pin));
break;
case OUTPUT_HIGH:
GPIO_PDDR_REG(gpioMapPtr) |= ((1<<pin));\
PORT_PCR_REG(portMapPtr, pin) |= PORT_PCR_DSE_MASK;
break;
case INPUT_PULLUP_INT:
GPIO_PDDR_REG(gpioMapPtr) &= (~(1<<pin));
PORT_PCR_REG(portMapPtr, pin) |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK | PORT_PCR_IRQC(0xA));
break;
default: break;
}
}
/**
* Routine to configure the orange LED
*
* Note: This procedure does not enable the port clock
*/
void ledOrangeConfig(void) {
/* Configure bit LED_ORANGE_PORTA_BIT of PORTA using the Pin Control Register
* (PORTA_PCR) to be a GPIO pin. This sets the MUX field (Pin Mux Control) to
* GPIO mode (Alternative 1). (See 11.4.1 on page 309 of the K70 Sub-Family
* Reference Manual, Rev. 2, Dec 2011) */
PORT_PCR_REG(PORTA_BASE_PTR, LED_ORANGE_PORTA_BIT) =
PORT_PCR_MUX(PORT_PCR_MUX_GPIO);
/* Above is equivalent to:
PORTA_PCR11 = PORT_PCR_MUX(PORT_PCR_MUX_GPIO);
* but uses my #define for the appropriate bit number.
*/
/* Configure bit LED_ORANGE_PORTA_BIT of PORTA using the Port Data Direction
* Register (GPIOx_PDDR) to be a GPIO output. (See 60.2.6 on page 2155 of the
* K70 Sub-Family Reference Manual, Rev. 2, Dec 2011) */
PTA_BASE_PTR->PDDR |= 1<<LED_ORANGE_PORTA_BIT;
}
_mqx_int _bsp_usb_io_init
(
void
)
{
#if PE_LDD_VERSION
/* USB clock is configured using CPU component */
/* Check if peripheral is not used by Processor Expert USB_LDD component */
if (PE_PeripheralUsed((uint32_t)USB0_BASE_PTR) == TRUE) {
/* IO Device used by PE Component*/
return IO_ERROR;
}
/**
* Workaround for Processor Expert as USB clock divider settings has been removed
* from __pe_initialize_hardware() and Cpu_SetClockConfiguration() functions
* Needs to be replaced by dynamic calculation of dividers.
* SIM_CLKDIV2: USBDIV=1,USBFRAC=0
*/
SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~0x0DUL) | (uint32_t)0x02UL); /* Update USB clock prescalers */
#endif
/* Configure USB to be clocked from PLL */
SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK;
/* Enable USB-OTG IP clocking */
SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK;
/* USB D+ and USB D- are standalone not multiplexed one-purpose pins */
/* VREFIN for device is standalone not multiplexed one-purpose pin */
/** If we need the USB working as a host we have to provide
** power to the USB connector. To do this PTC9 has to be set
** as a GPIO output in high level.
** If USB should work as a device, the J26 jumper should be removed.
*/
PORT_PCR_REG(PORTC_BASE_PTR, 9) = PORT_PCR_MUX(0x01) | PORT_PCR_PE_MASK;
GPIO_PDDR_REG(PTC_BASE_PTR) |= 0x00000200; // PTC9 as output
GPIO_PDOR_REG(PTC_BASE_PTR) |= 0x00000200; // PTC9 in high level
return MQX_OK;
}
_mqx_int _bsp_usb_host_io_init
(
struct usb_host_if_struct *dev_if
)
{
if (dev_if->HOST_INIT_PARAM == &_khci0_host_init_param)
{
_bsp_usb_io_init();
/* Set pin to enable power supply to on board usb conector */
PORT_PCR_REG(PORTC_BASE_PTR, 9) = PORT_PCR_MUX(0x01) | PORT_PCR_PE_MASK;
GPIO_PDDR_REG(PTC_BASE_PTR) |= 0x00000200; // PC9 as output
GPIO_PDOR_REG(PTC_BASE_PTR) |= 0x00000200; // PC9 in high level
}
else
{
return IO_ERROR; //unknown controller
}
return MQX_OK;
}
_mqx_int _bsp_usb_io_init
(
void
)
{
#if PE_LDD_VERSION
/* USB clock is configured using CPU component */
/* Check if peripheral is not used by Processor Expert USB_LDD component */
if (PE_PeripheralUsed((uint_32)USB0_BASE_PTR) == TRUE) {
/* IO Device used by PE Component*/
return IO_ERROR;
}
#endif
/* Configure USB to be clocked from PLL */
SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK;
/* Enable USB-OTG IP clocking */
SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK;
/* USB D+ and USB D- are standalone not multiplexed one-purpose pins */
/* VREFIN for device is standalone not multiplexed one-purpose pin */
#if BSP_USB_TWR_SER2
/* TWR-SER2 board has 2 connectors: on channel A, there is Micro-USB connector,
** which is not routed to TWRK60 board. On channel B, there is standard
** A-type host connector routed to the USB0 peripheral on TWRK60. To enable
** power to this connector, GPIO PB8 must be set as GPIO output
*/
PORT_PCR_REG(PORTB_BASE_PTR, 8) = PORT_PCR_MUX(0x01) | PORT_PCR_PE_MASK;
GPIO_PDDR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 as output
GPIO_PDOR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 in high level
#endif
return MQX_OK;
}
/*************************************************************************
* 野火嵌入式開發工作室
*
* 函數名稱：adc_init
* 功能說明：AD初始化，使能時鐘
* 參數說明：ADCn 模塊號（ ADC0、 ADC1）
* 函數返回：無
* 修改時間：2012-2-10
* 備 注：參考蘇州大學的例程
*************************************************************************/
void adc_init(ADCn adcn,ADC_Ch ch)
{
ASSERT( ((adcn == ADC0) && (ch>=AD8 && ch<=AD18)) || ((adcn == ADC1)&& (ch>=AD4a && ch<=AD17)) ) ; //使用斷言檢測ADCn_CHn是否正常
switch(adcn)
{
case ADC0: /* ADC0 */
SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK ); //開啟ADC0時鐘
SIM_SOPT7 &= ~(SIM_SOPT7_ADC0ALTTRGEN_MASK |SIM_SOPT7_ADC0PRETRGSEL_MASK);
SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0);
switch(ch)
{
case AD8: //ADC0_SE8 -- PTB0
case AD9: //ADC0_SE9 -- PTB1
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
PORT_PCR_REG(PORTB_BASE_PTR, ch-AD8+0) = PORT_PCR_MUX(0);
break;
case AD10: //ADC0_SE10 -- PTA7
case AD11: //ADC0_SE11 -- PTA8
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
PORT_PCR_REG(PORTA_BASE_PTR, ch-AD10+7) = PORT_PCR_MUX(0);
break;
case AD12: //ADC0_SE12 -- PTB2
case AD13: //ADC0_SE13 -- PTB3
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
PORT_PCR_REG(PORTB_BASE_PTR, ch-AD12+2) = PORT_PCR_MUX(0);
break;
case AD14: //ADC0_SE14 -- PTC0
case AD15: //ADC0_SE15 -- PTC1
SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;
PORT_PCR_REG(PORTC_BASE_PTR, ch-AD14+0) = PORT_PCR_MUX(0);
break;
case AD17: //ADC0_SE17 -- PTE24
case AD18: //ADC0_SE17 -- PTE25
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
PORT_PCR_REG(PORTE_BASE_PTR, ch-AD17+24) = PORT_PCR_MUX(0);
break;
default:
return;
}
return;
case ADC1: /* ADC1 */
SIM_SCGC3 |= (SIM_SCGC3_ADC1_MASK );
SIM_SOPT7 &= ~(SIM_SOPT7_ADC1ALTTRGEN_MASK |SIM_SOPT7_ADC1PRETRGSEL_MASK) ;
SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0);
switch(ch)
{
case AD4a: //ADC1_SE4a -- PTE0
case AD5a: //ADC1_SE5a -- PTE1
case AD6a: //ADC1_SE6a -- PTE2
case AD7a: //ADC1_SE7a -- PTE3
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
PORT_PCR_REG(PORTE_BASE_PTR, ch-AD4a+0) = PORT_PCR_MUX(0);
break;
case AD8: //ADC1_SE8 -- PTB0
case AD9: //ADC1_SE9 -- PTB1
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
PORT_PCR_REG(PORTB_BASE_PTR, ch-AD8+0) = PORT_PCR_MUX(0);
break;
case AD10: //ADC1_SE10 -- PTB4
case AD11: //ADC1_SE11 -- PTB5
case AD12: //ADC1_SE12 -- PTB6
case AD13: //ADC1_SE13 -- PTB7
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
PORT_PCR_REG(PORTB_BASE_PTR, ch-6) = PORT_PCR_MUX(0);
break;
case AD14: //ADC1_SE14 -- PTB10
case AD15: //ADC1_SE15 -- PTB11
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
PORT_PCR_REG(PORTB_BASE_PTR, ch-AD10+4) = PORT_PCR_MUX(0);
break;
case AD17: //ADC1_SE17 -- PTA17
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
PORT_PCR_REG(PORTA_BASE_PTR, ch) = PORT_PCR_MUX(0);
break;
default:
break;
}
break;
default:
break;
}
}
void Define_GPIO(PORTS PORT, bool Output, uint32_t Pin_Number)
{
GPIO_Enable_All_Ports();
switch(PORT)
{
case PORTA:
PORT_PCR_REG(PORTA_BASE_PTR,Pin_Number) = OUTPUT_EN;
if(Output)
{
GPIOA_PDDR |= (1<<Pin_Number);
}
else
{
GPIOA_PDDR &=~ (1<<Pin_Number);
}
break;
case PORTB:
PORT_PCR_REG(PORTB_BASE_PTR,Pin_Number) = OUTPUT_EN;
if(Output)
{
GPIOB_PDDR |= (1<<Pin_Number);
}
else
{
GPIOB_PDDR &=~ (1<<Pin_Number);
}
break;
case PORTC:
PORT_PCR_REG(PORTC_BASE_PTR,Pin_Number) = OUTPUT_EN;
if(Output)
{
GPIOC_PDDR |= (1<<Pin_Number);
}
else
{
GPIOC_PDDR &=~ (1<<Pin_Number);
}
break;
case PORTD:
PORT_PCR_REG(PORTD_BASE_PTR,Pin_Number) = OUTPUT_EN;
if(Output)
{
GPIOD_PDDR |= (1<<Pin_Number);
}
else
{
GPIOD_PDDR &=~ (1<<Pin_Number);
}
break;
case PORTE:
PORT_PCR_REG(PORTE_BASE_PTR,Pin_Number) = OUTPUT_EN;
if(Output)
{
GPIOE_PDDR |= (1<<Pin_Number);
}
else
{
GPIOE_PDDR &=~ (1<<Pin_Number);
}
break;
default:
break;
}
}
* $Date : Oct-4-2012$
*
* Comments:
*
* This file contains the GPIO standard functions used on boards
*
*END************************************************************************/
#include "mqx.h"
#include "bsp.h"
#include "lwgpio_vgpio.h"
#include "lwgpio.h"
const volatile uint32_t *pcr_reg_arr[] = {
&PORT_PCR_REG(PORT0_BASE_PTR, 0),
&PORT_PCR_REG(PORT1_BASE_PTR, 0),
&PORT_PCR_REG(PORT2_BASE_PTR, 0),
&PORT_PCR_REG(PORT3_BASE_PTR, 0),
&PORT_PCR_REG(PORT4_BASE_PTR, 0)
#ifdef PORT5_BASE_PTR
,&PORT_PCR_REG(PORT5_BASE_PTR, 0)
#endif
};
const static GPIO_MemMapPtr gpio_ptr_arr[] = {
PT0_BASE_PTR,
PT1_BASE_PTR,
PT2_BASE_PTR,
PT3_BASE_PTR,
PT4_BASE_PTR
/*TASK*-----------------------------------------------------------------
*
* Function Name : main_task
* Returned Value : void
* Comments :
*
*END------------------------------------------------------------------*/
void main_task(uint_32 temp) {
int_32 error;
HTTPD_STRUCT *server[BSP_ENET_DEVICE_COUNT];
extern const HTTPD_CGI_LINK_STRUCT cgi_lnk_tbl[];
extern const TFS_DIR_ENTRY tfs_data[];
HTTPD_PARAMS_STRUCT *params[BSP_ENET_DEVICE_COUNT];
_enet_address address[BSP_ENET_DEVICE_COUNT];
uint_32 phy_addr[BSP_ENET_DEVICE_COUNT];
uint_32 ip_addr[BSP_ENET_DEVICE_COUNT];
uint_32 i = 0;
char* indexes[BSP_ENET_DEVICE_COUNT];
uint_8 n_devices = BSP_ENET_DEVICE_COUNT;
#if DEMOCFG_USE_WIFI
ENET_ESSID ssid;
uint_32 mode;// = DEMOCFG_NW_MODE;
uint_32 sectype;// = DEMOCFG_SECURITY;
ENET_MEDIACTL_PARAM param;
#endif
#if RTCSCFG_ENABLE_IP6
IPCFG6_GET_ADDR_DATA data[RTCSCFG_IP6_IF_ADDRESSES_MAX];
char prn_addr6[sizeof "ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255"];
uint_32 n = 0;
uint_32 j = 0;
#endif
_int_install_unexpected_isr();
/*---------------- Initialize devices and variables ----------------------*/
_RTCSPCB_init = 4;
_RTCSPCB_grow = 2;
_RTCSPCB_max = 8;
_RTCSTASK_stacksize = 4500;
/*--------------------------- Init end -----------------------------------*/
PORT_PCR_REG(PORTC_BASE_PTR, 3) = PORT_PCR_MUX(5);
// SIM_SOPT2 |= 3<<5; // 1k LPO
error = RTCS_create();
if (error != RTCS_OK)
{
printf("RTCS failed to initialize, error = 0x%X\n", error);
_task_block();
}
_IP_forward = TRUE;
for (i = 0; (i < n_devices) && (n_devices != 0); i++)
{
IPCFG_IP_ADDRESS_DATA ip_data;
phy_addr[i] = i;
ip_addr[i] = IPADDR(A,B,C+i,D);
ENET_get_mac_address (phy_addr[i], ip_addr[i], address[i]);
/* Init ENET device */
error = ipcfg_init_device (phy_addr[i], address[i]);
if (error != RTCS_OK)
{
printf("IPCFG: Device n.%d init failed. Error = 0x%X\n", i, error);
_task_set_error(MQX_OK);
n_devices--;
i--;
continue;
}
#if RTCSCFG_ENABLE_IP4
ip_data.ip = ip_addr[i];
ip_data.mask = ENET_IPMASK;
ip_data.gateway = 0;
/* Bind IPv4 address */
//error = ipcfg_bind_staticip (phy_addr[i], &ip_data);
error = ipcfg_bind_autoip (phy_addr[i], &ip_data);
if (error != RTCS_OK)
{
printf("\nIPCFG: Failed to bind IP address. Error = 0x%X", error);
_task_block();
}
#endif /* RTCSCFG_ENABLE_IP4 */
indexes[i] = (char*) _mem_alloc(sizeof("\\index_x.html"));
}
error = _io_tfs_install("tfs:", tfs_data);
#if DEBUG__MESSAGES
printf("Preparing http servers...\n");
#endif
for (i = 0; i < n_devices; i++)
{
params[i] = httpd_default_params(NULL);
params[i]->af = HTTP_INET_AF; //IPv4+IPv6, set connection family from config.h
#if RTCSCFG_ENABLE_IP6
params[i]->if_scope_id = HTTP_SCOPE_ID; // set interface number here. 0 is any .
#endif
if (params[i])
{
sprintf(indexes[i], "\\index.html", i);
params[i]->root_dir = (HTTPD_ROOT_DIR_STRUCT*)root_dir;
params[i]->index_page = indexes[i];
printf("Starting http server No.%d on IP", i);
/*
** If there is only one interface listen on any IP address
** so address can change in runtime (DHCP etc.)
*/
#if RTCSCFG_ENABLE_IP4
if ((i == 0) && (n_devices == 1))
{
params[i]->address = INADDR_ANY;
}
else
{
params[i]->address = ip_addr[i];
}
/* Print active ip addresses */
printf(" %d.%d.%d.%d", IPBYTES(ip_addr[i]));
#endif
#if RTCSCFG_ENABLE_IP6
while(!ipcfg6_get_addr_info_n(i, n, &data[n]))
{
n++;
}
while(j < n)
{
if(inet_ntop(AF_INET6, &data[j++].ip_addr, prn_addr6, sizeof(prn_addr6)))
{
/* Print active ip addresses */
#if RTCSCFG_ENABLE_IP4
printf("%s %s", (HTTP_INET_AF & AF_INET) ? " and" : "", prn_addr6);
#else
printf(" %s", prn_addr6);
#endif
}
}
#endif
#if PSP_MQX_CPU_IS_MCF5223X
params[i]->max_ses = 1;
#else
params[i]->max_ses = _RTCS_socket_part_max - 1;
#endif
server[i] = httpd_init(params[i]);
}
HTTPD_SET_PARAM_CGI_TBL(server[i], (HTTPD_CGI_LINK_STRUCT*)cgi_lnk_tbl);
#if HTTPD_SEPARATE_TASK || !HTTPDCFG_POLL_MODE
printf("...");
error = httpd_server_run(server[i]);
if (error)
{
printf("[FAIL]\n");
}
else
{
printf("[OK]\n");
}
#endif
}
/* user stuff come here */
#if HTTPD_SEPARATE_TASK || !HTTPDCFG_POLL_MODE
_task_create(0, SHELL_TASK, 0);
_task_block();
#else
printf("Servers polling started.\n")
while (1)
{
for (i = 0; i < n_devices; i++)
{
httpd_server_poll(server[i], 1);
}
/* user stuff come here - only non blocking calls */
}
#endif
}
