/* $3f SWI absolute indirect ----- */ INLINE void swi( void ) { PUSHWORD(pPC); PUSHWORD(pX); PUSHBYTE(A); PUSHBYTE(B); PUSHBYTE(CC); SEI; PCD = RM16(0xfffa); CHANGE_PC(); }
static void check_irq_lines(m68_state_t *m68_state) { if( m68_state->irq_state[M6809_IRQ_LINE] != CLEAR_LINE || m68_state->irq_state[M6809_FIRQ_LINE] != CLEAR_LINE ) m68_state->int_state &= ~M6809_SYNC; /* clear SYNC flag */ if( m68_state->irq_state[M6809_FIRQ_LINE]!=CLEAR_LINE && !(CC & CC_IF) ) { /* fast IRQ */ /* HJB 990225: state already saved by CWAI? */ if( m68_state->int_state & M6809_CWAI ) { m68_state->int_state &= ~M6809_CWAI; /* clear CWAI */ m68_state->extra_cycles += 7; /* subtract +7 cycles */ } else { CC &= ~CC_E; /* save 'short' state */ PUSHWORD(pPC); PUSHBYTE(CC); m68_state->extra_cycles += 10; /* subtract +10 cycles */ } CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */ PCD=RM16(m68_state, 0xfff6); (void)(*m68_state->irq_callback)(m68_state->device, M6809_FIRQ_LINE); } else if( m68_state->irq_state[M6809_IRQ_LINE]!=CLEAR_LINE && !(CC & CC_II) ) { /* standard IRQ */ /* HJB 990225: state already saved by CWAI? */ if( m68_state->int_state & M6809_CWAI ) { m68_state->int_state &= ~M6809_CWAI; /* clear CWAI flag */ m68_state->extra_cycles += 7; /* subtract +7 cycles */ } else { CC |= CC_E; /* save entire state */ PUSHWORD(pPC); PUSHWORD(pU); PUSHWORD(pY); PUSHWORD(pX); PUSHBYTE(DP); PUSHBYTE(B); PUSHBYTE(A); PUSHBYTE(CC); m68_state->extra_cycles += 19; /* subtract +19 cycles */ } CC |= CC_II; /* inhibit IRQ */ PCD=RM16(m68_state, 0xfff8); (void)(*m68_state->irq_callback)(m68_state->device, M6809_IRQ_LINE); } }
/**************************************************************************** * Set IRQ line state ****************************************************************************/ static void set_irq_line(int irqline, int state) { if (irqline == INPUT_LINE_NMI) { if (hd6309.nmi_state == state) return; hd6309.nmi_state = state; LOG(("HD6309#%d set_irq_line (NMI) %d (PC=%4.4X)\n", cpu_getactivecpu(), state, pPC)); if( state == CLEAR_LINE ) return; /* if the stack was not yet initialized */ if( !(hd6309.int_state & HD6309_LDS) ) return; hd6309.int_state &= ~HD6309_SYNC; /* HJB 990225: state already saved by CWAI? */ if( hd6309.int_state & HD6309_CWAI ) { hd6309.int_state &= ~HD6309_CWAI; hd6309.extra_cycles += 7; /* subtract +7 cycles next time */ } else { CC |= CC_E; /* save entire state */ PUSHWORD(pPC); PUSHWORD(pU); PUSHWORD(pY); PUSHWORD(pX); PUSHBYTE(DP); if ( MD & MD_EM ) { PUSHBYTE(F); PUSHBYTE(E); hd6309.extra_cycles += 2; /* subtract +2 cycles */ } PUSHBYTE(B); PUSHBYTE(A); PUSHBYTE(CC); hd6309.extra_cycles += 19; /* subtract +19 cycles next time */ } CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */ PCD = RM16(0xfffc); CHANGE_PC; } else if (irqline < 2) { LOG(("HD6309#%d set_irq_line %d, %d (PC=%4.4X)\n", cpu_getactivecpu(), irqline, state, pPC)); hd6309.irq_state[irqline] = state; if (state == CLEAR_LINE) return; CHECK_IRQ_LINES(); } }
/* $3e WAI inherent ----- */ INLINE void wai( void ) { /* * WAI stacks the entire machine state on the * hardware stack, then waits for an interrupt. */ m6808.wai_state |= M6808_WAI; PUSHWORD(pPC); PUSHWORD(pX); PUSHBYTE(A); PUSHBYTE(B); PUSHBYTE(CC); CHECK_IRQ_LINES(); if (m6808.wai_state & M6808_WAI) EAT_CYCLES; }
/**************************************************************************** * Set IRQ line state ****************************************************************************/ void konami_set_irq_line(int irqline, int state) { #if defined FBA_DEBUG if (!DebugCPU_KonamiInitted) bprintf(PRINT_ERROR, _T("konami_set_irq_line called without init\n")); #endif if (irqline == KONAMI_INPUT_LINE_NMI) { if (konami.nmi_state == state) return; konami.nmi_state = state; // LOG(("KONAMI#%d set_nmi_line %d\n", cpu_getactivecpu(), state)); if( state == CPU_IRQSTATUS_NONE ) return; /* if the stack was not yet initialized */ if( !(konami.int_state & KONAMI_LDS) ) return; konami.int_state &= ~KONAMI_SYNC; /* state already saved by CWAI? */ if( konami.int_state & KONAMI_CWAI ) { konami.int_state &= ~KONAMI_CWAI; konami.extra_cycles += 7; /* subtract +7 cycles next time */ } else { CC |= CC_E; /* save entire state */ PUSHWORD(pPC); PUSHWORD(pU); PUSHWORD(pY); PUSHWORD(pX); PUSHBYTE(DP); PUSHBYTE(B); PUSHBYTE(A); PUSHBYTE(CC); konami.extra_cycles += 19; /* subtract +19 cycles next time */ } CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */ PCD = RM16(0xfffc); change_pc(PC); /* TS 971002 */ } else if (irqline < 2) { // LOG(("KONAMI#%d set_irq_line %d, %d\n", cpu_getactivecpu(), irqline, state)); konami.irq_state[irqline] = state; if (state == CPU_IRQSTATUS_NONE) return; CHECK_IRQ_LINES; } }
static void trap_23( void ) { PUSHWORD( PC ); pPC = RM16(0xffd0); CHANGE_PC; tms7000_icount -= 14; }
/* Generate interrupt - m68705 version */ void m68705_device::interrupt() { if ((m_pending_interrupts & ((1 << M6805_IRQ_LINE) | M68705_INT_MASK)) != 0 ) { if ((CC & IFLAG) == 0) { PUSHWORD(m_pc); PUSHBYTE(m_x); PUSHBYTE(m_a); PUSHBYTE(m_cc); SEI; standard_irq_callback(0); if ((m_pending_interrupts & (1 << M68705_IRQ_LINE)) != 0 ) { m_pending_interrupts &= ~(1 << M68705_IRQ_LINE); RM16(0xfffa, &m_pc); } else if ((m_pending_interrupts & (1 << M68705_INT_TIMER)) != 0) { m_pending_interrupts &= ~(1 << M68705_INT_TIMER); RM16(0xfff8, &m_pc); } } m_icount -= 11; } }
/* $bd JSR extended ----- */ INLINE void jsr_ex( void ) { EXTENDED; PUSHWORD(pPC); PC = EA; CHANGE_PC(); }
/* Generate interrupt - m68705 version */ static void m68705_Interrupt( m6805_Regs *cpustate ) { if( (cpustate->pending_interrupts & ((1<<M6805_IRQ_LINE)|M68705_INT_MASK)) != 0 ) { if ( (CC & IFLAG) == 0 ) { PUSHWORD(cpustate->pc); PUSHBYTE(cpustate->x); PUSHBYTE(cpustate->a); PUSHBYTE(cpustate->cc); SEI; if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0); if ((cpustate->pending_interrupts & (1<<M68705_IRQ_LINE)) != 0 ) { cpustate->pending_interrupts &= ~(1<<M68705_IRQ_LINE); RM16( cpustate, 0xfffa, &pPC); } else if((cpustate->pending_interrupts&(1<<M68705_INT_TIMER))!=0) { cpustate->pending_interrupts &= ~(1<<M68705_INT_TIMER); RM16( cpustate, 0xfff8, &pPC); } } cpustate->iCount -= 11; } }
/* $9d JSR direct ----- */ INLINE void jsr_di( void ) { DIRECT; PUSHWORD(pPC); PC = EA; CHANGE_PC(); }
/* $ad JSR indexed ----- */ INLINE void jsr_ix( void ) { INDEXED; PUSHWORD(pPC); PC = EA; CHANGE_PC(); }
/* Generate interrupt - m68705 version */ static void m68705_Interrupt(void) { if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|M68705_INT_MASK)) != 0 ) { if ( (CC & IFLAG) == 0 ) { PUSHWORD(m6805.pc); PUSHBYTE(m6805.x); PUSHBYTE(m6805.a); PUSHBYTE(m6805.cc); SEI; if (m6805.irq_callback) (*m6805.irq_callback)(0); if ((m6805.pending_interrupts & (1<<M68705_IRQ_LINE)) != 0 ) { m6805.pending_interrupts &= ~(1<<M68705_IRQ_LINE); RM16( 0xfffa, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<M68705_INT_TIMER))!=0) { m6805.pending_interrupts &= ~(1<<M68705_INT_TIMER); RM16( 0xfff8, &pPC); change_pc(PC); } } m6805_ICount -= 11; } }
/* $8d BSR ----- */ INLINE void bsr( void ) { UINT8 t; IMMBYTE(t); PUSHWORD(pPC); PC += SIGNED(t); CHANGE_PC(); /* TS 971002 */ }
DERIVED_OP_HANDLER( hd63705, swi ) { PUSHWORD(m_pc); PUSHBYTE(m_x); PUSHBYTE(m_a); PUSHBYTE(m_cc); SEI; RM16(0x1ffa, &m_pc); }
/**************************************************************************** * Set IRQ line state ****************************************************************************/ static void set_irq_line(int irqline, int state) { if (irqline == INPUT_LINE_NMI) { if (konami.nmi_state == state) return; konami.nmi_state = state; LOG(("KONAMI#%d set_nmi_line %d\n", cpu_getactivecpu(), state)); if( state == CLEAR_LINE ) return; /* if the stack was not yet initialized */ if( !(konami.int_state & KONAMI_LDS) ) return; konami.int_state &= ~KONAMI_SYNC; /* state already saved by CWAI? */ if( konami.int_state & KONAMI_CWAI ) { konami.int_state &= ~KONAMI_CWAI; konami.extra_cycles += 7; /* subtract +7 cycles next time */ } else { CC |= CC_E; /* save entire state */ PUSHWORD(pPC); PUSHWORD(pU); PUSHWORD(pY); PUSHWORD(pX); PUSHBYTE(DP); PUSHBYTE(B); PUSHBYTE(A); PUSHBYTE(CC); konami.extra_cycles += 19; /* subtract +19 cycles next time */ } CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */ PCD = RM16(0xfffc); change_pc(PC); /* TS 971002 */ } else if (irqline < 2) { LOG(("KONAMI#%d set_irq_line %d, %d\n", cpu_getactivecpu(), irqline, state)); konami.irq_state[irqline] = state; if (state == CLEAR_LINE) return; CHECK_IRQ_LINES; } }
/**************************************************************************** * Set IRQ line state ****************************************************************************/ static void set_irq_line(m68_state_t *m68_state, int irqline, int state) { if (irqline == INPUT_LINE_NMI) { if (m68_state->nmi_state == state) return; m68_state->nmi_state = state; LOG(("M6809 '%s' set_irq_line (NMI) %d\n", m68_state->device->tag(), state)); if( state == CLEAR_LINE ) return; /* if the stack was not yet initialized */ if( !(m68_state->int_state & M6809_LDS) ) return; m68_state->int_state &= ~M6809_SYNC; /* HJB 990225: state already saved by CWAI? */ if( m68_state->int_state & M6809_CWAI ) { m68_state->int_state &= ~M6809_CWAI; m68_state->extra_cycles += 7; /* subtract +7 cycles next time */ } else { CC |= CC_E; /* save entire state */ PUSHWORD(pPC); PUSHWORD(pU); PUSHWORD(pY); PUSHWORD(pX); PUSHBYTE(DP); PUSHBYTE(B); PUSHBYTE(A); PUSHBYTE(CC); m68_state->extra_cycles += 19; /* subtract +19 cycles next time */ } CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */ PCD = RM16(m68_state, 0xfffc); } else if (irqline < 2) { LOG(("M6809 '%s' set_irq_line %d, %d\n", m68_state->device->tag(), irqline, state)); m68_state->irq_state[irqline] = state; if (state == CLEAR_LINE) return; check_irq_lines(m68_state); } }
static void call_ind( void ) { UINT8 v; IMMBYTE( v ); PUSHWORD( PC ); PC.w.l = RRF16(v); tms7000_icount -= 13; }
static void call_inx( void ) { PAIR tPC; IMMWORD( tPC ); PUSHWORD( PC ); pPC = tPC.w.l + RDB; CHANGE_PC; tms7000_icount -= 16; }
static void call_dir( void ) { PAIR tPC; IMMWORD( tPC ); PUSHWORD( PC ); pPC = tPC.d; CHANGE_PC; tms7000_icount -= 14; }
/* Generate interrupts */ void m6805_base_device::interrupt() { /* the 6805 latches interrupt requests internally, so we don't clear */ /* pending_interrupts until the interrupt is taken, no matter what the */ /* external IRQ pin does. */ if ((m_pending_interrupts & (1 << HD63705_INT_NMI)) != 0) { PUSHWORD(m_pc); PUSHBYTE(m_x); PUSHBYTE(m_a); PUSHBYTE(m_cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ standard_irq_callback(0); RM16(0x1ffc, &m_pc); m_pending_interrupts &= ~(1 << HD63705_INT_NMI); m_icount -= 11; } else if((m_pending_interrupts & ((1 << M6805_IRQ_LINE) | HD63705_INT_MASK)) != 0) { if ((CC & IFLAG) == 0) { /* standard IRQ */ PUSHWORD(m_pc); PUSHBYTE(m_x); PUSHBYTE(m_a); PUSHBYTE(m_cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ standard_irq_callback(0); interrupt_vector(); m_pending_interrupts &= ~(1 << M6805_IRQ_LINE); } m_icount -= 11; } }
/* IRQ enter */ void m6800_cpu_device::enter_interrupt(const char *message,UINT16 irq_vector) { LOG((message, tag())); if( m_wai_state & (M6800_WAI|M6800_SLP) ) { if( m_wai_state & M6800_WAI ) m_icount -= 4; m_wai_state &= ~(M6800_WAI|M6800_SLP); } else { PUSHWORD(pPC); PUSHWORD(pX); PUSHBYTE(A); PUSHBYTE(B); PUSHBYTE(CC); m_icount -= 12; } SEI; PCD = RM16( irq_vector ); }
static void tms7000_do_interrupt( UINT16 address, UINT8 line ) { PUSHBYTE( pSR ); /* Push Status register */ PUSHWORD( PC ); /* Push Program Counter */ pSR = 0; /* Clear Status register */ pPC = RM16(address); /* Load PC with interrupt vector */ CHANGE_PC; if( tms7000.idle_state == 0 ) tms7000_icount -= 19; /* 19 cycles used */ else { tms7000_icount -= 17; /* 17 if idled */ tms7000.idle_state = 0; } (void)(*tms7000.irq_callback)(line); }
void CHECK_IRQ_LINES( void ) { if( hd6309.irq_state[HD6309_IRQ_LINE] != CLEAR_LINE || hd6309.irq_state[HD6309_FIRQ_LINE] != CLEAR_LINE ) hd6309.int_state &= ~HD6309_SYNC; /* clear SYNC flag */ if( hd6309.irq_state[HD6309_FIRQ_LINE]!=CLEAR_LINE && !(CC & CC_IF)) { /* fast IRQ */ /* HJB 990225: state already saved by CWAI? */ if( hd6309.int_state & HD6309_CWAI ) { hd6309.int_state &= ~HD6309_CWAI; hd6309.extra_cycles += 7; /* subtract +7 cycles */ } else { if ( MD & MD_FM ) { CC |= CC_E; /* save entire state */ PUSHWORD(pPC); PUSHWORD(pU); PUSHWORD(pY); PUSHWORD(pX); PUSHBYTE(DP); if ( MD & MD_EM ) { PUSHBYTE(F); PUSHBYTE(E); hd6309.extra_cycles += 2; /* subtract +2 cycles */ } PUSHBYTE(B); PUSHBYTE(A); PUSHBYTE(CC); hd6309.extra_cycles += 19; /* subtract +19 cycles */ } else { CC &= ~CC_E; /* save 'short' state */ PUSHWORD(pPC); PUSHBYTE(CC); hd6309.extra_cycles += 10; /* subtract +10 cycles */ } } CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */ PCD=RM16(0xfff6); CHANGE_PC; (void)(*hd6309.irq_callback)(HD6309_FIRQ_LINE); } else if( hd6309.irq_state[HD6309_IRQ_LINE]!=CLEAR_LINE && !(CC & CC_II) ) { /* standard IRQ */ /* HJB 990225: state already saved by CWAI? */ if( hd6309.int_state & HD6309_CWAI ) { hd6309.int_state &= ~HD6309_CWAI; /* clear CWAI flag */ hd6309.extra_cycles += 7; /* subtract +7 cycles */ } else { CC |= CC_E; /* save entire state */ PUSHWORD(pPC); PUSHWORD(pU); PUSHWORD(pY); PUSHWORD(pX); PUSHBYTE(DP); if ( MD & MD_EM ) { PUSHBYTE(F); PUSHBYTE(E); hd6309.extra_cycles += 2; /* subtract +2 cycles */ } PUSHBYTE(B); PUSHBYTE(A); PUSHBYTE(CC); hd6309.extra_cycles += 19; /* subtract +19 cycles */ } CC |= CC_II; /* inhibit IRQ */ PCD=RM16(0xfff8); CHANGE_PC; (void)(*hd6309.irq_callback)(HD6309_IRQ_LINE); } }
/* Generate interrupts */ static void Interrupt(void) { /* the 6805 latches interrupt requests internally, so we don't clear */ /* pending_interrupts until the interrupt is taken, no matter what the */ /* external IRQ pin does. */ #if (HAS_HD63705) if( (m6805.pending_interrupts & (1<<HD63705_INT_NMI)) != 0) { PUSHWORD(m6805.pc); PUSHBYTE(m6805.x); PUSHBYTE(m6805.a); PUSHBYTE(m6805.cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ if (m6805.irq_callback) (*m6805.irq_callback)(0); RM16( 0x1ffc, &pPC); change_pc(PC); m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI); m6805_ICount -= 11; } else if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) { if ( (CC & IFLAG) == 0 ) { #else if( (m6805.pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) { if ( (CC & IFLAG) == 0 ) { #endif { /* standard IRQ */ /*#if (HAS_HD63705) */ /* if(SUBTYPE!=SUBTYPE_HD63705) */ /*#endif */ /* PC |= ~AMASK; */ PUSHWORD(m6805.pc); PUSHBYTE(m6805.x); PUSHBYTE(m6805.a); PUSHBYTE(m6805.cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ if (m6805.irq_callback) (*m6805.irq_callback)(0); #if (HAS_HD63705) if(SUBTYPE==SUBTYPE_HD63705) { /* Need to add emulation of other interrupt sources here KW-2/4/99 */ /* This is just a quick patch for Namco System 2 operation */ if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ1))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1); RM16( 0x1ff8, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2); RM16( 0x1fec, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV); RM16( 0x1fea, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1); RM16( 0x1ff6, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2); RM16( 0x1ff4, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3); RM16( 0x1ff2, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI); RM16( 0x1ff0, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI); RM16( 0x1fee, &pPC); change_pc(PC); } } else #endif { RM16( 0xffff - 5, &pPC ); change_pc(PC); } } /* CC & IFLAG */ m6805.pending_interrupts &= ~(1<<M6805_IRQ_LINE); } m6805_ICount -= 11; } } static void state_register(const char *type) { int cpu = cpu_getactivecpu(); state_save_register_UINT8(type, cpu, "A", &A, 1); state_save_register_UINT16(type, cpu, "PC", &PC, 1); state_save_register_UINT16(type, cpu, "S", &S, 1); state_save_register_UINT8(type, cpu, "X", &X, 1); state_save_register_UINT8(type, cpu, "CC", &CC, 1); state_save_register_UINT16(type, cpu, "PENDING", &m6805.pending_interrupts, 1); state_save_register_INT32(type, cpu, "IRQ_STATE", &m6805.irq_state[0], 1); } static void m6805_init(void) { state_register("m6805"); }
/* Generate interrupts */ static void Interrupt(void) { /* the 6805 latches interrupt requests internally, so we don't clear */ /* pending_interrupts until the interrupt is taken, no matter what the */ /* external IRQ pin does. */ #if (1) //HAS_HD63705) if( (m6805.pending_interrupts & (1<<HD63705_INT_NMI)) != 0) { PUSHWORD(m6805.pc); PUSHBYTE(m6805.x); PUSHBYTE(m6805.a); PUSHBYTE(m6805.cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ if (m6805.irq_callback) (*m6805.irq_callback)(0); RM16( 0x1ffc, &pPC); change_pc(PC); m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI); m6805_ICount -= 11; } else if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) { if ( (CC & IFLAG) == 0 ) { #else if( (m6805.pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) { if ( (CC & IFLAG) == 0 ) { #endif { /* standard IRQ */ //#if (HAS_HD63705) // if(SUBTYPE!=SUBTYPE_HD63705) //#endif // PC |= ~AMASK; PUSHWORD(m6805.pc); PUSHBYTE(m6805.x); PUSHBYTE(m6805.a); PUSHBYTE(m6805.cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ if (m6805.irq_callback) (*m6805.irq_callback)(0); //#if (HAS_HD63705) if(SUBTYPE==SUBTYPE_HD63705) { /* Need to add emulation of other interrupt sources here KW-2/4/99 */ /* This is just a quick patch for Namco System 2 operation */ if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ1))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1); RM16( 0x1ff8, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2); RM16( 0x1fec, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV); RM16( 0x1fea, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1); RM16( 0x1ff6, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2); RM16( 0x1ff4, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3); RM16( 0x1ff2, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI); RM16( 0x1ff0, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI); RM16( 0x1fee, &pPC); change_pc(PC); } } else //#endif { RM16( 0xffff - 5, &pPC ); change_pc(PC); } } // CC & IFLAG m6805.pending_interrupts &= ~(1<<M6805_IRQ_LINE); } m6805_ICount -= 11; } } static void m6805_reset() { int (*save_irqcallback)(int) = m6805.irq_callback; memset(&m6805, 0, sizeof(m6805)); m6805.irq_callback = save_irqcallback; /* Force CPU sub-type and relevant masks */ m6805.subtype = SUBTYPE_M6805; SP_MASK = 0x07f; SP_LOW = 0x060; /* Initial stack pointer */ S = SP_MASK; /* IRQ disabled */ SEI; RM16( 0xfffe , &pPC ); change_pc(PC); } void m6805Reset() { m6805_reset(); } //static void m6805_init(int ) //int (*irqcallback)(int)) //{ // m6805.irq_callback = irqcallback; //} //static void m6805_exit(void) //{ // /* nothing to do */ //} void m6805SetIrqLine(int , int state) { /* Basic 6805 only has one IRQ line */ /* See HD63705 specific version */ if (m6805.irq_state[0] == state) return; m6805.irq_state[0] = state; if (state != CLEAR_LINE) m6805.pending_interrupts |= 1<<M6805_IRQ_LINE; } #include "6805ops.c" /* execute instructions on this CPU until icount expires */ int m6805Run(int cycles) { UINT8 ireg; m6805_ICount = cycles; do { if (m6805.pending_interrupts != 0) { if (SUBTYPE==SUBTYPE_M68705) { m68705_Interrupt(); } else { Interrupt(); } } ireg=M_RDOP(PC++); switch( ireg ) { case 0x00: brset(0x01); break; case 0x01: brclr(0x01); break; case 0x02: brset(0x02); break; case 0x03: brclr(0x02); break; case 0x04: brset(0x04); break; case 0x05: brclr(0x04); break; case 0x06: brset(0x08); break; case 0x07: brclr(0x08); break; case 0x08: brset(0x10); break; case 0x09: brclr(0x10); break; case 0x0A: brset(0x20); break; case 0x0B: brclr(0x20); break; case 0x0C: brset(0x40); break; case 0x0D: brclr(0x40); break; case 0x0E: brset(0x80); break; case 0x0F: brclr(0x80); break; case 0x10: bset(0x01); break; case 0x11: bclr(0x01); break; case 0x12: bset(0x02); break; case 0x13: bclr(0x02); break; case 0x14: bset(0x04); break; case 0x15: bclr(0x04); break; case 0x16: bset(0x08); break; case 0x17: bclr(0x08); break; case 0x18: bset(0x10); break; case 0x19: bclr(0x10); break; case 0x1a: bset(0x20); break; case 0x1b: bclr(0x20); break; case 0x1c: bset(0x40); break; case 0x1d: bclr(0x40); break; case 0x1e: bset(0x80); break; case 0x1f: bclr(0x80); break; case 0x20: bra(); break; case 0x21: brn(); break; case 0x22: bhi(); break; case 0x23: bls(); break; case 0x24: bcc(); break; case 0x25: bcs(); break; case 0x26: bne(); break; case 0x27: beq(); break; case 0x28: bhcc(); break; case 0x29: bhcs(); break; case 0x2a: bpl(); break; case 0x2b: bmi(); break; case 0x2c: bmc(); break; case 0x2d: bms(); break; case 0x2e: bil(); break; case 0x2f: bih(); break; case 0x30: neg_di(); break; case 0x31: illegal(); break; case 0x32: illegal(); break; case 0x33: com_di(); break; case 0x34: lsr_di(); break; case 0x35: illegal(); break; case 0x36: ror_di(); break; case 0x37: asr_di(); break; case 0x38: lsl_di(); break; case 0x39: rol_di(); break; case 0x3a: dec_di(); break; case 0x3b: illegal(); break; case 0x3c: inc_di(); break; case 0x3d: tst_di(); break; case 0x3e: illegal(); break; case 0x3f: clr_di(); break; case 0x40: nega(); break; case 0x41: illegal(); break; case 0x42: illegal(); break; case 0x43: coma(); break; case 0x44: lsra(); break; case 0x45: illegal(); break; case 0x46: rora(); break; case 0x47: asra(); break; case 0x48: lsla(); break; case 0x49: rola(); break; case 0x4a: deca(); break; case 0x4b: illegal(); break; case 0x4c: inca(); break; case 0x4d: tsta(); break; case 0x4e: illegal(); break; case 0x4f: clra(); break; case 0x50: negx(); break; case 0x51: illegal(); break; case 0x52: illegal(); break; case 0x53: comx(); break; case 0x54: lsrx(); break; case 0x55: illegal(); break; case 0x56: rorx(); break; case 0x57: asrx(); break; case 0x58: aslx(); break; case 0x59: rolx(); break; case 0x5a: decx(); break; case 0x5b: illegal(); break; case 0x5c: incx(); break; case 0x5d: tstx(); break; case 0x5e: illegal(); break; case 0x5f: clrx(); break; case 0x60: neg_ix1(); break; case 0x61: illegal(); break; case 0x62: illegal(); break; case 0x63: com_ix1(); break; case 0x64: lsr_ix1(); break; case 0x65: illegal(); break; case 0x66: ror_ix1(); break; case 0x67: asr_ix1(); break; case 0x68: lsl_ix1(); break; case 0x69: rol_ix1(); break; case 0x6a: dec_ix1(); break; case 0x6b: illegal(); break; case 0x6c: inc_ix1(); break; case 0x6d: tst_ix1(); break; case 0x6e: illegal(); break; case 0x6f: clr_ix1(); break; case 0x70: neg_ix(); break; case 0x71: illegal(); break; case 0x72: illegal(); break; case 0x73: com_ix(); break; case 0x74: lsr_ix(); break; case 0x75: illegal(); break; case 0x76: ror_ix(); break; case 0x77: asr_ix(); break; case 0x78: lsl_ix(); break; case 0x79: rol_ix(); break; case 0x7a: dec_ix(); break; case 0x7b: illegal(); break; case 0x7c: inc_ix(); break; case 0x7d: tst_ix(); break; case 0x7e: illegal(); break; case 0x7f: clr_ix(); break; case 0x80: rti(); break; case 0x81: rts(); break; case 0x82: illegal(); break; case 0x83: swi(); break; case 0x84: illegal(); break; case 0x85: illegal(); break; case 0x86: illegal(); break; case 0x87: illegal(); break; case 0x88: illegal(); break; case 0x89: illegal(); break; case 0x8a: illegal(); break; case 0x8b: illegal(); break; case 0x8c: illegal(); break; case 0x8d: illegal(); break; case 0x8e: illegal(); break; case 0x8f: illegal(); break; case 0x90: illegal(); break; case 0x91: illegal(); break; case 0x92: illegal(); break; case 0x93: illegal(); break; case 0x94: illegal(); break; case 0x95: illegal(); break; case 0x96: illegal(); break; case 0x97: tax(); break; case 0x98: CLC; break; case 0x99: SEC; break; #if IRQ_LEVEL_DETECT case 0x9a: CLI; if (m6805.irq_state != CLEAR_LINE) m6805.pending_interrupts |= 1<<M6805_IRQ_LINE; break; #else case 0x9a: CLI; break; #endif case 0x9b: SEI; break; case 0x9c: rsp(); break; case 0x9d: nop(); break; case 0x9e: illegal(); break; case 0x9f: txa(); break; case 0xa0: suba_im(); break; case 0xa1: cmpa_im(); break; case 0xa2: sbca_im(); break; case 0xa3: cpx_im(); break; case 0xa4: anda_im(); break; case 0xa5: bita_im(); break; case 0xa6: lda_im(); break; case 0xa7: illegal(); break; case 0xa8: eora_im(); break; case 0xa9: adca_im(); break; case 0xaa: ora_im(); break; case 0xab: adda_im(); break; case 0xac: illegal(); break; case 0xad: bsr(); break; case 0xae: ldx_im(); break; case 0xaf: illegal(); break; case 0xb0: suba_di(); break; case 0xb1: cmpa_di(); break; case 0xb2: sbca_di(); break; case 0xb3: cpx_di(); break; case 0xb4: anda_di(); break; case 0xb5: bita_di(); break; case 0xb6: lda_di(); break; case 0xb7: sta_di(); break; case 0xb8: eora_di(); break; case 0xb9: adca_di(); break; case 0xba: ora_di(); break; case 0xbb: adda_di(); break; case 0xbc: jmp_di(); break; case 0xbd: jsr_di(); break; case 0xbe: ldx_di(); break; case 0xbf: stx_di(); break; case 0xc0: suba_ex(); break; case 0xc1: cmpa_ex(); break; case 0xc2: sbca_ex(); break; case 0xc3: cpx_ex(); break; case 0xc4: anda_ex(); break; case 0xc5: bita_ex(); break; case 0xc6: lda_ex(); break; case 0xc7: sta_ex(); break; case 0xc8: eora_ex(); break; case 0xc9: adca_ex(); break; case 0xca: ora_ex(); break; case 0xcb: adda_ex(); break; case 0xcc: jmp_ex(); break; case 0xcd: jsr_ex(); break; case 0xce: ldx_ex(); break; case 0xcf: stx_ex(); break; case 0xd0: suba_ix2(); break; case 0xd1: cmpa_ix2(); break; case 0xd2: sbca_ix2(); break; case 0xd3: cpx_ix2(); break; case 0xd4: anda_ix2(); break; case 0xd5: bita_ix2(); break; case 0xd6: lda_ix2(); break; case 0xd7: sta_ix2(); break; case 0xd8: eora_ix2(); break; case 0xd9: adca_ix2(); break; case 0xda: ora_ix2(); break; case 0xdb: adda_ix2(); break; case 0xdc: jmp_ix2(); break; case 0xdd: jsr_ix2(); break; case 0xde: ldx_ix2(); break; case 0xdf: stx_ix2(); break; case 0xe0: suba_ix1(); break; case 0xe1: cmpa_ix1(); break; case 0xe2: sbca_ix1(); break; case 0xe3: cpx_ix1(); break; case 0xe4: anda_ix1(); break; case 0xe5: bita_ix1(); break; case 0xe6: lda_ix1(); break; case 0xe7: sta_ix1(); break; case 0xe8: eora_ix1(); break; case 0xe9: adca_ix1(); break; case 0xea: ora_ix1(); break; case 0xeb: adda_ix1(); break; case 0xec: jmp_ix1(); break; case 0xed: jsr_ix1(); break; case 0xee: ldx_ix1(); break; case 0xef: stx_ix1(); break; case 0xf0: suba_ix(); break; case 0xf1: cmpa_ix(); break; case 0xf2: sbca_ix(); break; case 0xf3: cpx_ix(); break; case 0xf4: anda_ix(); break; case 0xf5: bita_ix(); break; case 0xf6: lda_ix(); break; case 0xf7: sta_ix(); break; case 0xf8: eora_ix(); break; case 0xf9: adca_ix(); break; case 0xfa: ora_ix(); break; case 0xfb: adda_ix(); break; case 0xfc: jmp_ix(); break; case 0xfd: jsr_ix(); break; case 0xfe: ldx_ix(); break; case 0xff: stx_ix(); break; } m6805_ICount -= cycles1[ireg]; m6805.nTotalCycles += cycles1[ireg]; } while( m6805_ICount > 0 ); return cycles - m6805_ICount; }
static void check_irq_lines(konami_state *cpustate) { if (cpustate->nmi_pending && (cpustate->int_state & KONAMI_LDS)) { cpustate->nmi_pending = FALSE; /* state already saved by CWAI? */ if (cpustate->int_state & KONAMI_CWAI) { cpustate->int_state &= ~KONAMI_CWAI; cpustate->icount -= 7; } else { CC |= CC_E; /* save entire state */ PUSHWORD(cpustate, pPC); PUSHWORD(cpustate, pU); PUSHWORD(cpustate, pY); PUSHWORD(cpustate, pX); PUSHBYTE(cpustate, DP); PUSHBYTE(cpustate, B); PUSHBYTE(cpustate, A); PUSHBYTE(cpustate, CC); cpustate->icount -= 19; } CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */ PCD = RM16(cpustate, 0xfffc); (void)(*cpustate->irq_callback)(cpustate->device, INPUT_LINE_NMI); } else if (cpustate->irq_state[KONAMI_FIRQ_LINE] !=CLEAR_LINE && !(CC & CC_IF)) { /* fast IRQ */ /* state already saved by CWAI? */ if (cpustate->int_state & KONAMI_CWAI) { cpustate->int_state &= ~KONAMI_CWAI; /* clear CWAI */ cpustate->icount -= 7; } else { CC &= ~CC_E; /* save 'short' state */ PUSHWORD(cpustate, pPC); PUSHBYTE(cpustate, CC); cpustate->icount -= 10; } CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */ PCD = RM16(cpustate, 0xfff6); (void)(*cpustate->irq_callback)(cpustate->device, KONAMI_FIRQ_LINE); } else if (cpustate->irq_state[KONAMI_IRQ_LINE] != CLEAR_LINE && !(CC & CC_II)) { /* standard IRQ */ /* state already saved by CWAI? */ if (cpustate->int_state & KONAMI_CWAI) { cpustate->int_state &= ~KONAMI_CWAI; /* clear CWAI flag */ cpustate->icount -= 7; } else { CC |= CC_E; /* save entire state */ PUSHWORD(cpustate, pPC); PUSHWORD(cpustate, pU); PUSHWORD(cpustate, pY); PUSHWORD(cpustate, pX); PUSHBYTE(cpustate, DP); PUSHBYTE(cpustate, B); PUSHBYTE(cpustate, A); PUSHBYTE(cpustate, CC); cpustate->icount -= 19; } CC |= CC_II; /* inhibit IRQ */ PCD = RM16(cpustate, 0xfff8); (void)(*cpustate->irq_callback)(cpustate->device, KONAMI_IRQ_LINE); } }
/* $3c PSHX inherent ----- */ INLINE void pshx (void) { PUSHWORD(pX); }
/* Generate interrupts */ static void Interrupt( m6805_Regs *cpustate ) { /* the 6805 latches interrupt requests internally, so we don't clear */ /* pending_interrupts until the interrupt is taken, no matter what the */ /* external IRQ pin does. */ if( (cpustate->pending_interrupts & (1<<HD63705_INT_NMI)) != 0) { PUSHWORD(cpustate->pc); PUSHBYTE(cpustate->x); PUSHBYTE(cpustate->a); PUSHBYTE(cpustate->cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0); RM16( cpustate, 0x1ffc, &pPC); cpustate->pending_interrupts &= ~(1<<HD63705_INT_NMI); cpustate->iCount -= 11; } else if( (cpustate->pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) { if ( (CC & IFLAG) == 0 ) { { /* standard IRQ */ //#if (HAS_HD63705) // if(SUBTYPE!=SUBTYPE_HD63705) //#endif // PC |= ~AMASK; PUSHWORD(cpustate->pc); PUSHBYTE(cpustate->x); PUSHBYTE(cpustate->a); PUSHBYTE(cpustate->cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0); if(SUBTYPE==SUBTYPE_HD63705) { /* Need to add emulation of other interrupt sources here KW-2/4/99 */ /* This is just a quick patch for Namco System 2 operation */ if((cpustate->pending_interrupts&(1<<HD63705_INT_IRQ1))!=0) { cpustate->pending_interrupts &= ~(1<<HD63705_INT_IRQ1); RM16( cpustate, 0x1ff8, &pPC); } else if((cpustate->pending_interrupts&(1<<HD63705_INT_IRQ2))!=0) { cpustate->pending_interrupts &= ~(1<<HD63705_INT_IRQ2); RM16( cpustate, 0x1fec, &pPC); } else if((cpustate->pending_interrupts&(1<<HD63705_INT_ADCONV))!=0) { cpustate->pending_interrupts &= ~(1<<HD63705_INT_ADCONV); RM16( cpustate, 0x1fea, &pPC); } else if((cpustate->pending_interrupts&(1<<HD63705_INT_TIMER1))!=0) { cpustate->pending_interrupts &= ~(1<<HD63705_INT_TIMER1); RM16( cpustate, 0x1ff6, &pPC); } else if((cpustate->pending_interrupts&(1<<HD63705_INT_TIMER2))!=0) { cpustate->pending_interrupts &= ~(1<<HD63705_INT_TIMER2); RM16( cpustate, 0x1ff4, &pPC); } else if((cpustate->pending_interrupts&(1<<HD63705_INT_TIMER3))!=0) { cpustate->pending_interrupts &= ~(1<<HD63705_INT_TIMER3); RM16( cpustate, 0x1ff2, &pPC); } else if((cpustate->pending_interrupts&(1<<HD63705_INT_PCI))!=0) { cpustate->pending_interrupts &= ~(1<<HD63705_INT_PCI); RM16( cpustate, 0x1ff0, &pPC); } else if((cpustate->pending_interrupts&(1<<HD63705_INT_SCI))!=0) { cpustate->pending_interrupts &= ~(1<<HD63705_INT_SCI); RM16( cpustate, 0x1fee, &pPC); } } else if (SUBTYPE == SUBTYPE_M68HC05EG) { if((cpustate->pending_interrupts&(1<<M68HC05EG_INT_IRQ))!=0) { cpustate->pending_interrupts &= ~(1<<M68HC05EG_INT_IRQ); RM16( cpustate, 0x1ffa, &pPC); } else if((cpustate->pending_interrupts&(1<<M68HC05EG_INT_TIMER))!=0) { cpustate->pending_interrupts &= ~(1<<M68HC05EG_INT_TIMER); RM16( cpustate, 0x1ff8, &pPC); } else if((cpustate->pending_interrupts&(1<<M68HC05EG_INT_CPI))!=0) { cpustate->pending_interrupts &= ~(1<<M68HC05EG_INT_CPI); RM16( cpustate, 0x1ff6, &pPC); } } else { RM16( cpustate, 0xffff - 5, &pPC ); } } // CC & IFLAG cpustate->pending_interrupts &= ~(1<<M6805_IRQ_LINE); } cpustate->iCount -= 11; } }
/* Generate interrupts */ static void Interrupt(void) { /* the 6805 latches interrupt requests internally, so we don't clear */ /* pending_interrupts until the interrupt is taken, no matter what the */ /* external IRQ pin does. */ #if (HAS_HD63705) if( (m6805.pending_interrupts & (1<<HD63705_INT_NMI)) != 0) { PUSHWORD(m6805.pc); PUSHBYTE(m6805.x); PUSHBYTE(m6805.a); PUSHBYTE(m6805.cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ if (m6805.irq_callback) (*m6805.irq_callback)(0); RM16( 0x1ffc, &pPC); change_pc(PC); m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI); m6805_ICount -= 11; } else if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) { if ( (CC & IFLAG) == 0 ) { #else if( (m6805.pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) { if ( (CC & IFLAG) == 0 ) { #endif { /* standard IRQ */ //#if (HAS_HD63705) // if(SUBTYPE!=SUBTYPE_HD63705) //#endif // PC |= ~AMASK; PUSHWORD(m6805.pc); PUSHBYTE(m6805.x); PUSHBYTE(m6805.a); PUSHBYTE(m6805.cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ if (m6805.irq_callback) (*m6805.irq_callback)(0); #if (HAS_HD63705) if(SUBTYPE==SUBTYPE_HD63705) { /* Need to add emulation of other interrupt sources here KW-2/4/99 */ /* This is just a quick patch for Namco System 2 operation */ if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ1))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1); RM16( 0x1ff8, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2); RM16( 0x1fec, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV); RM16( 0x1fea, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1); RM16( 0x1ff6, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2); RM16( 0x1ff4, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3); RM16( 0x1ff2, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI); RM16( 0x1ff0, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI); RM16( 0x1fee, &pPC); change_pc(PC); } } else #endif { RM16( 0xffff - 5, &pPC ); change_pc(PC); } } // CC & IFLAG m6805.pending_interrupts &= ~(1<<M6805_IRQ_LINE); } m6805_ICount -= 11; } } static void state_register(const char *type, int index) { state_save_register_item(type, index, A); state_save_register_item(type, index, PC); state_save_register_item(type, index, S); state_save_register_item(type, index, X); state_save_register_item(type, index, CC); state_save_register_item(type, index, m6805.pending_interrupts); state_save_register_item_array(type, index, m6805.irq_state); } static void m6805_init(int index, int clock, const void *config, int (*irqcallback)(int)) { state_register("m6805", index); m6805.irq_callback = irqcallback; }