void __init pxa_init_irq(int irq_nr, set_wake_t fn) { int irq, i; BUG_ON(irq_nr > MAX_INTERNAL_IRQS); pxa_internal_irq_nr = irq_nr; for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) { _ICMR(irq) = 0; /* disable all IRQs */ _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */ } /* initialize interrupt priority */ if (cpu_is_pxa27x() || cpu_is_pxa3xx()) { for (i = 0; i < irq_nr; i++) IPR(i) = i | (1 << 31); } /* only unmasked interrupts kick us out of idle */ ICCR = 1; for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) { set_irq_chip(irq, &pxa_internal_irq_chip); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } pxa_internal_irq_chip.set_wake = fn; pxa_init_low_gpio_irq(fn); }
static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) { int i, irq = PXA_IRQ(0); for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { saved_icmr[i] = _ICMR(irq); _ICMR(irq) = 0; } return 0; }
static int pxa_irq_resume(struct sys_device *dev) { int i, irq = PXA_IRQ(0); for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { _ICMR(irq) = saved_icmr[i]; _ICLR(irq) = 0; } ICCR = 1; return 0; }
void __init pxa_init_irq(int irq_nr, set_wake_t fn) { int irq, i, n; BUG_ON(irq_nr > MAX_INTERNAL_IRQS); pxa_internal_irq_nr = irq_nr; for (n = 0; n < irq_nr; n += 32) { void __iomem *base = irq_base(n >> 5); __raw_writel(0, base + ICMR); /* disable all IRQs */ __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { /* initialize interrupt priority */ if (cpu_has_ipr()) __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); irq = PXA_IRQ(i); irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, handle_level_irq); irq_set_chip_data(irq, base); set_irq_flags(irq, IRQF_VALID); } } /* only unmasked interrupts kick us out of idle */ __raw_writel(1, irq_base(0) + ICCR); pxa_internal_irq_chip.irq_set_wake = fn; pxa_init_low_gpio_irq(fn); }
void __init pxa_init_irq(int irq_nr, set_wake_t fn) { int irq; pxa_internal_irq_nr = irq_nr; for (irq = 0; irq < irq_nr; irq += 32) { _ICMR(irq) = 0; /* disable all IRQs */ _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */ } /* only unmasked interrupts kick us out of idle */ ICCR = 1; for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) { set_irq_chip(irq, &pxa_internal_irq_chip); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } pxa_internal_irq_chip.set_wake = fn; }
static void pxa_unmask_low_gpio(unsigned int irq) { ICMR |= 1 << (irq - PXA_IRQ(0)); }
static void pxa_mask_low_gpio(unsigned int irq) { ICMR &= ~(1 << (irq - PXA_IRQ(0))); }
void __init pxa_init_irq(void) { int irq; /* disable all IRQs */ ICMR = 0; /* all IRQs are IRQ, not FIQ */ ICLR = 0; /* clear all GPIO edge detects */ GFER0 = 0; GFER1 = 0; GFER2 = 0; GRER0 = 0; GRER1 = 0; GRER2 = 0; GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; #ifdef CONFIG_PXA27x /* And similarly for the extra regs on the PXA27x */ ICMR2 = 0; ICLR2 = 0; GFER3 = 0; GRER3 = 0; GEDR3 = GEDR3; #endif /* only unmasked interrupts kick us out of idle */ ICCR = 1; /* GPIO 0 and 1 must have their mask bit always set */ GPIO_IRQ_mask[0] = 3; for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) { set_irq_chip(irq, &pxa_internal_chip_low); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } #if PXA_INTERNAL_IRQS > 32 for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) { set_irq_chip(irq, &pxa_internal_chip_high); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } #endif for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { set_irq_chip(irq, &pxa_low_gpio_chip); set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { set_irq_chip(irq, &pxa_muxed_gpio_chip); set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* Install handler for GPIO>=2 edge detect interrupts */ set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); }