/**
* PCie EP not present
*
*
* @param[in] CurrentEngine Pointer to engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
PcieTrainingNotPresent (
IN PCIe_ENGINE_CONFIG *CurrentEngine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) {
} else {
PcieRegisterWriteField (
PcieEngineGetParentWrapper (CurrentEngine),
WRAP_SPACE (PcieEngineGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
1,
FALSE,
Pcie
);
}
PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
/**
* Release training
*
*
* @param[in] CurrentEngine Pointer to engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
PcieTrainingRelease (
IN PCIe_ENGINE_CONFIG *CurrentEngine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 LinkTrainingState;
PcieRegisterWriteField (
PcieEngineGetParentWrapper (CurrentEngine),
WRAP_SPACE (PcieEngineGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
0,
FALSE,
Pcie
);
if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
LinkTrainingState = LinkStateCompliance;
} else {
LinkTrainingState = LinkStateDetectPresence;
}
PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie);
}
VOID
STATIC
PcieAlibSetPortInfoCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
ALIB_PORT_INFO_PACKAGE *PortInfoPackage;
UINT8 PortIndex;
PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer;
PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2;
PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane;
PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane;
PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane;
PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane;
PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId;
// PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieEngineGetParentWrapper (Engine)->WrapId);
PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130u | (PcieEngineGetParentWrapper (Engine)->WrapId);
PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug;
PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie);
}
/**
* Reduce link width
*
*
* @param[in] LinkWidth Link width
* @param[in] Engine Pointer to Engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyReduceLinkWidth (
IN UINT8 LinkWidth,
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_WRAPPER_CONFIG *Wrapper;
UINT32 LinkReversed;
UINT8 DeltaLinkWidthBitmap;
UINT32 LanesToDisable;
Wrapper = PcieEngineGetParentWrapper (Engine);
LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie);
DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1;
LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane + LinkWidth)));
PcieTopologyLaneControl (
DisableLanes,
LanesToDisable,
Wrapper,
Pcie
);
}
AGESA_STATUS
PcieFmMapPortPciAddress (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_WRAPPER_CONFIG *Wrapper;
UINT64 ConfigurationSignature;
Wrapper = PcieEngineGetParentWrapper (Engine);
if (Wrapper->WrapId == GPP_WRAP_ID) {
ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, Engine->Type.Port.CoreId);
if ((ConfigurationSignature == GPP_CORE_x4x2x1x1_ST) || (ConfigurationSignature == GPP_CORE_x4x2x2_ST)) {
//Enable device remapping
GnbLibPciIndirectRMW (
MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
0x20 | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
~(UINT32) (1 << 1),
0x0,
GnbLibGetHeader (Pcie)
);
}
}
if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) {
Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber;
Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber;
return AGESA_SUCCESS;
}
if (Engine->Type.Port.PortData.DeviceNumber == Engine->Type.Port.NativeDevNumber &&
Engine->Type.Port.PortData.FunctionNumber == Engine->Type.Port.NativeFunNumber) {
return AGESA_SUCCESS;
}
return AGESA_ERROR;
}
