/**
* Common Core Init
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieCommonCoreInit (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
UINTN Index;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n");
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) {
UINT32 Value;
Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (CoreId, CoreInitTable[Index].Reg),
Pcie
);
Value &= (~CoreInitTable[Index].Mask);
Value |= CoreInitTable[Index].Data;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (CoreId, CoreInitTable[Index].Reg),
Value,
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Exit\n");
}
}
/**
* Init core registers.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieEarlyCoreInitCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
UINTN Index;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitCZ Enter\n");
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
for (Index = 0; Index < CoreInitTableCZ.Length; Index++) {
UINT32 Value;
Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (CoreId, CoreInitTableCZ.Table[Index].Reg),
Pcie
);
Value &= (~CoreInitTableCZ.Table[Index].Mask);
Value |= CoreInitTableCZ.Table[Index].Data;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (CoreId, CoreInitTableCZ.Table[Index].Reg),
Value,
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitCZ Exit\n");
}
}
/**
* Cleanup reconfig
*
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieTopologyCleanUpReconfigCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_CORE_0101_STRUCT D0F0xE4_CORE_0101;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyCleanUpReconfigCZ Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
D0F0xE4_CORE_0101.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0101_ADDRESS),
Pcie
);
D0F0xE4_CORE_0101.Field.CONFIG_XFER_MODE = 0x1;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0101_ADDRESS),
D0F0xE4_CORE_0101.Value,
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyCleanUpReconfigCZ Exit\n");
}
/**
* Execute/clean up reconfiguration
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyExecuteReconfigV4 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
PCIe_SILICON_CONFIG *Silicon;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Enter\n");
PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie);
D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
Silicon = PcieConfigGetParentSilicon (Wrapper);
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xB8_ADDRESS,
D0F0xBC_x1F630_ADDRESS,
AccessWidth32,
(UINT32) ~D0F0xBC_x1F630_RECONF_WRAPPER_MASK,
Wrapper->WrapId << D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET,
GnbLibGetHeader (Pcie)
);
GnbSmuServiceRequestV4 (
Silicon->Address,
SMC_MSG_RECONFIGURE,
0,
GnbLibGetHeader (Pcie)
);
D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Exit\n");
}
}
AGESA_STATUS
STATIC
PcieTopologySetCoreConfigCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
OUT BOOLEAN *ConfigChanged,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
AGESA_STATUS Status;
D0F0xE4_WRAP_0080_STRUCT D0F0xE4_WRAP_0080;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetCoreConfigCZ Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
UINT64 ConfigurationSignature;
UINT8 NewConfigurationValue;
ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId);
Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue);
if (Status == AGESA_SUCCESS) {
D0F0xE4_WRAP_0080.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
Pcie
);
IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s Original configuration - %s\n",
PcieFmDebugGetWrapperNameString (Wrapper),
CoreId,
PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue),
PcieFmDebugGetCoreConfigurationString (Wrapper, (UINT8) D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig)
);
if (ConfigChanged != NULL) {
if (D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig != NewConfigurationValue) {
*ConfigChanged = TRUE;
}
}
D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig = NewConfigurationValue;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
D0F0xE4_WRAP_0080.Value,
FALSE,
Pcie
);
} else {
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n",
PcieFmDebugGetWrapperNameString (Wrapper),
((UINT32*)&ConfigurationSignature)[1],
((UINT32*)&ConfigurationSignature)[0]
);
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetCoreConfigCZ Exit\n");
return Status;
}
/**
* Execute/clean up reconfiguration
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyExecuteReconfigV5 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
PCIe_SILICON_CONFIG *Silicon;
DEV_OBJECT DevObject;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV5 Enter\n");
D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
D0F0xE4_WRAP_8062.Field.ResetPeriod = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
Silicon = PcieConfigGetParentSilicon (Wrapper);
DevObject.StdHeader = GnbLibGetHeader (Pcie);
DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie));
DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue;
GnbSmuServiceRequestV7 (
&DevObject,
SMC_MSG_RECONFIGURE,
Wrapper->WrapId,
0
);
D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV5 Exit\n");
}
}
/**
* Cleanup reconfig
*
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyCleanUpReconfig (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
if (PcieLibIsPcieWrapper (Wrapper)) {
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062_ConfigXferMode_MASK,
1 << D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET,
FALSE,
Pcie
);
}
}
/**
* Set SSID
*
*
* @param[in] Ssid SSID
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieSetSsidV4 (
IN UINT32 Ssid,
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
if (PcieLibIsPcieWrapper (Wrapper)) {
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0046_ADDRESS),
Ssid,
FALSE,
Pcie
);
}
}
/**
* Init core registers.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieEarlyCoreInitTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
UINTN Index;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Enter\n");
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
for (Index = 0; Index < CoreInitTableTN.Length; Index++) {
UINT32 Value;
Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg),
Pcie
);
Value &= (~CoreInitTableTN.Table[Index].Mask);
Value |= CoreInitTableTN.Table[Index].Data;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg),
Value,
FALSE,
Pcie
);
}
if (GnbBuildOptionsTN.CfgLinkBwNotificationEn == FALSE) {
PcieRegisterRMW (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_00C1_ADDRESS),
D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK,
0 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET,
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Exit\n");
}
}
AGESA_STATUS
PcieTopologySetCoreConfig (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
UINT64 ConfigurationSignature;
UINT8 NewConfigurationValue;
ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId);
Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue);
if (Status == AGESA_SUCCESS) {
IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s\n",
PcieFmDebugGetWrapperNameString (Wrapper),
CoreId,
PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue)
);
PcieRegisterWriteField (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET,
D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH,
NewConfigurationValue,
FALSE,
Pcie
);
} else {
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n",
PcieFmDebugGetWrapperNameString (Wrapper),
((UINT32*)&ConfigurationSignature)[1],
((UINT32*)&ConfigurationSignature)[0]
);
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
}
}
}
return Status;
}
/**
* Prepare for reconfiguration
*
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyPrepareForReconfig (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
UINT8 CoreId;
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
0xf,
FALSE,
Pcie
);
}
D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0;
D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
}
}
VOID
PcieAcsCapabilityWrapperEnableV4 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAcsCapabilityWrapperEnableV4 Enter\n");
if (!PcieLibIsPcieWrapper (Wrapper)) {
return;
}
//Step 1, Enable the ACS capability strap, which add ACS capability pointer to the PCIE extend capability list
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_00B0_ADDRESS),
D0F0xE4_CORE_00B0_Bitfield_6_6_OFFSET,
D0F0xE4_CORE_00B0_Bitfield_6_6_WIDTH,
0x1,
TRUE,
Pcie
);
}
//Step 2, Enable ACS capabilities strap, including sub-items, in WRP
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0000_ADDRESS),
D0F0xE4_WRAP_0000_Bitfield_24_24_MASK | D0F0xE4_WRAP_0000_Bitfield_25_25_MASK | D0F0xE4_WRAP_0000_Bitfield_26_26_MASK,
(0x1 << D0F0xE4_WRAP_0000_Bitfield_24_24_OFFSET) | (0x1 << D0F0xE4_WRAP_0000_Bitfield_25_25_OFFSET) | (0x1 << D0F0xE4_WRAP_0000_Bitfield_26_26_OFFSET),
TRUE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAcsCapabilityWrapperEnableV4 Exit\n");
}
VOID
PcieLockRegisters (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_HwInitWrLock_OFFSET,
D0F0xE4_CORE_0010_HwInitWrLock_WIDTH,
0x1,
TRUE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n");
}
VOID
STATIC
PcieTopologyApplyLaneMuxCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT32 Index;
UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorArrayCZ)];
UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorArrayCZ)];
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxCZ Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
LibAmdMemCopy (
&TxLaneMuxSelectorArray[0],
&LaneMuxSelectorArrayCZ[0],
sizeof (LaneMuxSelectorArrayCZ),
GnbLibGetHeader (Pcie)
);
LibAmdMemCopy (
&RxLaneMuxSelectorArray[0],
&LaneMuxSelectorArrayCZ[0],
sizeof (LaneMuxSelectorArrayCZ),
GnbLibGetHeader (Pcie)
);
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
UINT32 CoreLaneBitmap;
UINT32 PifLaneBitmap;
UINT8 CurrentCoreLane;
UINT8 CurrentPifLane;
CoreLaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_CORE_ALLOC, 0, EngineList);
PifLaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, EngineList);
IDS_HDT_CONSOLE (GNB_TRACE, "CoreLaneBitmap - %x, CurrentPifLane - %x\n", CoreLaneBitmap, PifLaneBitmap);
while (CoreLaneBitmap != 0) {
CurrentCoreLane = LibAmdBitScanForward (CoreLaneBitmap);
CurrentPifLane = LibAmdBitScanForward (PifLaneBitmap);
if (TxLaneMuxSelectorArray[CurrentPifLane] != CurrentCoreLane) {
TxLaneMuxSelectorArray[PcieTopologyLocateMuxIndexCZ (TxLaneMuxSelectorArray, CurrentCoreLane)] = TxLaneMuxSelectorArray[CurrentPifLane];
TxLaneMuxSelectorArray[CurrentPifLane] = CurrentCoreLane;
}
if (RxLaneMuxSelectorArray[CurrentCoreLane] != CurrentPifLane) {
RxLaneMuxSelectorArray[PcieTopologyLocateMuxIndexCZ (RxLaneMuxSelectorArray, CurrentPifLane)] = RxLaneMuxSelectorArray[CurrentCoreLane];
RxLaneMuxSelectorArray[CurrentCoreLane] = CurrentPifLane;
}
CoreLaneBitmap &= (~ (1 << CurrentCoreLane));
PifLaneBitmap &= (~ (1 << CurrentPifLane));
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
for (Index = 0; Index < 2; ++Index) {
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0121_ADDRESS + Index),
((UINT32 *) TxLaneMuxSelectorArray) [Index],
FALSE,
Pcie
);
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0125_ADDRESS + Index),
((UINT32 *) RxLaneMuxSelectorArray) [Index],
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxCZ Exit\n");
}
/**
* Configure engine list to support lane allocation according to configuration ID.
*
* PCIE port
*
*
* 1 Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
* 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG)
* 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
* 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG)
* 5 Check if lane can be muxed
*
*
* DDI Link
*
* 1 Check if lane from user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
* 2 Check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG)
*
*
*
* @param[in] ComplexDescriptor Pointer to used define complex descriptor
* @param[in,out] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
* @retval AGESA_SUCCESS Topology successfully mapped
* @retval AGESA_ERROR Topology can not be mapped
*/
AGESA_STATUS
PcieMapTopologyOnWrapper (
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
IN OUT PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_ENGINE_CONFIG *EngineList;
UINT32 WrapperPhyLaneBitMap;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Enter\n");
AgesaStatus = AGESA_SUCCESS;
if (PcieLibIsPcieWrapper (Wrapper)) {
Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_ERROR) {
// If we can not map topology on wrapper we can not enable any engines.
PutEventLog (
AGESA_ERROR,
GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION,
Wrapper->WrapId,
Wrapper->StartPhyLane,
Wrapper->EndPhyLane,
0,
GnbLibGetHeader (Pcie)
);
PcieConfigDisableAllEngines (PciePortEngine, Wrapper);
}
}
if (PcieLibIsDdiWrapper (Wrapper)) {
Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_ERROR) {
// If we can not map topology on wrapper we can not enable any engines.
PutEventLog (
AGESA_ERROR,
GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION,
Wrapper->WrapId,
Wrapper->StartPhyLane,
Wrapper->EndPhyLane,
0,
GnbLibGetHeader (Pcie)
);
PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper);
}
}
// Copy engine data
PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie);
EngineList = PcieConfigGetChildEngine (Wrapper);
// Verify if we oversubscribe lanes and PHY link width
WrapperPhyLaneBitMap = 0;
while (EngineList != NULL) {
UINT32 EnginePhyLaneBitMap;
if (PcieLibIsEngineAllocated (EngineList)) {
EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList);
if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) {
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n",
EngineList->EngineData.StartLane,
EngineList->EngineData.EndLane
);
PutEventLog (
AGESA_ERROR,
GNB_EVENT_INVALID_LANES_CONFIGURATION,
EngineList->EngineData.StartLane,
EngineList->EngineData.EndLane,
0,
0,
GnbLibGetHeader (Pcie)
);
PcieConfigDisableEngine (EngineList);
Status = AGESA_ERROR;
AGESA_STATUS_UPDATE (Status, AgesaStatus);
} else {
WrapperPhyLaneBitMap |= EnginePhyLaneBitMap;
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Exit [%d]\n", AgesaStatus);
return AgesaStatus;
}
VOID
PcieTopologyApplyLaneMux (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT8 CurrentPhyLane;
UINT8 CurrentCoreLane;
UINT8 CoreLaneIndex;
UINT8 PhyLaneIndex;
UINT8 NumberOfPhyLane;
UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
UINT8 Index;
UINT32 TxMaxSelectorValue;
UINT32 RxMaxSelectorValue;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
EngineList = PcieConfigGetChildEngine (Wrapper);
LibAmdMemCopy (
&TxLaneMuxSelectorArray[0],
&LaneMuxSelectorTable[0],
sizeof (LaneMuxSelectorTable),
GnbLibGetHeader (Pcie)
);
LibAmdMemCopy (
&RxLaneMuxSelectorArray[0],
&LaneMuxSelectorTable[0],
sizeof (LaneMuxSelectorTable),
GnbLibGetHeader (Pcie)
);
while (EngineList != NULL) {
if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList);
CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane;
if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) {
CurrentCoreLane = CurrentCoreLane + PcieConfigGetNumberOfCoreLane (EngineList) - NumberOfPhyLane;
}
for (Index = 0; Index < NumberOfPhyLane; Index = Index + 2 ) {
CoreLaneIndex = (CurrentCoreLane + Index) / 2;
PhyLaneIndex = (CurrentPhyLane + Index) / 2;
if (RxLaneMuxSelectorArray [CoreLaneIndex] != PhyLaneIndex) {
RxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (RxLaneMuxSelectorArray, PhyLaneIndex)] = RxLaneMuxSelectorArray [CoreLaneIndex];
RxLaneMuxSelectorArray [CoreLaneIndex] = PhyLaneIndex;
}
if (TxLaneMuxSelectorArray [PhyLaneIndex] != CoreLaneIndex) {
TxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (TxLaneMuxSelectorArray, CoreLaneIndex)] = TxLaneMuxSelectorArray [PhyLaneIndex];
TxLaneMuxSelectorArray [PhyLaneIndex] = CoreLaneIndex;
}
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
RxMaxSelectorValue = 0;
TxMaxSelectorValue = 0;
for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++) {
RxMaxSelectorValue |= (RxLaneMuxSelectorArray[Index] << (Index * 4));
TxMaxSelectorValue |= (TxLaneMuxSelectorArray[Index] << (Index * 4));
}
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS),
TxMaxSelectorValue,
FALSE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS),
RxMaxSelectorValue,
FALSE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Exit\n");
}
/**
* Execute/clean up reconfiguration
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyExecuteReconfig (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
D0F0xE4_WRAP_8060_STRUCT D0F0xE4_WRAP_8060;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n");
PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie);
D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
D0F0xE4_WRAP_8060.Value,
FALSE,
Pcie
);
do {
D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
Pcie
);
} while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1);
D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n");
}
}
/**
* Execute/clean up reconfiguration
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieTopologyExecuteReconfigCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_CORE_0101_STRUCT D0F0xE4_CORE_0101;
PCIe_SILICON_CONFIG *Silicon;
DEV_OBJECT DevObject;
UINT32 SmuArg[6];
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigCZ Enter\n");
D0F0xE4_CORE_0101.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
Pcie
);
D0F0xE4_CORE_0101.Field.RECONFIGURE_EN = 0x1;
D0F0xE4_CORE_0101.Field.RESET_PERIOD = 0x2;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
D0F0xE4_CORE_0101.Value,
FALSE,
Pcie
);
Silicon = PcieConfigGetParentSilicon (Wrapper);
DevObject.StdHeader = GnbLibGetHeader (Pcie);
DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie));
DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue;
LibAmdMemFill (SmuArg, 0x00, sizeof (SmuArg), GnbLibGetHeader (Pcie));
SmuArg [0] = Wrapper->WrapId;
GnbSmuServiceRequestV8 (
&DevObject,
SMC_MSG_RECONFIGURE_SB,
SmuArg,
0
);
D0F0xE4_CORE_0101.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
Pcie
);
D0F0xE4_CORE_0101.Field.RECONFIGURE_EN = 0x0;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
D0F0xE4_CORE_0101.Value,
FALSE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigCZ Exit\n");
}
}
