VOID
STATIC
PciePortInitCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
PciePortProgramRegisterTable (PortInitTable, (sizeof (PortInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, FALSE, Pcie);
PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie);
PcieSetLinkWidthCap (Engine, Pcie);
PcieCompletionTimeout (Engine, Pcie);
PcieLinkSetSlotCap (Engine, Pcie);
PcieLinkInitHotplug (Engine, Pcie);
PcieFmPhyChannelCharacteristic (Engine, Pcie);
if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
PcieLinkSafeMode (Engine, Pcie);
}
if (Engine->Type.Port.PortData.PortPresent == PortDisabled) {
ASSERT (Engine->Type.Port.IsSB == FALSE);
PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
// Train port that forced to compliance in last stage of training
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
}
}
VOID
STATIC
PcieEarlyPortInitCallbackTN (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Enter\n");
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
PciePortProgramRegisterTable (PortInitEarlyTableTN.Table, PortInitEarlyTableTN.Length, Engine, FALSE, Pcie);
PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie);
PcieSetLinkWidthCap (Engine, Pcie);
PcieCompletionTimeout (Engine, Pcie);
PcieLinkSetSlotCap (Engine, Pcie);
PcieLinkInitHotplug (Engine, Pcie);
if (Engine->Type.Port.PortData.PortPresent == PortDisabled ||
(Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent &&
Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced &&
Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) {
ASSERT (!PcieConfigIsSbPcieEngine (Engine));
//
// Pass endpoint status in scratch
//
PciePortRegisterRMW (
Engine,
DxF0xE4_x01_ADDRESS,
0x1,
0x1,
FALSE,
Pcie
);
PcieTrainingSetPortStateV1 (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieTrainingSetPortStateV1 (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Exit\n");
}
VOID
STATIC
PcieMidPortInitCallbackKV (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxFxx68_STRUCT DxFxx68;
D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
PCIe_SUBLINK_INFO *SublinkInfo;
PCIe_WRAPPER_INFO *WrapperInfo;
PCIe_WRAPPER_CONFIG *Wrapper;
CPU_LOGICAL_ID LogicalId;
UINT8 Count;
UINT8 Nibble;
PciePortProgramRegisterTable (PortInitMidTableKV.Table, PortInitMidTableKV.Length, Engine, TRUE, Pcie);
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
PcieEnableSlotPowerLimitV5 (Engine, Pcie);
if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) {
PcieInitPortForIommuV4 (Engine, Pcie);
}
// After GFX link is trained up and before ASPM is enabled, AGESA needs to check link width,
// if it equals to x16, then apply the following change to GFX port:
// Per port register 0xA1 - PCIE LC TRAINING CONTROL, bit16 - LC_EXTEND_WAIT_FOR_SKP = 1
GnbLibPciRead (
Engine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS,
AccessWidth32,
&DxFxx68,
GnbLibGetHeader (Pcie)
);
if (DxFxx68.Field.NegotiatedLinkWidth == 16) {
PciePortRegisterRMW (
Engine,
DxFxxE4_xA1_ADDRESS,
DxFxxE4_xA1_LcExtendWaitForSkp_MASK,
(1 << DxFxxE4_xA1_LcExtendWaitForSkp_OFFSET),
TRUE,
Pcie
);
}
}
Wrapper = PcieConfigGetParentWrapper (Engine);
SublinkInfo = &(((PCIe_INFO_BUFFER *)Buffer)->SublinkInfo[MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) / 4]);
WrapperInfo = &(((PCIe_INFO_BUFFER *)Buffer)->WrapperInfo[Wrapper->WrapId]);
GetLogicalIdOfCurrentCore (&LogicalId, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
// Check if this CPU is KV A0
// UBTS468566
if ((LogicalId.Revision & AMD_F15_KV_A0) != 0) {
Count = SublinkInfo->GppPortCount;
IDS_HDT_CONSOLE (GNB_TRACE, "x1x2 PortCount = %02x\n", Count);
if (Count == 2) {
// If number of GPP ports under the same sublink is 2, Delay L1 Exit (prolong minimum time spent in L1)
PciePortRegisterRMW (
Engine,
DxFxxE4_xA0_ADDRESS,
DxFxxE4_xA0_LcDelayCount_MASK |
DxFxxE4_xA0_LcDelayL1Exit_MASK,
(0 << DxFxxE4_xA0_LcDelayCount_OFFSET) |
(1 << DxFxxE4_xA0_LcDelayL1Exit_OFFSET),
TRUE,
Pcie
);
} else if (Count > 2) {
// If number of GPP ports > 2
if (SublinkInfo->MaxGenCapability > Gen1) {
// If at least 1 GPP is Gen2 capable, Disable PLL Power down feature
Wrapper = PcieConfigGetParentWrapper (Engine);
Nibble = (UINT8) ((MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) % 8) / 4);
// Only PSD and PPD can have x1/x2 links, so we assume that PIF number is always 0
D0F0xE4_PIF_0012.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + Nibble),
Pcie
);
D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0;
D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0;
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + Nibble),
D0F0xE4_PIF_0012.Value,
TRUE,
Pcie
);
} else {
// All ports are only Gen1
PciePortRegisterRMW (
Engine,
DxFxxE4_xC0_ADDRESS,
DxFxxE4_xC0_StrapMedyTSxCount_MASK,
0x2 << DxFxxE4_xC0_StrapMedyTSxCount_OFFSET,
TRUE,
Pcie
);
}
}
}
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0802_ADDRESS + (0x100 * Engine->Type.Port.PortId)),
D0F0xE4_WRAP_0802_StrapBifL1ExitLatency_MASK,
(WrapperInfo->L1ExitLatencyValue << D0F0xE4_WRAP_0802_StrapBifL1ExitLatency_OFFSET),
TRUE,
Pcie
);
if (WrapperInfo->DisableL1OnWrapper == TRUE) {
Engine->Type.Port.PortData.LinkAspm &= ~(AspmL1);
}
PcieEnableAspm (Engine, Pcie);
}
VOID
STATIC
PcieEarlyPortInitCallbackCZ (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackCZ Enter\n");
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
PciePortProgramRegisterTable (PortInitEarlyTableCZ.Table, PortInitEarlyTableCZ.Length, Engine, FALSE, Pcie);
IDS_OPTION_HOOK (IDS_GNB_EQUAL_PRESET, Engine, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie);
PcieSetLinkWidthCap (Engine, Pcie);
PcieCompletionTimeout (Engine, Pcie);
PcieLinkSetSlotCap (Engine, Pcie);
PcieLinkInitHotplugCZ (Engine, Pcie);
//Move EXTENDED_FMT_SUPPORTED stting from Mid to here.
PciePortRegisterRMW (
Engine,
DxFxxE4_xC1_ADDRESS,
DxFxxE4_xC1_StrapE2EPrefixEn_MASK | DxFxxE4_xC1_StrapExtendedFmtSupported_MASK,
(1 << DxFxxE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << DxFxxE4_xC1_StrapExtendedFmtSupported_OFFSET),
FALSE,
Pcie
);
if (Engine->Type.Port.PortData.PortPresent == PortDisabled ||
(Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent &&
Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced &&
Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) {
ASSERT (!PcieConfigIsSbPcieEngine (Engine));
//
// Pass endpoint status in scratch
//
PciePortRegisterRMW (
Engine,
DxFxxE4_x01_ADDRESS,
0x1,
0x1,
FALSE,
Pcie
);
PcieTrainingSetPortStateV2 (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
if (PcieConfigIsSbPcieEngine (Engine)) {
PcieTrainingSetPortStateV2 (Engine, LinkStateTrainingSuccess, FALSE, Pcie);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_001C_ADDRESS),
D0F0xE4_CORE_001C_TX_ATOMIC_OPS_DISABLE_OFFSET,
D0F0xE4_CORE_001C_TX_ATOMIC_OPS_DISABLE_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieTrainingSetPortStateV2 (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
}
IDS_OPTION_HOOK (IDS_GNB_GEN1_LOOPBACK, Engine, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackCZ Exit\n");
}
