static void SGXResetInvalDC(struct PVRSRV_SGXDEV_INFO *psDevInfo,
u32 ui32PDUMPFlags, IMG_BOOL bPDump)
{
u32 ui32RegVal;
ui32RegVal = EUR_CR_BIF_CTRL_INVALDC_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
if (bPDump)
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, bPDump);
ui32RegVal = 0;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
if (bPDump)
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, bPDump);
{
if (PollForValueKM
((u32 *)((u8 __force *)psDevInfo->pvRegsBaseKM +
EUR_CR_BIF_MEM_REQ_STAT), 0,
EUR_CR_BIF_MEM_REQ_STAT_READS_MASK,
MAX_HW_TIME_US / WAIT_TRY_COUNT,
WAIT_TRY_COUNT) != PVRSRV_OK)
PVR_DPF(PVR_DBG_ERROR,
"Wait for DC invalidate failed.");
if (bPDump)
PDUMPREGPOLWITHFLAGS(EUR_CR_BIF_MEM_REQ_STAT, 0,
EUR_CR_BIF_MEM_REQ_STAT_READS_MASK,
ui32PDUMPFlags);
}
}
/*!
*******************************************************************************
@Function SGXResetInvalDC
@Description
Invalidate the BIF Directory Cache and wait for the operation to complete.
@Input psDevInfo - SGX Device Info
@Input ui32PDUMPFlags - flags to control PDUMP output
@Return Nothing
******************************************************************************/
static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO *psDevInfo,
IMG_UINT32 ui32PDUMPFlags,
IMG_BOOL bPDump)
{
IMG_UINT32 ui32RegVal;
/* Invalidate BIF Directory cache. */
#if defined(EUR_CR_BIF_CTRL_INVAL)
ui32RegVal = EUR_CR_BIF_CTRL_INVAL_ALL_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL_INVAL, ui32RegVal);
if (bPDump)
{
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL_INVAL, ui32RegVal, ui32PDUMPFlags);
}
#else
ui32RegVal = EUR_CR_BIF_CTRL_INVALDC_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
if (bPDump)
{
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
}
ui32RegVal = 0;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
if (bPDump)
{
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
}
#endif
SGXResetSleep(psDevInfo, ui32PDUMPFlags, bPDump);
#if !defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
{
/*
Wait for the DC invalidate to complete - indicated by
outstanding reads reaching zero.
*/
if (PollForValueKM((IMG_UINT32 *)((IMG_UINT8*)psDevInfo->pvRegsBaseKM + EUR_CR_BIF_MEM_REQ_STAT),
0,
EUR_CR_BIF_MEM_REQ_STAT_READS_MASK,
MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"Wait for DC invalidate failed."));
PVR_DBG_BREAK;
}
if (bPDump)
{
PDUMPREGPOLWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_REQ_STAT, 0, EUR_CR_BIF_MEM_REQ_STAT_READS_MASK, ui32PDUMPFlags, PDUMP_POLL_OPERATOR_EQUAL);
}
}
#endif /* SGX_FEATURE_MULTIPLE_MEM_CONTEXTS */
}
static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO *psDevInfo,
IMG_UINT32 ui32PDUMPFlags,
IMG_BOOL bPDump)
{
IMG_UINT32 ui32RegVal;
#if defined(EUR_CR_BIF_CTRL_INVAL)
ui32RegVal = EUR_CR_BIF_CTRL_INVAL_ALL_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL_INVAL, ui32RegVal);
if (bPDump)
{
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL_INVAL, ui32RegVal, ui32PDUMPFlags);
}
#else
ui32RegVal = EUR_CR_BIF_CTRL_INVALDC_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
if (bPDump)
{
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
}
SGXResetSleep(psDevInfo, ui32PDUMPFlags, bPDump);
ui32RegVal = 0;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
if (bPDump)
{
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
}
#endif
SGXResetSleep(psDevInfo, ui32PDUMPFlags, bPDump);
#if !defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
{
if (PollForValueKM((IMG_UINT32 *)((IMG_UINT8*)psDevInfo->pvRegsBaseKM + EUR_CR_BIF_MEM_REQ_STAT),
0,
EUR_CR_BIF_MEM_REQ_STAT_READS_MASK,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
WAIT_TRY_COUNT) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"Wait for DC invalidate failed."));
PVR_DBG_BREAK;
}
if (bPDump)
{
PDUMPREGPOLWITHFLAGS(EUR_CR_BIF_MEM_REQ_STAT, 0, EUR_CR_BIF_MEM_REQ_STAT_READS_MASK, ui32PDUMPFlags);
}
}
#endif
}
