void DEX_REGION::process(OUT PRNO2UINT & prno2v, UINT param_num, UINT vregnum,
UINT2PR * v2pr, IN PRNO2UINT * pr2v, TYIDR * tr)
{
if (get_ir_list() == NULL) { return; }
OPT_CTX oc;
OPTC_show_comp_time(oc) = g_show_comp_time;
g_indent = 0;
note("\n==---- REGION_NAME:%s ----==", get_ru_name());
prescan(get_ir_list());
RU_is_pr_unique_for_same_no(this) = true;
//g_do_ssa = true;
PASS_MGR * pm = new_pass_mgr();
OPTC_pass_mgr(oc) = pm;
high_process(oc);
middle_process(oc);
IR_SSA_MGR * ssamgr = (IR_SSA_MGR*)pm->query_opt(OPT_SSA_MGR);
if (ssamgr != NULL && ssamgr->is_ssa_construct()) {
ssamgr->destruction_in_bblist_order();
}
delete pm;
OPTC_pass_mgr(oc) = NULL;
if (RU_type(this) != RU_FUNC) { return; }
IR_BB_LIST * bbl = get_bb_list();
if (bbl->get_elem_count() == 0) { return; }
IS_TRUE0(verify_ir_and_bb(bbl, get_dm()));
RF_CTX rf;
RC_insert_cvt(rf) = false; //Do not insert cvt for DEX code.
refine_ir_bb_list(bbl, rf);
IS_TRUE0(verify_ir_and_bb(bbl, get_dm()));
RA ra(this, tr, param_num, vregnum, v2pr, pr2v, &m_var2pr);
LOG("\t\tdo DEX Register Allcation for '%s'", get_ru_name());
ra.perform(oc);
update_ra_res(ra, prno2v);
}
//This function outputs Prno2Vreg after Dex register allocation.
bool DexRegion::process(OptCtx * oc)
{
if (getIRList() == NULL) { return true; }
OC_show_comp_time(*oc) = g_show_comp_time;
g_indent = 0;
if (!g_silence) {
LOG("DexRegion process %s", getRegionName());
}
//note("\n==---- REGION_NAME:%s ----==", getRegionName());
prescan(getIRList());
PassMgr * passmgr = initPassMgr();
HighProcess(*oc);
MiddleProcess(*oc);
ASSERT0(getPassMgr());
PRSSAMgr * ssamgr = (PRSSAMgr*)passmgr->queryPass(PASS_PR_SSA_MGR);
if (ssamgr != NULL && ssamgr->isSSAConstructed()) {
ssamgr->destruction();
}
if (!g_retain_pass_mgr_for_region) {
//Destroy PassMgr.
destroyPassMgr();
}
if (!is_function()) { return true; }
///////////////////////////////////////
//DO NOT REQUEST PASS AFTER THIS LINE//
///////////////////////////////////////
BBList * bbl = getBBList();
if (bbl->get_elem_count() == 0) { return true; }
ASSERT0(verifyIRandBB(bbl, this));
RefineCtx rf;
RC_insert_cvt(rf) = false; //Do not insert cvt for DEX code.
refineBBlist(bbl, rf);
ASSERT0(verifyIRandBB(bbl, this));
if (g_do_dex_ra) {
Prno2Vreg * original_prno2vreg = getDex2IR()->getPR2Vreg();
RA ra(this,
getTypeIndexRep(),
getParamNum(),
getOrgVregNum(),
getDex2IR()->getVreg2PR(),
original_prno2vreg,
&m_var2pr);
LOG("\t\tdo DEX Register Allcation for '%s'", getRegionName());
ra.perform(*oc);
updateRAresult(ra, *getPrno2Vreg());
} else {
//Do not allocate register.
getPrno2Vreg()->clean();
getPrno2Vreg()->copy(*getDex2IR()->getPR2Vreg());
}
return true;
}
void IR_CP::doFinalRefine()
{
RefineCtx rf;
RC_insert_cvt(rf) = false;
m_ru->refineBBlist(m_ru->get_bb_list(), rf);
}
