status_t CAN001_ReadMsgObj
(
const CAN001_HandleType* Handle,
CAN001_MessageHandleType* SwMsgObjptr,
uint8_t MsgObjnr
)
{
uint32_t Error = (uint32_t)CAN001_ERROR;
uint32_t Count = 0U;
bool RxPnd = 0U;
bool NewData = 0U;
uint8_t MsgNo = (uint8_t)(Handle->FirstMOMapping+(MsgObjnr-1U));
/* Mapping to message object offset value*/
CAN_MO_TypeDef* CAN_MOxRegs = \
GET_MO_OFFSET(MsgNo);
DBG002_N((MsgObjnr == 0U)||(MsgObjnr > Handle->NodeMONo));
/* check if message object is a receive message object */
/*<<<DD_CAN001_API_6_1>>>*/
if( RD_REG(CAN_MOxRegs->MOSTAT, CAN_MO_MOSTAT_DIR_Msk, \
CAN_MO_MOSTAT_DIR_Pos) != (uint32_t)RECMSGOBJ)
{
Error = (uint32_t)CAN001_MO_NOT_ACCEPTABLE;
DBG002_ERROR(APP_GID, DBG002_MESSAGEID_LITERAL, sizeof(Error), &Error);
}
/* check if reception is ongoing on message object */
/*<<<DD_CAN001_API_6_2>>>*/
else if( RD_REG(CAN_MOxRegs->MOSTAT, CAN_MO_MOSTAT_RXUPD_Msk, \
CAN_MO_MOSTAT_RXUPD_Pos) == 1U)
{
Error = (uint32_t)CAN001_MO_BUSY;
DBG002_ERROR(APP_GID, DBG002_MESSAGEID_LITERAL, sizeof(Error), &Error);
}
else
{
/* read message parameters */
/*<<<DD_CAN001_API_6_3>>>*/
do
{
CAN_MOxRegs->MOCTR = CAN_MO_MOCTR_RESNEWDAT_Msk;
if((RD_REG(CAN_MOxRegs->MOAR, CAN_MO_MOAR_IDE_Msk , \
CAN_MO_MOAR_IDE_Pos)) == 0U)
{
SwMsgObjptr->IDExten = (uint8_t)STANDARDTYPE;
SwMsgObjptr->Identifier = (CAN_MOxRegs->MOAR & (uint32_t)CAN_MO_MOAR_STDID_Msk) >> \
CAN_MO_MOAR_STDID_Pos;
SwMsgObjptr->IDEMask = (uint8_t)((uint32_t)(CAN_MOxRegs->MOAMR & (uint32_t)CAN_MO_MOAMR_MIDE_Msk) >> \
CAN_MO_MOAMR_MIDE_Pos);
if(SwMsgObjptr->IDEMask == 1U)
{
SwMsgObjptr->IDMask = (CAN_MOxRegs->MOAMR & (uint32_t)CAN_MO_MOAR_STDID_Msk) >> \
CAN_MO_MOAR_STDID_Pos;
}
else
{
SwMsgObjptr->IDMask = CAN_MOxRegs->MOAMR & (uint32_t)CAN_MO_MOAMR_AM_Msk;
}
}
else
{
void MATH_IRQHandler(void)
{
uint32_t CordicEvent, DivEvent;
DivEvent = RD_REG(MATH->EVFR, MATH_EVFR_DIVEOC_Msk, MATH_EVFR_DIVEOC_Pos);
/* High precedence for DIV event. DIV event should be executed before CORDIC
* event. Execution of FASTMATH01_tan() & FASTMATH01_tanh() result in both
* DIV & CORDIC end of calculations events. The results of these functions are
* the output of DIV operation. For this case DIV event should be
* handled first to return the result (QUOT register) of these functions. */
if(DivEvent)
{
/* Clear Divider End of Calculation Event Flag */
SET_BIT(MATH->EVFCR, MATH_EVFCR_DIVEOCC_Pos);
MATH_DIV_lIRQHandler();
}
CordicEvent = RD_REG(MATH->EVFR, MATH_EVFR_CDEOC_Msk,
MATH_EVFR_CDEOC_Pos);
/* Low precedence for CORDIC interrupt */
if(CordicEvent)
{
/* Clear CORDIC End of Calculation Event Flag*/
SET_BIT(MATH->EVFCR, MATH_EVFCR_CDEOCC_Pos);
MATH_CORDIC_lIRQHandler();
}
}
/*
* This function used to read the No_of_bytes
* from the specified address
*/
status_t FLASH003_ReadBytes(uint32_t Address, uint8_t buf[],\
uint32_t No_of_bytes)
{
FLASH003Status_Type status;
const FLASH003_HandleType* Handle;
uint32_t lByte_Cnt;
uint32_t rd1;
uint32_t rd2;
uint32_t rd3;
Handle = &FLASH003_Handle0;
/*This is to check weather the last byte of data is crossing the max limit
*of the flash or not.
*/
uint32_t final_add_location;
status = FLASH003_IN_PROGRESS;
/*calculation of the last byte address*/
final_add_location = (uint32_t)((uint32_t)Address + \
(uint32_t)No_of_bytes) - 1U;
rd1 = RD_REG(Handle->FlashRegsPtr->NVMPROG,NVM_NVMPROG_ACTION_Msk,\
NVM_NVMPROG_ACTION_Pos);
rd2 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_BUSY_Msk,\
NVM_NVMSTATUS_BUSY_Pos);
rd3 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_SLEEP_Msk,\
NVM_NVMSTATUS_SLEEP_Pos);
/*validate the Address for Range and Block Alignment*/
if ((Address < Handle->kStart_Address) || (Address > Handle->kEnd_Address)\
|| (final_add_location > Handle->kEnd_Address))
{
status = FLASH003_INVALID_ADDRESS;
}
/*Checking for the status of Flash for Idle and Sleep Mode*/
else if((rd1 == FLASH003_RESET) && (rd2 == FLASH003_RESET) && \
(rd3 == FLASH003_RESET))
{
/* reads no of bytes specified*/
for(lByte_Cnt = 0U;lByte_Cnt < (uint32_t)No_of_bytes;lByte_Cnt++)
{
/* reads one byte*/
*(buf + lByte_Cnt) = *((uint8_t*)Address + lByte_Cnt);
status = FLASH003_COMPLETE;
}
rd1 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_ECC1READ_Msk,\
NVM_NVMSTATUS_ECC1READ_Pos);
rd2 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_ECC2READ_Msk,\
NVM_NVMSTATUS_ECC2READ_Pos);
/*Checking for ECC error flags*/
if((rd1 != FLASH003_RESET) || (rd2 != FLASH003_RESET))
{
status = FLASH003_ERROR;
}
}
else
{
status = FLASH003_ERROR;
}
return (uint32_t)status;
}
/*
* This function used to read the Block
* from the specified address
*/
status_t FLASH003_ReadBlock(uint32_t Address,uint32_t buf[])
{
FLASH003Status_Type status;
uint32_t lWord_Cnt;
const FLASH003_HandleType* Handle;
uint32_t rd1;
uint32_t rd2;
uint32_t rd3;
status = FLASH003_IN_PROGRESS;
Handle = &FLASH003_Handle0;
rd1 = RD_REG(Handle->FlashRegsPtr->NVMPROG,NVM_NVMPROG_ACTION_Msk,\
NVM_NVMPROG_ACTION_Pos);
rd2 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_BUSY_Msk,\
NVM_NVMSTATUS_BUSY_Pos);
rd3 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_SLEEP_Msk,\
NVM_NVMSTATUS_SLEEP_Pos);
/*validate the Address for Range and Block Alignment*/
if ((Address < Handle->kStart_Address) || (Address > Handle->kEnd_Address) \
|| ((Address & FLASH003_BLOCK_ALIGN_CHECK) != 0U))
{
status = FLASH003_INVALID_ADDRESS;
}
/*Checking for the status of Flash for Idle and Sleep Mode*/
else if((rd1 == FLASH003_RESET) && (rd2 == FLASH003_RESET) && \
(rd3 == FLASH003_RESET))
{
/* reads one Block*/
for(lWord_Cnt = 0U;lWord_Cnt < (uint32_t)FLASH003_WORD_SIZE;lWord_Cnt++)
{
/* reads one word*/
*(buf + lWord_Cnt) = *((uint32_t*)Address + lWord_Cnt);
status = FLASH003_COMPLETE;
}
rd1 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,\
NVM_NVMSTATUS_ECC1READ_Msk,NVM_NVMSTATUS_ECC1READ_Pos);
rd2 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,\
NVM_NVMSTATUS_ECC2READ_Msk,NVM_NVMSTATUS_ECC2READ_Pos);
/*Checking for ECC error flags*/
if((rd1 != FLASH003_RESET) || (rd2 != FLASH003_RESET))
{
status = FLASH003_ERROR;
}
}
else
{
status = FLASH003_ERROR;
}
return (uint32_t)status;
}
/**
* This function checks whether given interrupt is set
*/
status_t CNT001_GetPendingEvent
(
const CNT001_HandleType * HandlePtr,
const CNT001_EventNameType Event,
uint8_t* EvtStatus
)
{
status_t Status = (uint32_t)CNT001_OPER_NOT_ALLOWED_ERROR;
CCU4_CC4_TypeDef* CC4yRegsPtr = HandlePtr->CC4Ptr;
DBG002_FUNCTION_ENTRY(APP_GID, (uint32_t)CNT001_FUNCTION_ENTRY);
if (HandlePtr->DynamicHandlePtr->State == CNT001_UNINITIALIZED)
{
DBG002_INFO(APP_GID, DBG002_MESSAGEID_LITERAL, CNT001_STATUS_LEN, &status);
}
else
{
if(RD_REG(CC4yRegsPtr->INTS, ((uint32_t)0x01<<(uint8_t)Event),(uint8_t)Event))
{
*EvtStatus = (uint8_t)SET;
}
else
{
*EvtStatus = (uint8_t)RESET;
}
/* *EvtStatus = RD_REG(CC4yRegsPtr->INTS, (0x01<<(uint8_t)Event),(uint8_t)Event) ?\
(uint8_t)SET : (uint8_t)RESET; */
Status = (uint32_t)DAVEApp_SUCCESS;
}
DBG002_FUNCTION_EXIT(APP_GID, (uint32_t)CNT001_FUNCTION_EXIT);
return (Status);
}
/*
* The function is local to Flash app
* used to write the block of data
*/
void FLASH003_lWriteBlock (uint32_t Address, const uint32_t pBuf[])
{
uint32_t lWord_Cnt;
const FLASH003_HandleType* Handle;
Handle = &FLASH003_Handle0;
/*updating the ACTION with Oneshot Write and Auto Verify*/
WR_REG(Handle->FlashRegsPtr->NVMPROG,NVM_NVMPROG_ACTION_Msk,\
NVM_NVMPROG_ACTION_Pos,FLASH003_ONESHOT_WRITE_AUTOVERIFY);
/*Writing a Block of Data*/
for(lWord_Cnt = 0U;lWord_Cnt < FLASH003_WORD_SIZE;lWord_Cnt++)
{
*((uint32_t *) (Address + (FLASH003_WORD_SIZE * lWord_Cnt) )) = \
pBuf[lWord_Cnt];
}
#if (FLASH003_SEQ_INTERRUPT != FLASH003_INTR_ENABLED)
/*Polling Busy Flag until Idle State*/
while(RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_BUSY_Msk,\
NVM_NVMSTATUS_BUSY_Pos) != FLASH003_RESET)
{
;
}
/*Wait for 10us to complete the verification(need to check)*/
WR_REG(SCU_CLK->CLKCR, SCU_CLK_CLKCR_CNTADJ_Msk, SCU_CLK_CLKCR_CNTADJ_Pos,\
FLASH003_DELAY);
while (SCU_CLK->CLKCR&(SCU_CLK_CLKCR_VDDC2LOW_Msk))
{
;
}
#endif
}
/*
* This function used to read a word
* from the specified address
*/
status_t FLASH003_ReadWord(uint32_t Address,uint32_t* buf)
{
FLASH003Status_Type status;
const FLASH003_HandleType* Handle;
uint32_t rd1;
uint32_t rd2;
uint32_t rd3;
Handle = &FLASH003_Handle0;
status = FLASH003_IN_PROGRESS;
rd1 = RD_REG(Handle->FlashRegsPtr->NVMPROG,NVM_NVMPROG_ACTION_Msk,\
NVM_NVMPROG_ACTION_Pos);
rd2 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_BUSY_Msk,\
NVM_NVMSTATUS_BUSY_Pos);
rd3 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_SLEEP_Msk,\
NVM_NVMSTATUS_SLEEP_Pos);
/*validate the Address for Range*/
if ((Address < Handle->kStart_Address) || (Address > Handle->kEnd_Address))
{
status = FLASH003_INVALID_ADDRESS;
}
/*Checking for the status of Flash for Idle and Sleep Mode*/
else if((rd1 == FLASH003_RESET) && (rd2 == FLASH003_RESET) && \
(rd3 == FLASH003_RESET))
{
/* reads one word*/
*buf = *((uint32_t*)Address);
status = FLASH003_COMPLETE;
rd1 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_ECC1READ_Msk,\
NVM_NVMSTATUS_ECC1READ_Pos);
rd2 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_ECC2READ_Msk,\
NVM_NVMSTATUS_ECC2READ_Pos);
/*Checking for ECC error flags*/
if((rd1 != FLASH003_RESET) || (rd2 != FLASH003_RESET))
{
status = FLASH003_ERROR;
}
}
else
{
status = FLASH003_ERROR;
}
return (uint32_t)status;
}
status_t CAN001_SendRemoteFrame(const CAN001_HandleType* Handle, uint8_t MsgObjnr)
{
uint32_t Error = 0U;
uint8_t MsgNo = (uint8_t)(Handle->FirstMOMapping+(MsgObjnr-1U));
/* Mapping to message object offset value*/
CAN_MO_TypeDef* CAN_MOxRegs = \
GET_MO_OFFSET(MsgNo);
/*<<<DD_CAN001_API_5>>>*/
DBG002_FUNCTION_ENTRY(DBG002_GID_CAN001,CAN001_FUNCTION_ENTRY);
DBG002_N ((MsgObjnr == 0U)||(MsgObjnr > Handle->NodeMONo));
/* check if message object is a receive message object */
/*<<<DD_CAN001_API_5_1>>>*/
if( RD_REG(CAN_MOxRegs->MOSTAT, CAN_MO_MOSTAT_DIR_Msk, \
CAN_MO_MOSTAT_DIR_Pos) != (uint32_t)RECMSGOBJ)
{
Error = (uint32_t)CAN001_MO_NOT_ACCEPTABLE;
DBG002_ERROR(DBG002_GID_CAN001,Error, 0, NULL);
}
/* check if message is disabled */
else if( RD_REG(CAN_MOxRegs->MOSTAT, CAN_MO_MOSTAT_MSGVAL_Msk, \
CAN_MO_MOSTAT_MSGVAL_Pos) == 0U)
{
Error = (uint32_t)CAN001_MSGOBJ_DISABLED;
DBG002_INFO(DBG002_GID_CAN001,Error, 0, NULL);
}
/* check if transmission is ongoing on message object */
/*<<<DD_CAN001_API_5_2>>>*/
else if( RD_REG(CAN_MOxRegs->MOSTAT, CAN_MO_MOSTAT_TXRQ_Msk, \
CAN_MO_MOSTAT_TXRQ_Pos) == 1U)
{
Error = (uint32_t)CAN001_MO_BUSY;
DBG002_INFO(DBG002_GID_CAN001,Error, 0, NULL);
}
else
{
/* Put transmit request to message object */
/*<<<DD_CAN001_API_5_3>>>*/
CAN_MOxRegs->MOCTR = CAN_MO_MOCTR_SETTXRQ_Msk;
Error = (uint32_t)DAVEApp_SUCCESS;
}
DBG002_FUNCTION_EXIT(DBG002_GID_CAN001,CAN001_FUNCTION_EXIT);
return Error;
}
status_t CAN001_SendDataFrame(const CAN001_HandleType* Handle, uint8_t MsgObjnr)
{
uint32_t Error = (uint32_t)CAN001_ERROR;
uint8_t MsgNo = (uint8_t)(Handle->FirstMOMapping+(MsgObjnr-1U));
/* Mapping to message object offset value*/
CAN_MO_TypeDef* CAN_MOxRegs = \
GET_MO_OFFSET(MsgNo);
DBG002_N((MsgObjnr == 0U)||(MsgObjnr > Handle->NodeMONo));
/* check if message object is not a transmit message object */
/*<<<DD_CAN001_API_4_1>>>*/
if( RD_REG(CAN_MOxRegs->MOSTAT, CAN_MO_MOSTAT_DIR_Msk, \
CAN_MO_MOSTAT_DIR_Pos) != (uint32_t)TRANSMSGOBJ)
{
Error = (uint32_t)CAN001_MO_NOT_ACCEPTABLE;
DBG002_ERROR(APP_GID, DBG002_MESSAGEID_LITERAL, sizeof(Error), &Error);
}
/* check if message is disabled */
else if( RD_REG(CAN_MOxRegs->MOSTAT, CAN_MO_MOSTAT_MSGVAL_Msk, \
CAN_MO_MOSTAT_MSGVAL_Pos) == 0U)
{
Error = (uint32_t)CAN001_MSGOBJ_DISABLED;
DBG002_INFO(APP_GID, DBG002_MESSAGEID_LITERAL, sizeof(Error), &Error);
}
/* check if transmission is ongoing on message object */
/*<<<DD_CAN001_API_4_2>>>*/
else if( RD_REG(CAN_MOxRegs->MOSTAT, CAN_MO_MOSTAT_TXRQ_Msk, \
CAN_MO_MOSTAT_TXRQ_Pos) == 1U)
{
Error = (uint32_t)CAN001_MO_BUSY;
DBG002_INFO(APP_GID, DBG002_MESSAGEID_LITERAL, sizeof(Error), &Error);
}
else
{
/* set TXRQ bit */
/*<<<DD_CAN001_API_4_3>>>*/
CAN_MOxRegs->MOCTR = CAN_MO_MOCTR_SETTXRQ_Msk;
Error = (uint32_t)DAVEApp_SUCCESS;
}
return Error;
}
/**
* This function reads the compare match status (ST bit) of the given slice.
*/
status_t PWMSP003_GetCompareMatchStatus(const PWMSP003_HandleType * HandlePtr,
uint8_t * CompareMatchStatus)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
if (HandlePtr->DynamicDataType->StateType != PWMSP003_UNINITIALIZED)
{
*CompareMatchStatus = (uint32_t) RD_REG(HandlePtr->CC4yKernRegsPtr->GCST,\
(CCU4_GCST_CC40ST_Msk << (uint32_t)HandlePtr->Slice),\
(CCU4_GCST_CC40ST_Pos + (uint32_t)HandlePtr->Slice));
Status = (uint32_t)DAVEApp_SUCCESS;
}
return Status;
}
/**
* This function returns the timer status - Running or Idle
*/
status_t PWMSP003_GetTimerStatus(const PWMSP003_HandleType * HandlePtr,
uint32_t* TimerStatus)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
if (HandlePtr->DynamicDataType->StateType != PWMSP003_UNINITIALIZED)
{
*TimerStatus = (uint32_t) RD_REG(HandlePtr->CC4yRegsPtr->TCST,
CCU4_CC4_TCST_TRB_Msk, CCU4_CC4_TCST_TRB_Pos);
Status = (uint32_t)DAVEApp_SUCCESS;
}
return Status;
}
void alpha8201_cpu_device::state_export(const device_state_entry &entry)
{
switch (entry.index())
{
case STATE_GENFLAGS:
m_flags = (m_cf << 1) | m_zf;
break;
case ALPHA8201_SP:
case STATE_GENSP:
m_sp = M_RDMEM(0x001);
break;
case ALPHA8201_R0:
m_R[0] = RD_REG(0);
break;
case ALPHA8201_R1:
m_R[1] = RD_REG(1);
break;
case ALPHA8201_R2:
m_R[2] = RD_REG(2);
break;
case ALPHA8201_R3:
m_R[3] = RD_REG(3);
break;
case ALPHA8201_R4:
m_R[4] = RD_REG(4);
break;
case ALPHA8201_R5:
m_R[5] = RD_REG(5);
break;
case ALPHA8201_R6:
m_R[6] = RD_REG(6);
break;
case ALPHA8201_R7:
m_R[7] = RD_REG(7);
break;
}
}
/**
* This function reads the requested event status for the given slice
*/
status_t PWMSP003_GetInterruptStatus(const PWMSP003_HandleType * HandlePtr,
PWMSP003_InterruptType Event,
uint8_t * InterruptStatus)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
if (HandlePtr->DynamicDataType->StateType != PWMSP003_UNINITIALIZED)
{
*InterruptStatus = (uint32_t) RD_REG(HandlePtr->CC4yRegsPtr->INTS,\
(CCU4_CC4_INTS_PMUS_Msk << (uint32_t)Event),\
(CCU4_CC4_INTS_PMUS_Pos + (uint32_t)Event));
Status = (uint32_t)DAVEApp_SUCCESS;
}
return Status;
}
/**
* This function reads the counting direction of the given slice
*/
status_t PWMSP003_GetCountingDirection(const PWMSP003_HandleType * HandlePtr,
PWMSP003_CountDirectionType * CountDir)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
if ((HandlePtr->DynamicDataType->StateType != PWMSP003_UNINITIALIZED))
{
*CountDir =
(PWMSP003_CountDirectionType)RD_REG(HandlePtr->CC4yRegsPtr->TCST,\
CCU4_CC4_TCST_CDIR_Msk,
CCU4_CC4_TCST_CDIR_Pos);
Status = (uint32_t)DAVEApp_SUCCESS;
}
return Status;
}
/**
* This function reads the idle status of the given CCU4 slice
*/
status_t PWMSP003_GetSliceIdleStatus(const PWMSP003_HandleType * HandlePtr,
uint32_t * State)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
if(HandlePtr->DynamicDataType->StateType != PWMSP003_UNINITIALIZED)
{
/* Get the slice idle status */
*State = (uint32_t)RD_REG(HandlePtr->CC4yKernRegsPtr->GSTAT,\
(uint32_t)(CCU4_GSTAT_S0I_Msk << (uint32_t)HandlePtr->Slice),\
(uint32_t)(CCU4_GSTAT_S0I_Pos + (uint32_t)HandlePtr->Slice));
Status = (uint32_t)DAVEApp_SUCCESS;
}
return Status;
}
/**
* This function reads the shadow transfer status of the given slice
*/
status_t PWMSP003_GetShadowTransferStatus(const PWMSP003_HandleType * HandlePtr,
PWMSP003_ShadowTransferType Function,
uint8_t * State)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
if (HandlePtr->DynamicDataType->StateType != PWMSP003_UNINITIALIZED)
{
*State = (uint8_t)RD_REG(HandlePtr->CC4yKernRegsPtr->GCST,\
(uint32_t)(CCU4_GCST_S0SS_Msk << (uint32_t)Function),
(uint32_t)(CCU4_GCST_S0SS_Pos + (uint32_t)Function));
Status = (uint32_t)DAVEApp_SUCCESS;
}
return Status;
}
/**
* This function returns the timer registers of the given slice
*/
status_t PWMSP003_GetTimerValue(const PWMSP003_HandleType * HandlePtr,
PWMSP003_TimerRegsType* TimerRegs)
{
status_t Status = (uint32_t)PWMSP003_OPER_NOT_ALLOWED_ERROR;
if (HandlePtr->DynamicDataType->StateType != PWMSP003_UNINITIALIZED)
{
TimerRegs->TimerReg = (uint32_t)RD_REG(HandlePtr->CC4yRegsPtr->TIMER,
CCU4_CC4_TIMER_TVAL_Msk, CCU4_CC4_TIMER_TVAL_Pos);
TimerRegs->CompReg = HandlePtr->CC4yRegsPtr->CRS;
TimerRegs->PeriodReg = HandlePtr->CC4yRegsPtr->PRS;
Status = (uint32_t)DAVEApp_SUCCESS;
}
return Status;
}
/* This Function gets the timer count value which is the number of events counted till now */
status_t CNT001_GetEvtCountValue(const CNT001_HandleType *HandlePtr, uint32_t *NumEvents )
{
status_t status = (uint32_t)CNT001_OPER_NOT_ALLOWED_ERROR;
CCU4_CC4_TypeDef *CCU4Ptr; /* Pointer to the CCU4 Register set */
CCU4Ptr = HandlePtr->CC4Ptr;
DBG002_FUNCTION_ENTRY(APP_GID, (uint32_t)CNT001_FUNCTION_ENTRY);
/*<<<DD_CNT001_API_5_1>>>*/
if (HandlePtr->DynamicHandlePtr->State == CNT001_UNINITIALIZED)
{
DBG002_INFO(APP_GID, DBG002_MESSAGEID_LITERAL, CNT001_STATUS_LEN, &status);
}
else
{
*NumEvents = RD_REG(CCU4Ptr->TIMER, (uint32_t)CCU4_CC4_TIMER_TVAL_Msk,\
(uint32_t)CCU4_CC4_TIMER_TVAL_Pos);
status = (uint32_t)DAVEApp_SUCCESS;
}
DBG002_FUNCTION_EXIT(APP_GID, (uint32_t)CNT001_FUNCTION_EXIT);
return status;
}
/* This Function reads the timer status */
status_t CNT001_GetTimerStatus(const CNT001_HandleType *HandlePtr, uint32_t* Status)
{
status_t status = (uint32_t)CNT001_OPER_NOT_ALLOWED_ERROR;
CCU4_CC4_TypeDef *CCU4Ptr; /* Pointer to the CCU4 Register set */
CCU4Ptr = HandlePtr->CC4Ptr;
DBG002_FUNCTION_ENTRY(APP_GID, (uint32_t)CNT001_FUNCTION_ENTRY);
/*<<<DD_CNT001_API_8_1>>> */
if (HandlePtr->DynamicHandlePtr->State == CNT001_UNINITIALIZED)
{
DBG002_INFO(APP_GID, DBG002_MESSAGEID_LITERAL, CNT001_STATUS_LEN, &status);
}
else
{
/*<<<DD_CNT001_API_8_2>>> */
/* Get the Status of the Timer */
*Status = RD_REG( CCU4Ptr->TCST, (uint32_t)CCU4_CC4_TCST_TRB_Msk,\
(uint32_t)CCU4_CC4_TCST_TRB_Pos);
status = (uint32_t)DAVEApp_SUCCESS;
}
DBG002_FUNCTION_EXIT(APP_GID, (uint32_t)CNT001_FUNCTION_EXIT);
return status;
}
/* SCU Interrupt Handler.
*
*/
void SCU_0_IRQHandler(void)
{
NVIC_SCU001_CallbackType UserCallback;
NVIC_SCU001_HandleType* Handle = &NVIC_SCU001_Handle0;
uint32_t callbackArg = 0;
uint32_t IrqActive= 0;
/* read the interrupt status Register */
IrqActive = SCU_INTERRUPT->SRSTAT;
/* WDT pre-warning Interrupt */
if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_PRWARN_Msk, SCU_INTERRUPT_SRSTAT_PRWARN_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_PRWARN].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_PRWARN].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_PRWARN].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_PRWARN_Msk;
}
/* RTC Periodic Interrupt */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_PI_Msk, SCU_INTERRUPT_SRSTAT_PI_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_PI].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_PI].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_PI].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_PI_Msk;
}
/* RTC Alarm Interrupt */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_AI_Msk, SCU_INTERRUPT_SRSTAT_AI_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_AI].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_AI].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_AI].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_AI_Msk;
}
/* DLR Request Overrun Interrupt */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_DLROVR_Msk, SCU_INTERRUPT_SRSTAT_DLROVR_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_DLROVR].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_DLROVR].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_DLROVR].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_DLROVR_Msk;
}
/* HDSTAT Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_HDSTAT_Msk, SCU_INTERRUPT_SRSTAT_HDSTAT_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_HDSTAT].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_HDSTAT].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_HDSTAT].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_HDSTAT_Msk;
}
/* HDCLR Mirror Register Update */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_HDCLR_Msk, SCU_INTERRUPT_SRSTAT_HDCLR_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_HDCLR].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_HDCLR].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_HDCLR].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_HDCLR_Msk;
}
/* HDSET Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_HDSET_Msk, SCU_INTERRUPT_SRSTAT_HDSET_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_HDSET].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_HDSET].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_HDSET].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_HDSET_Msk;
}
/* HDCR Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_HDCR_Msk, SCU_INTERRUPT_SRSTAT_HDCR_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_HDCR].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_HDCR].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_HDCR].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_HDCR_Msk;
}
/* OSCSITRIM Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_OSCSITRIM_Msk, SCU_INTERRUPT_SRSTAT_OSCSITRIM_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_OSCSITRIM].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_OSCSITRIM].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_OSCSITRIM].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_OSCSITRIM_Msk;
}
/* OSCSICTRL Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk, SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_OSCSICTRL].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_OSCSICTRL].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_OSCSICTRL].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk;
}
/* OSCULSTAT Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_OSCULSTAT_Msk, SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_OSCULSTAT].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_OSCULSTAT].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_OSCULSTAT].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_OSCULSTAT_Msk;
}
/* OSCULCTRL Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk, SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_OSCULCTRL].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_OSCULCTRL].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_OSCULCTRL].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk;
}
/* RTC_CTR Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk, SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_RTC_CTR].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_RTC_CTR].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_RTC_CTR].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_RTC_CTR_Msk;
}
/* RTC_ATIM0 Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk, SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_RTC_ATIM0].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_RTC_ATIM0].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_RTC_ATIM0].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk;
}
/* RTC_ATIM1 Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk, SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_RTC_ATIM1].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_RTC_ATIM1].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_RTC_ATIM1].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk;
}
/* RTC_TIM0 Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk, SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_RTC_TIM0].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_RTC_TIM0].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_RTC_TIM0].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk;
}
/* RTC_TIM1 Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk, SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_RTC_TIM1].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_RTC_TIM1].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_RTC_TIM1].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk;
}
/* Retention Memory Mirror Register Update Status */
else if(RD_REG(IrqActive,SCU_INTERRUPT_SRSTAT_RMX_Msk, SCU_INTERRUPT_SRSTAT_RMX_Pos))
{
/* run the listener function */
if(Handle->SCU[NVIC_SCU001_RMX].CbListener != NULL)
{
UserCallback = Handle->SCU[NVIC_SCU001_RMX].CbListener;
callbackArg = Handle->SCU[NVIC_SCU001_RMX].CbArg;
UserCallback(callbackArg);
}
/* clear the interrupt */
SCU_INTERRUPT->SRCLR |= SCU_INTERRUPT_SRCLR_RMX_Msk;
}
else
{
/* If we've reached this point, either the enabling and
* disabling of SCU interrupts is not being handled
* properly or this function is being called unnecessarily.
*/
}
}
void DAVE_MUX_Init(void)
{
/* SCU Macro definitions */
//********* MODULE USIC CONFIGURATIONS *************************
/* Disable mode before configuring all USIC registers to avoid unintended edges */
/* Variable to store the CCR_MODE values for various USIC channels */
uint32_t UsicCcrMode[6] = {0};
UsicCcrMode[0] |= (uint32_t) RD_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
UsicCcrMode[1] |= (uint32_t) RD_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
/*USIC 0 Channel 0 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC0_CH0->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,4);
//Standard receive buffer event is enabled.
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC0_CH0->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x01000006); /* DPTR = 6, SIZE = 1 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x01000004); /* DPTR = 4, SIZE = 1 */
/*USIC 0 Channel 1 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC0_CH1->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,5);
WR_REG(USIC0_CH1->DX1CR, USIC_CH_DX1CR_DSEL_Msk, USIC_CH_DX1CR_DSEL_Pos,4);
//Standard receive buffer event is enabled.
WR_REG(USIC0_CH1->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
//Interrupt node 2 is selected for Protocol specific event
WR_REG(USIC0_CH1->INPR, USIC_CH_INPR_PINP_Msk, USIC_CH_INPR_PINP_Pos,2);
//Interrupt node 1 is selected for Standard receive buffer event
WR_REG(USIC0_CH1->RBCTR, USIC_CH_RBCTR_SRBINP_Msk, USIC_CH_RBCTR_SRBINP_Pos,1);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC0_CH1->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x01000002); /* DPTR = 2, SIZE = 1 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC0_CH1->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x01000000); /* DPTR = 0, SIZE = 1 */
/*USIC 1 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 1 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 1 Mux Related SFR/Bitfields Configurations*/
/* Enable mode after configuring all USIC registers to avoid unintended edges */
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[0]);
WR_REG(USIC0_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[1]);
//********* Capture/Compare Unit 4 (CAPCOM4) CONFIGURATIONS *************************
// Configuring CCU40 CC41INS - Input Selector Configuration
WR_REG(CCU40_CC41->INS, CCU4_CC4_INS_EV0IS_Msk, CCU4_CC4_INS_EV0IS_Pos, CCU4xINyB);
WR_REG(CCU40_CC41->INS, CCU4_CC4_INS_EV1IS_Msk, CCU4_CC4_INS_EV1IS_Pos, CCU4xINyB);
// Configuring CCU40 CC42INS - Input Selector Configuration
WR_REG(CCU40_CC42->INS, CCU4_CC4_INS_EV0IS_Msk, CCU4_CC4_INS_EV0IS_Pos, CCU4xINyB);
WR_REG(CCU40_CC42->INS, CCU4_CC4_INS_EV1IS_Msk, CCU4_CC4_INS_EV1IS_Pos, CCU4xINyB);
// Configuring CCU40 CC43INS - Input Selector Configuration
WR_REG(CCU40_CC43->INS, CCU4_CC4_INS_EV0IS_Msk, CCU4_CC4_INS_EV0IS_Pos, CCU4xINyB);
WR_REG(CCU40_CC43->INS, CCU4_CC4_INS_EV1IS_Msk, CCU4_CC4_INS_EV1IS_Pos, CCU4xINyB);
/* PORT Macro definitions for IOCR_OE, IOCR_PCR & HWSEL_HW */
WR_REG(PORT0->IOCR0, PORT_IOCR_PC0_OE_Msk, PORT_IOCR_PC0_OE_Pos, PORT_IOCR_OE1); /* P0.0 : PORT0_IOCR0_PC0_OE */
WR_REG(PORT0->IOCR4, 0xb8U, PORT_IOCR_PC0_PCR_Pos, 0x11U); /*P0.4 : PORT0_IOCR4_PC4_PCR and PORT0_IOCR4_PC4_OE */
WR_REG(PORT0->IOCR4, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x16U); /*P0.5 : PORT0_IOCR4_PC5_PCR and PORT0_IOCR4_PC5_OE */
WR_REG(PORT0->IOCR4, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x11U); /*P0.6 : PORT0_IOCR4_PC6_PCR and PORT0_IOCR4_PC6_OE */
WR_REG(PORT0->IOCR8, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x14U); /*P0.10 : PORT0_IOCR8_PC10_PCR and PORT0_IOCR8_PC10_OE */
WR_REG(PORT0->IOCR12, 0xb8U, PORT_IOCR_PC0_PCR_Pos, 0x11U); /*P0.12 : PORT0_IOCR12_PC12_PCR and PORT0_IOCR12_PC12_OE */
WR_REG(PORT0->IOCR12, PORT_IOCR_PC1_OE_Msk, PORT_IOCR_PC1_OE_Pos, PORT_IOCR_OE1); /* P0.13 : PORT0_IOCR12_PC13_OE */
WR_REG(PORT1->IOCR0, 0xb8U, PORT_IOCR_PC0_PCR_Pos, 0x16U); /*P1.0 : PORT1_IOCR0_PC0_PCR and PORT1_IOCR0_PC0_OE */
WR_REG(PORT1->IOCR0, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x12U); /*P1.1 : PORT1_IOCR0_PC1_PCR and PORT1_IOCR0_PC1_OE */
WR_REG(PORT1->IOCR0, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x12U); /*P1.2 : PORT1_IOCR0_PC2_PCR and PORT1_IOCR0_PC2_OE */
WR_REG(PORT1->IOCR0, 0xb8000000U, PORT_IOCR_PC3_PCR_Pos, 0x12U); /*P1.3 : PORT1_IOCR0_PC3_PCR and PORT1_IOCR0_PC3_OE */
WR_REG(PORT2->PDISC, PORT2_PDISC_PDIS10_Msk, PORT2_PDISC_PDIS10_Pos, PORT_PDISC_PDIS0); /* P2.10 : PORT2_PDISC_PDIS10 */
WR_REG(PORT2->IOCR8, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x17U); /*P2.10 : PORT2_IOCR8_PC10_PCR and PORT2_IOCR8_PC10_OE */
WR_REG(PORT2->PDISC, PORT2_PDISC_PDIS11_Msk, PORT2_PDISC_PDIS11_Pos, PORT_PDISC_PDIS0); /* P2.11 : PORT2_PDISC_PDIS11 */
WR_REG(PORT2->IOCR8, 0xb8000000U, PORT_IOCR_PC3_PCR_Pos, 0x16U); /*P2.11 : PORT2_IOCR8_PC11_PCR and PORT2_IOCR8_PC11_OE */
/* BCCU Macro definitions: */
WR_REG(BCCU0_CH0->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 7); /* BCCU_CHCONFIG0_DSEL */
WR_REG(BCCU0_CH2->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 7); /* BCCU_CHCONFIG2_DSEL */
WR_REG(BCCU0_CH3->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 2); /* BCCU_CHCONFIG3_DSEL */
WR_REG(BCCU0_CH4->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 2); /* BCCU_CHCONFIG4_DSEL */
WR_REG(BCCU0_CH5->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 2); /* BCCU_CHCONFIG5_DSEL */
WR_REG(BCCU0_CH6->CHCONFIG, BCCU_CH_CHCONFIG_DSEL_Msk, BCCU_CH_CHCONFIG_DSEL_Pos, 7); /* BCCU_CHCONFIG6_DSEL */
}
/* Function which allows changing of baudrate,parity & stopbit at run time.*/
status_t UART001_Configure
(
const UART001_HandleType* Handle,
uint32_t BaudRate,
UART_ParityType Parity,
UART_StopBitType Stopbit
)
{
uint32_t Brg_Pdiv = 0x00U;
uint32_t Fdr_Step = 0x00U;
uint32_t TXIDLE_status;
uint32_t RXIDLE_status;
USIC_CH_TypeDef* UartRegs = Handle->UartRegs;
status_t Status = (status_t)UART001_ERROR;
DBG002_FUNCTION_ENTRY(APP_GID,UART001_FUN_ENTRY);
/* <<<DD_UART001_API_3>>>*/
TXIDLE_status = (uint32_t)\
RD_REG(UartRegs->PSR_ASCMode,USIC_CH_PSR_ASCMode_TXIDLE_Msk, \
USIC_CH_PSR_ASCMode_TXIDLE_Pos);
RXIDLE_status = (uint32_t)\
RD_REG(UartRegs->PSR_ASCMode,USIC_CH_PSR_ASCMode_RXIDLE_Msk, \
USIC_CH_PSR_ASCMode_RXIDLE_Pos);
if(( TXIDLE_status & RXIDLE_status) == 0x01U)
{
/* Configuration of USIC Channel Fractional Divider */
UART001_lConfigureBaudRate(BaudRate,&Brg_Pdiv,&Fdr_Step);
/* Step value: 0x3FF */
UartRegs->FDR &= ~(USIC_CH_FDR_STEP_Msk);
UartRegs->FDR |= ( Fdr_Step & USIC_CH_FDR_STEP_Msk);
/* The PreDivider for CTQ, PCTQ = 0 */
/* The Denominator for CTQ, DCTQ = 16 */
UartRegs->BRG &= ~(USIC_CH_BRG_PDIV_Msk);
UartRegs->BRG |= ((((uint32_t)Brg_Pdiv << USIC_CH_BRG_PDIV_Pos) \
& USIC_CH_BRG_PDIV_Msk));
/* Configure StopBit */
UartRegs->PCR_ASCMode &= ~(USIC_CH_PCR_ASCMode_STPB_Msk);
UartRegs->PCR_ASCMode |= \
(((uint32_t)Stopbit << USIC_CH_PCR_ASCMode_STPB_Pos) & \
USIC_CH_PCR_ASCMode_STPB_Msk);
/* Configure Parity*/
UartRegs->CCR &= ~(USIC_CH_CCR_PM_Msk);
UartRegs->CCR |= (((UART_MODE & USIC_CH_CCR_MODE_Msk)) | \
(((uint32_t)Parity << USIC_CH_CCR_PM_Pos) & \
USIC_CH_CCR_PM_Msk));
Status = (status_t)DAVEApp_SUCCESS;
}
else
{
Status = (status_t)UART001_BUSY;
DBG002_ERROR(APP_GID,Status, 0, NULL);
}
DBG002_FUNCTION_EXIT(APP_GID,UART001_FUN_EXIT);
return Status;
}
/*
* The function programs Multiple No_of_Blocks of the Flash using
* WriteMultipleBlocks command
*/
status_t FLASH003_WriteMultipleBlocks(uint32_t Address,const uint32_t pBuf[],\
uint32_t No_of_Blocks)
{
FLASH003Status_Type status;
const FLASH003_HandleType* Handle;
uint32_t lBlk_Cnt;
uint32_t lAddress;
uint32_t rd1;
uint32_t rd2;
uint32_t rd3;
/*This is to check weather the last byte of data is crossing the max limit
*of the flash or not.
*/
uint32_t final_blk_end_add;
#if (FLASH003_SEQ_INTERRUPT == FLASH003_INTR_ENABLED)
FLASH003_DynamicHandleType* DynamicHandle;
DynamicHandle = &FLASH003_DynamicHandle0;
DynamicHandle->FLASH003_Blk_Cnt = No_of_Blocks;
if(DynamicHandle->FLASH003_global_status != FLASH003_IDLE)
{
DynamicHandle->FLASH003_global_status = FLASH003_ERROR;
}
else
#endif
{
#if (FLASH003_SEQ_INTERRUPT == FLASH003_INTR_ENABLED)
DynamicHandle->FLASH003_global_status = FLASH003_IN_PROGRESS;
#endif
Handle = &FLASH003_Handle0;
status = FLASH003_IN_PROGRESS;
/*calculation of the last byte address*/
final_blk_end_add = (uint32_t)((uint32_t)Address + \
(uint32_t)(No_of_Blocks*FLASH003_BLOCK_SIZE)) - 1U;
rd1 = RD_REG(Handle->FlashRegsPtr->NVMPROG,NVM_NVMPROG_ACTION_Msk,\
NVM_NVMPROG_ACTION_Pos);
rd2 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_BUSY_Msk,\
NVM_NVMSTATUS_BUSY_Pos);
rd3 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_SLEEP_Msk,\
NVM_NVMSTATUS_SLEEP_Pos);
/*validate the Address for Range and Block Alignment*/
if((Address < Handle->kStart_Address) || (Address > Handle->kEnd_Address)\
|| (final_blk_end_add > Handle->kEnd_Address) || \
((Address & FLASH003_BLOCK_ALIGN_CHECK) != 0U))
{
status = FLASH003_INVALID_ADDRESS;
#if (FLASH003_SEQ_INTERRUPT == FLASH003_INTR_ENABLED)
DynamicHandle->FLASH003_global_status = FLASH003_IDLE;
#endif
}
/*Checking for the status of Flash for Idle and Sleep Mode*/
else if((rd1 == FLASH003_RESET) && (rd2 == FLASH003_RESET) && \
(rd3 == FLASH003_RESET))
{
for(lBlk_Cnt = 0U;lBlk_Cnt < (uint32_t)No_of_Blocks;lBlk_Cnt++)
{
/*Updating the Address for each Block*/
lAddress = Address+(FLASH003_BLOCK_SIZE*lBlk_Cnt);
/*Calling Write Block API*/
FLASH003_lWriteBlock (lAddress, pBuf+(FLASH003_WORD_SIZE*lBlk_Cnt));
/*Checking for verification flag for any writing errors*/
if(RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_VERR_Msk,\
NVM_NVMSTATUS_VERR_Pos) == FLASH003_RESET)
{
status = FLASH003_COMPLETE;
}
else
{
status = FLASH003_ERROR;
#if (FLASH003_SEQ_INTERRUPT == FLASH003_INTR_ENABLED)
DynamicHandle->FLASH003_global_status = FLASH003_IDLE;
#endif
break;
}
}
}
else
{
status = FLASH003_ERROR;
#if (FLASH003_SEQ_INTERRUPT == FLASH003_INTR_ENABLED)
DynamicHandle->FLASH003_global_status = FLASH003_IDLE;
#endif
}
}
return (uint32_t)status;
}
/*
* The function programs one Block of the Flash using
* WriteBlock command
*/
status_t FLASH003_WriteBlock (uint32_t Address, const uint32_t pBuf[])
{
FLASH003Status_Type status;
const FLASH003_HandleType* Handle;
uint32_t rd1;
uint32_t rd2;
uint32_t rd3;
#if (FLASH003_SEQ_INTERRUPT == FLASH003_INTR_ENABLED)
FLASH003_DynamicHandleType* DynamicHandle;
DynamicHandle = &FLASH003_DynamicHandle0;
/*no of blocks will be only one,so while interrupt is called user handler
has to be called at first time itself*/
DynamicHandle->FLASH003_Blk_Cnt = 0U;
if(DynamicHandle->FLASH003_global_status != FLASH003_IDLE)
{
DynamicHandle->FLASH003_global_status = FLASH003_ERROR;
}
else
#endif
{
#if (FLASH003_SEQ_INTERRUPT == FLASH003_INTR_ENABLED)
DynamicHandle->FLASH003_global_status = FLASH003_IN_PROGRESS;
#endif
Handle = &FLASH003_Handle0;
status = FLASH003_IN_PROGRESS;
rd1 = RD_REG(Handle->FlashRegsPtr->NVMPROG,NVM_NVMPROG_ACTION_Msk,\
NVM_NVMPROG_ACTION_Pos);
rd2 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_BUSY_Msk,\
NVM_NVMSTATUS_BUSY_Pos);
rd3 = RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_SLEEP_Msk,\
NVM_NVMSTATUS_SLEEP_Pos);
/* <<<DD_FLASH003_API_3>>> */
/*validate the Address for Range and Block Alignment*/
if((Address < Handle->kStart_Address) || (Address > Handle->kEnd_Address)\
|| ((Address & FLASH003_BLOCK_ALIGN_CHECK) != 0U))
{
status = FLASH003_INVALID_ADDRESS;
#if (FLASH003_SEQ_INTERRUPT == FLASH003_INTR_ENABLED)
DynamicHandle->FLASH003_global_status = FLASH003_IDLE;
#endif
}
/*Checking for the status of Flash for Idle and Sleep Mode*/
else if((rd1 == FLASH003_RESET) && (rd2 == FLASH003_RESET) && \
(rd3 == FLASH003_RESET))
{
/*Calling Write Block API*/
FLASH003_lWriteBlock (Address, pBuf);
/*Checking for verification flag for any writing errors*/
if(RD_REG(Handle->FlashRegsPtr->NVMSTATUS,NVM_NVMSTATUS_VERR_Msk,\
NVM_NVMSTATUS_VERR_Pos) == FLASH003_RESET)
{
status = FLASH003_COMPLETE;
}
else
{
status = FLASH003_ERROR;
/* need to be checked whether required or not*/
#if (FLASH003_SEQ_INTERRUPT == FLASH003_INTR_ENABLED)
DynamicHandle->FLASH003_global_status = FLASH003_IDLE;
#endif
}
}
else
{
status = FLASH003_ERROR;
#if (FLASH003_SEQ_INTERRUPT == FLASH003_INTR_ENABLED)
DynamicHandle->FLASH003_global_status = FLASH003_IDLE;
#endif
}
}
return (uint32_t)status;
}
void DAVE_MUX_Init(void)
{
/* SCU Macro definitions */
//********* MODULE USIC CONFIGURATIONS *************************
/* Disable mode before configuring all USIC registers to avoid unintended edges */
/* Variable to store the CCR_MODE values for various USIC channels */
uint32_t UsicCcrMode[6] = {0};
UsicCcrMode[0] |= (uint32_t) RD_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
/*USIC 0 Channel 0 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC0_CH0->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,6);
WR_REG(USIC0_CH0->DX3CR, USIC_CH_DX3CR_DSEL_Msk, USIC_CH_DX3CR_DSEL_Pos,5);
WR_REG(USIC0_CH0->DX5CR, USIC_CH_DX5CR_DSEL_Msk, USIC_CH_DX5CR_DSEL_Pos,4);
//Standard receive buffer event is enabled.
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC0_CH0->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x05000020); /* DPTR = 32, SIZE = 5 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x05000000); /* DPTR = 0, SIZE = 5 */
/*USIC 0 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 1 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 1 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 1 Mux Related SFR/Bitfields Configurations*/
/* Enable mode after configuring all USIC registers to avoid unintended edges */
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[0]);
//********* Capture/Compare Unit 4 (CAPCOM4) CONFIGURATIONS *************************
/* PORT Macro definitions for IOCR_OE, IOCR_PCR & HWSEL_HW */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC0_OE_Msk, PORT_IOCR_PC0_OE_Pos, PORT_IOCR_OE1); /* P1.0 : PORT1_IOCR0_PC0_OE */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC1_OE_Msk, PORT_IOCR_PC1_OE_Pos, PORT_IOCR_OE1); /* P1.1 : PORT1_IOCR0_PC1_OE */
WR_REG(PORT1->IOCR4, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x12U); /*P1.5 : PORT1_IOCR4_PC5_PCR and PORT1_IOCR4_PC5_OE */
//********* Capture/Compare Unit 8 (CAPCOM8) CONFIGURATIONS *************************
/*VADC GROUP0 Mux Related SFR/Bitfields Configurations*/
/*VADC GROUP1 Mux Related SFR/Bitfields Configurations*/
/*VADC GROUP2 Mux Related SFR/Bitfields Configurations*/
/*VADC GROUP3 Mux Related SFR/Bitfields Configurations*/
/*VADC GLOBAL RESULT Mux Related SFR/Bitfields Configurations*/
/*VADC BACKGROUND Source Mux Related SFR/Bitfields Configurations*/
}
void DAVE_MUX_Init(void)
{
/* SCU Macro definitions */
//********* MODULE USIC CONFIGURATIONS *************************
/* Disable mode before configuring all USIC registers to avoid unintended edges */
/* Variable to store the CCR_MODE values for various USIC channels */
uint32_t UsicCcrMode[6] = {0};
UsicCcrMode[2] |= (uint32_t) RD_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
UsicCcrMode[4] |= (uint32_t) RD_REG(USIC2_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC2_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
/*USIC 0 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 0 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 1 Channel 0 Mux Related SFR/Bitfields Configurations*/
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC1_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x06000000); /* DPTR = 0, SIZE = 6 */
/*USIC 1 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 0 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC2_CH0->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,1);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC2_CH0->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x01000008); /* DPTR = 8, SIZE = 1 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC2_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x03000000); /* DPTR = 0, SIZE = 3 */
/*USIC 2 Channel 1 Mux Related SFR/Bitfields Configurations*/
/* Enable mode after configuring all USIC registers to avoid unintended edges */
WR_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[2]);
WR_REG(USIC2_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[4]);
/* PORT Macro definitions for IOCR_OE, IOCR_PCR & HWSEL_HW */
WR_REG(PORT0->IOCR4, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x12U); /*P0.5 : PORT0_IOCR4_PC5_PCR and PORT0_IOCR4_PC5_OE */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC0_OE_Msk, PORT_IOCR_PC0_OE_Pos, PORT_IOCR_OE1); /* P1.0 : PORT1_IOCR0_PC0_OE */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC1_OE_Msk, PORT_IOCR_PC1_OE_Pos, PORT_IOCR_OE1); /* P1.1 : PORT1_IOCR0_PC1_OE */
WR_REG(PORT5->IOCR0, 0xb8U, PORT_IOCR_PC0_PCR_Pos, 0x11U); /*P5.0 : PORT5_IOCR0_PC0_PCR and PORT5_IOCR0_PC0_OE */
WR_REG(PORT5->IOCR0, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x11U); /*P5.2 : PORT5_IOCR0_PC2_PCR and PORT5_IOCR0_PC2_OE */
WR_REG(PORT5->IOCR4, PORT_IOCR_PC3_OE_Msk, PORT_IOCR_PC3_OE_Pos, PORT_IOCR_OE1); /* P5.7 : PORT5_IOCR4_PC7_OE */
}
void DAVE_MUX_Init(void)
{
/* SCU Macro definitions */
/*
* CAN peripheral configuration:
*/
//Node2 configuration:
WR_REG(CAN_NODE2->NIPR, CAN_NODE_NIPR_ALINP_Msk, CAN_NODE_NIPR_ALINP_Pos, SRN1);
//Message object 35 configuration:
WR_REG(CAN_MO35->MOIPR, CAN_MO_MOIPR_RXINP_Msk, CAN_MO_MOIPR_RXINP_Pos, SRN1);
//Message object 36 configuration:
WR_REG(CAN_MO36->MOIPR, CAN_MO_MOIPR_RXINP_Msk, CAN_MO_MOIPR_RXINP_Pos, SRN1);
//Message object 37 configuration:
WR_REG(CAN_MO37->MOIPR, CAN_MO_MOIPR_RXINP_Msk, CAN_MO_MOIPR_RXINP_Pos, SRN1);
//Message object 38 configuration:
WR_REG(CAN_MO38->MOIPR, CAN_MO_MOIPR_RXINP_Msk, CAN_MO_MOIPR_RXINP_Pos, SRN1);
/* Macros which makes the CAN peripheral to exit from the INITIALISATION mode to NORMAL mode */
#ifdef CAN_NODE0_ENABLE
CAN_Handle0_NODE();
#endif
#ifdef CAN_NODE1_ENABLE
CAN_Handle1_NODE();
#endif
#ifdef CAN_NODE2_ENABLE
CAN_Handle2_NODE();
#endif
/*
* POSIF0 peripheral configuration:
*/
//POSIF0 configuration:
WR_REG(POSIF0->PCONF, POSIF_PCONF_INSEL0_Msk, POSIF_PCONF_INSEL0_Pos, INSIGNAL1);
WR_REG(POSIF0->PCONF, POSIF_PCONF_INSEL1_Msk, POSIF_PCONF_INSEL1_Pos, INSIGNAL1);
/*
* POSIF1 peripheral configuration:
*/
//********* MODULE USIC CONFIGURATIONS *************************
/* Disable mode before configuring all USIC registers to avoid unintended edges */
/* Variable to store the CCR_MODE values for various USIC channels */
uint32_t UsicCcrMode[6] = {0};
UsicCcrMode[0] |= (uint32_t) RD_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
UsicCcrMode[2] |= (uint32_t) RD_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
UsicCcrMode[3] |= (uint32_t) RD_REG(USIC1_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos);
WR_REG(USIC1_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,0);
/*USIC 0 Channel 0 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC0_CH0->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,3);
//Standard transmit buffer event is enabled.
WR_REG(USIC0_CH0->TBCTR, USIC_CH_TBCTR_STBIEN_Msk, USIC_CH_TBCTR_STBIEN_Pos,1);
//Standard receive buffer event is enabled.
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
//Interrupt node 3 is selected for Standard transmit buffer event
WR_REG(USIC0_CH0->TBCTR, USIC_CH_TBCTR_STBINP_Msk, USIC_CH_TBCTR_STBINP_Pos,3);
//Interrupt node 5 is selected for Standard receive buffer event
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_SRBINP_Msk, USIC_CH_RBCTR_SRBINP_Pos,5);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC0_CH0->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x04000010); /* DPTR = 16, SIZE = 4 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC0_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x04000000); /* DPTR = 0, SIZE = 4 */
/*USIC 0 Channel 1 Mux Related SFR/Bitfields Configurations*/
/*USIC 1 Channel 0 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC1_CH0->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,2);
//Standard transmit buffer event is enabled.
WR_REG(USIC1_CH0->TBCTR, USIC_CH_TBCTR_STBIEN_Msk, USIC_CH_TBCTR_STBIEN_Pos,1);
//Standard receive buffer event is enabled.
WR_REG(USIC1_CH0->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
//Interrupt node 1 is selected for Standard transmit buffer event
WR_REG(USIC1_CH0->TBCTR, USIC_CH_TBCTR_STBINP_Msk, USIC_CH_TBCTR_STBINP_Pos,1);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC1_CH0->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x04000010); /* DPTR = 16, SIZE = 4 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC1_CH0->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x04000000); /* DPTR = 0, SIZE = 4 */
/*USIC 1 Channel 1 Mux Related SFR/Bitfields Configurations*/
WR_REG(USIC1_CH1->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos,3);
//Standard transmit buffer event is enabled.
WR_REG(USIC1_CH1->TBCTR, USIC_CH_TBCTR_STBIEN_Msk, USIC_CH_TBCTR_STBIEN_Pos,1);
//Standard receive buffer event is enabled.
WR_REG(USIC1_CH1->RBCTR, USIC_CH_RBCTR_SRBIEN_Msk, USIC_CH_RBCTR_SRBIEN_Pos,1);
//Interrupt node 3 is selected for Standard transmit buffer event
WR_REG(USIC1_CH1->TBCTR, USIC_CH_TBCTR_STBINP_Msk, USIC_CH_TBCTR_STBINP_Pos,3);
//Interrupt node 2 is selected for Standard receive buffer event
WR_REG(USIC1_CH1->RBCTR, USIC_CH_RBCTR_SRBINP_Msk, USIC_CH_RBCTR_SRBINP_Pos,2);
// Data Pointer & Buffer Size for Transmitter Buffer Control
WR_REG(USIC1_CH1->TBCTR, USIC_CH_TBCTR_DPTRSIZE_Msk, USIC_CH_TBCTR_DPTRSIZE_Pos,0x04000030); /* DPTR = 48, SIZE = 4 */
// Data Pointer & Buffer Size for Receiver Buffer Control
WR_REG(USIC1_CH1->RBCTR, USIC_CH_RBCTR_DPTRSIZE_Msk, USIC_CH_RBCTR_DPTRSIZE_Pos,0x04000020); /* DPTR = 32, SIZE = 4 */
/*USIC 2 Channel 0 Mux Related SFR/Bitfields Configurations*/
/*USIC 2 Channel 1 Mux Related SFR/Bitfields Configurations*/
/* Enable mode after configuring all USIC registers to avoid unintended edges */
WR_REG(USIC0_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[0]);
WR_REG(USIC1_CH0->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[2]);
WR_REG(USIC1_CH1->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos,UsicCcrMode[3]);
//********* Capture/Compare Unit 4 (CAPCOM4) CONFIGURATIONS *************************
// Configuring CCU40 CC41INS - Input Selector Configuration
WR_REG(CCU40_CC41->INS, CCU4_CC4_INS_EV0IS_Msk, CCU4_CC4_INS_EV0IS_Pos, CCU4xINyE);
WR_REG(CCU40_CC41->INS, CCU4_CC4_INS_EV1IS_Msk, CCU4_CC4_INS_EV1IS_Pos, CCU4xINyF);
// Configuring CCU40 CC42INS - Input Selector Configuration
WR_REG(CCU40_CC42->INS, CCU4_CC4_INS_EV0IS_Msk, CCU4_CC4_INS_EV0IS_Pos, CCU4xINyF);
WR_REG(CCU40_CC42->INS, CCU4_CC4_INS_EV1IS_Msk, CCU4_CC4_INS_EV1IS_Pos, CCU4xINyM);
// Configuring CCU40_CC40SRS = Service Request Selector
WR_REG(CCU40_CC40->SRS, CCU4_CC4_SRS_POSR_Msk, CCU4_CC4_SRS_POSR_Pos, CCU_SR1);
// Configuring CCU40_CC41SRS = Service Request Selector
WR_REG(CCU40_CC41->SRS, CCU4_CC4_SRS_CMSR_Msk, CCU4_CC4_SRS_CMSR_Pos, CCU_SR2);
/* PORT Macro definitions for IOCR_OE, IOCR_PCR & HWSEL_HW */
WR_REG(PORT0->IOCR0, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x12U); /*P0.1 : PORT0_IOCR0_PC1_PCR and PORT0_IOCR0_PC1_OE */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC0_OE_Msk, PORT_IOCR_PC0_OE_Pos, PORT_IOCR_OE1); /* P1.0 : PORT1_IOCR0_PC0_OE */
WR_REG(PORT1->IOCR0, PORT_IOCR_PC1_OE_Msk, PORT_IOCR_PC1_OE_Pos, PORT_IOCR_OE1); /* P1.1 : PORT1_IOCR0_PC1_OE */
WR_REG(PORT2->IOCR12, 0xb80000U, PORT_IOCR_PC2_PCR_Pos, 0x12U); /*P2.14 : PORT2_IOCR12_PC14_PCR and PORT2_IOCR12_PC14_OE */
WR_REG(PORT5->IOCR0, 0xb800U, PORT_IOCR_PC1_PCR_Pos, 0x11U); /*P5.1 : PORT5_IOCR0_PC1_PCR and PORT5_IOCR0_PC1_OE */
}
