static int put_data(struct _simulate *simulate, int PC, int reg, int Ad, int bw, uint32_t data)
{
struct _simulate_msp430 *simulate_msp430 = (struct _simulate_msp430 *)simulate->context;
if (Ad == 0) // Rn
{
if (bw == 0)
{ simulate_msp430->reg[reg] = data; }
else
{
//simulate_msp430->reg[reg]&=0xff00;
//simulate_msp430->reg[reg]|=data&0xff;
simulate_msp430->reg[reg] = data & 0xff;
}
return 0;
}
if (reg == 2)
{
if (Ad == 1) // &LABEL
{
uint16_t a = READ_RAM(PC) | (READ_RAM(PC+1) << 8);
if (bw == 0)
{
WRITE_RAM(a, data & 0xff);
WRITE_RAM(a + 1, data >> 8);
}
else
{ WRITE_RAM(a, data & 0xff); }
void disasm_range_805x(struct _memory *memory, int start, int end)
{
char instruction[128];
char temp[32];
char temp2[4];
int cycles_min=0,cycles_max=0;
int count;
int n;
printf("\n");
printf("%-7s %-5s %-40s Cycles\n", "Addr", "Opcode", "Instruction");
printf("------- ------ ---------------------------------- ------\n");
while(start<=end)
{
//num=READ_RAM(start)|(READ_RAM(start+1)<<8);
count=disasm_805x(memory, start, instruction, &cycles_min, &cycles_max);
temp[0]=0;
for (n=0; n<count; n++)
{
//sprintf(temp2, "%02x ", READ_RAM(start+n));
sprintf(temp2, "%02x ", memory_read_m(memory, start+n));
strcat(temp, temp2);
}
if (cycles_min<1)
{
printf("0x%04x: %-10s %-40s ?\n", start, temp, instruction);
}
else
if (cycles_min==cycles_max)
{
printf("0x%04x: %-10s %-40s %d\n", start, temp, instruction, cycles_min);
}
else
{
printf("0x%04x: %-10s %-40s %d-%d\n", start, temp, instruction, cycles_min, cycles_max);
}
#if 0
count-=4;
while (count>0)
{
start=start+4;
num=READ_RAM(start)|(READ_RAM(start+1)<<8);
printf("0x%04x: 0x%04x\n", start, num);
count-=4;
}
#endif
start=start+count;
}
}
int disasm_6800(struct _memory *memory, uint32_t address, char *instruction, int *cycles_min, int *cycles_max)
{
int opcode;
int size = 1;
*cycles_min = -1;
*cycles_max = -1;
opcode = READ_RAM(address);
switch(table_6800[opcode].operand_type)
{
case M6800_OP_UNDEF:
strcpy(instruction, "???");
break;
case M6800_OP_NONE:
strcpy(instruction, table_6800[opcode].instr);
break;
case M6800_OP_IMM8:
sprintf(instruction, "%s #$%02x", table_6800[opcode].instr, READ_RAM(address+1));
size = 2;
break;
case M6800_OP_IMM16:
sprintf(instruction, "%s #$%04x", table_6800[opcode].instr, READ_RAM16(address + 1));
size = 3;
break;
case M6800_OP_DIR_PAGE_8:
sprintf(instruction, "%s $%02x", table_6800[opcode].instr, READ_RAM(address + 1));
size = 2;
break;
case M6800_OP_ABSOLUTE_16:
sprintf(instruction, "%s $%04x", table_6800[opcode].instr, READ_RAM16(address + 1));
size = 3;
break;
case M6800_OP_NN_X:
sprintf(instruction, "%s $%04x,X (%d)", table_6800[opcode].instr, (address + 2)+(char)(READ_RAM(address + 1)), (char)(READ_RAM(address + 1)));
size = 2;
break;
case M6800_OP_REL_OFFSET:
sprintf(instruction, "%s $%04x,X (%d)", table_6800[opcode].instr, (address + 2)+(char)(READ_RAM(address + 1)), (char)READ_RAM(address + 1));
size=2;
break;
}
return size;
}
void disasm_range_65816(struct _memory *memory, int start, int end)
{
#if 0
char instruction[128];
//int vectors_flag=0;
int cycles_min=0,cycles_max=0;
int num;
printf("\n");
printf("%-7s %-5s %-40s Cycles\n", "Addr", "Opcode", "Instruction");
printf("------- ------ ---------------------------------- ------\n");
while(start<=end)
{
num=READ_RAM(start)|(READ_RAM(start+1)<<8);
int count=disasm_65816(memory, start, instruction, &cycles_min, &cycles_max);
if (cycles_min<1)
{
printf("0x%04x: 0x%02x %-40s ?\n", start, num & 0xFF, instruction);
}
else
if (cycles_min==cycles_max)
{
printf("0x%04x: 0x%02x %-40s %d\n", start, num & 0xFF, instruction, cycles_min);
}
else
{
printf("0x%04x: 0x%02x %-40s %d-%d\n", start, num & 0xFF, instruction, cycles_min, cycles_max);
}
count-=1;
while (count>0)
{
start=start+1;
num=READ_RAM(start)|(READ_RAM(start+1)<<8);
printf("0x%04x: 0x%02x\n", start, num & 0xFF);
count-=1;
}
start=start+1;
}
#endif
}
void disasm_range_6800(struct _memory *memory, uint32_t flags, uint32_t start, uint32_t end)
{
char instruction[128];
char bytes[10];
int cycles_min = 0,cycles_max = 0;
int count;
int n;
printf("\n");
printf("%-7s %-5s %-40s Cycles\n", "Addr", "Opcode", "Instruction");
printf("------- ------ ---------------------------------- ------\n");
while(start <= end)
{
count = disasm_6800(memory, start, instruction, &cycles_min, &cycles_max);
bytes[0] = 0;
for (n = 0; n < count; n++)
{
char temp[4];
sprintf(temp, "%02x ", READ_RAM(start + n));
strcat(bytes, temp);
}
if (cycles_min < 1)
{
printf("0x%04x: %-9s %-40s ?\n", start, bytes, instruction);
}
else
if (cycles_min==cycles_max)
{
printf("0x%04x: %-9s %-40s %d\n", start, bytes, instruction, cycles_min);
}
else
{
printf("0x%04x: %-9s %-40s %d-%d\n", start, bytes, instruction, cycles_min, cycles_max);
}
start = start + count;
}
}
int get_indexed(struct _memory *memory, struct _table_6809 *table, char *instruction, uint32_t address, int *cycles_min, int *cycles_max)
{
const char *name[] = { "x", "y", "u", "s" };
uint8_t post_byte = READ_RAM(address);
int reg = (post_byte >> 5) & 0x3;
if ((post_byte & 0x9f) == 0x84)
{
// ,R non-indirect
sprintf(instruction, "%s ,%s", table->instr, name[reg]);
return 0;
}
else
if ((post_byte & 0x9f) == 0x94)
{
// [,R] indirect
sprintf(instruction, "%s [,%s]", table->instr, name[reg]);
ADD_CYCLES(3);
return 0;
}
else
if ((post_byte & 0x80) == 0x00)
{
// 5 bit offset, R non-indirect
int8_t offset = post_byte & 0x1f;
if ((offset & 0x10) != 0) { offset |= 0xe0; }
sprintf(instruction, "%s %d,%s", table->instr, offset, name[reg]);
ADD_CYCLES(1);
return 0;
}
else
if ((post_byte & 0x9f) == 0x88)
{
// 8 bit offset, R non-indirect
int8_t offset = READ_RAM(address + 1);
sprintf(instruction, "%s %d,%s", table->instr, offset, name[reg]);
ADD_CYCLES(1);
return 1;
}
else
if ((post_byte & 0x9f) == 0x98)
{
// [8 bit offset, R] indirect
int8_t offset = READ_RAM(address + 1);
sprintf(instruction, "%s [%d,%s]", table->instr, offset, name[reg]);
ADD_CYCLES(4);
return 1;
}
else
if ((post_byte & 0x9f) == 0x89)
{
// 16 bit offset, R non-indirect
int16_t offset = READ_RAM16(address + 1);
sprintf(instruction, "%s %d,%s", table->instr, offset, name[reg]);
ADD_CYCLES(4);
return 2;
}
else
if ((post_byte & 0x9f) == 0x99)
{
// [16 bit offset, R] indirect
int16_t offset = READ_RAM16(address + 1);
sprintf(instruction, "%s [%d,%s]", table->instr, offset, name[reg]);
ADD_CYCLES(7);
return 2;
}
else
if ((post_byte & 0x9f) == 0x86)
{
// A,R non-indirect
sprintf(instruction, "%s a,%s", table->instr, name[reg]);
ADD_CYCLES(1);
return 0;
}
else
if ((post_byte & 0x9f) == 0x96)
{
// [A,R] non-indirect
sprintf(instruction, "%s [a,%s]", table->instr, name[reg]);
ADD_CYCLES(4);
return 0;
}
else
if ((post_byte & 0x9f) == 0x85)
{
// B,R non-indirect
sprintf(instruction, "%s b,%s", table->instr, name[reg]);
ADD_CYCLES(1);
return 0;
}
else
if ((post_byte & 0x9f) == 0x95)
{
// [B,R] indirect
sprintf(instruction, "%s [b,%s]", table->instr, name[reg]);
ADD_CYCLES(4);
return 0;
}
else
if ((post_byte & 0x9f) == 0x8b)
{
// D,R non-indirect
sprintf(instruction, "%s d,%s", table->instr, name[reg]);
ADD_CYCLES(4);
return 0;
}
else
if ((post_byte & 0x9f) == 0x9b)
{
// [D,R] non-indirect
sprintf(instruction, "%s [d,%s]", table->instr, name[reg]);
ADD_CYCLES(7);
return 0;
}
else
if ((post_byte & 0x9f) == 0x80)
{
// ,R+ non-indirect
sprintf(instruction, "%s ,%s+", table->instr, name[reg]);
ADD_CYCLES(2);
return 0;
}
else
if ((post_byte & 0x9f) == 0x81)
{
// ,R++ non-indirect
sprintf(instruction, "%s ,%s++", table->instr, name[reg]);
ADD_CYCLES(3);
return 0;
}
else
if ((post_byte & 0x9f) == 0x91)
{
// [,R++] indirect
sprintf(instruction, "%s [,%s++]", table->instr, name[reg]);
ADD_CYCLES(6);
return 0;
}
else
if ((post_byte & 0x9f) == 0x82)
{
// ,-R non-indirect
sprintf(instruction, "%s ,-%s", table->instr, name[reg]);
ADD_CYCLES(2);
return 0;
}
else
if ((post_byte & 0x9f) == 0x83)
{
// ,--R non-indirect
sprintf(instruction, "%s ,--%s", table->instr, name[reg]);
ADD_CYCLES(3);
return 0;
}
else
if ((post_byte & 0x9f) == 0x93)
{
// [,--R] indirect
sprintf(instruction, "%s [,--%s]", table->instr, name[reg]);
ADD_CYCLES(6);
return 0;
}
else
if ((post_byte & 0x9f) == 0x8c)
{
// 8 bit offset, PCR non-indirect
int8_t offset = READ_RAM(address + 1);
sprintf(instruction, "%s %d,pc", table->instr, offset);
ADD_CYCLES(1);
return 1;
}
else
if ((post_byte & 0x9f) == 0x9c)
{
// [8 bit offset, PCR] indirect
int8_t offset = READ_RAM(address + 1);
sprintf(instruction, "%s [%d,pc]", table->instr, offset);
ADD_CYCLES(4);
return 1;
}
else
if ((post_byte & 0x9f) == 0x8d)
{
// 16 bit offset, PCR non-indirect
int16_t offset = READ_RAM16(address + 1);
sprintf(instruction, "%s %d,pc", table->instr, offset);
ADD_CYCLES(5);
return 2;
}
else
if ((post_byte & 0x9f) == 0x9d)
{
// [16 bit offset, PCR] non-indirect
int16_t offset = READ_RAM16(address + 1);
sprintf(instruction, "%s [%d,pc]", table->instr, offset);
ADD_CYCLES(8);
return 2;
}
else
if ((post_byte & 0x9f) == 0x9f)
{
// [16 bit offset] non-indirect
int16_t offset = READ_RAM16(address + 1);
sprintf(instruction, "%s [0x%04x]", table->instr, offset);
ADD_CYCLES(5);
return 2;
}
strcpy(instruction, "???");
return 0;
}
int disasm_6809(struct _memory *memory, uint32_t address, char *instruction, int *cycles_min, int *cycles_max)
{
int opcode;
int n;
*cycles_min = -1;
*cycles_max = -1;
opcode = READ_RAM(address);
if (opcode == 0x10 || opcode == 0x11)
{
opcode = READ_RAM16(address);
n = 0;
while(table_6809_16[n].instr != NULL)
{
if (table_6809_16[n].opcode == opcode)
{
strcpy(instruction, table_6809_16[n].instr);
*cycles_min = table_6809_16[n].cycles_min;
*cycles_max = table_6809_16[n].cycles_min;
switch(table_6809_16[n].operand_type)
{
case M6809_OP_INHERENT:
{
return 2;
}
case M6809_OP_IMMEDIATE:
{
if (table_6809_16[n].bytes == 4)
{
sprintf(instruction, "%s #0x%02x", table_6809_16[n].instr, READ_RAM16(address + 2));
return 4;
}
break;
}
case M6809_OP_EXTENDED:
{
if (table_6809_16[n].bytes == 4)
{
sprintf(instruction, "%s 0x%04x", table_6809_16[n].instr, READ_RAM16(address + 2));
return 4;
}
break;
}
case M6809_OP_RELATIVE:
{
if (table_6809_16[n].bytes == 4)
{
int16_t offset = READ_RAM16(address + 2);
sprintf(instruction, "%s 0x%04x (%d)", table_6809_16[n].instr, (address + 4 + offset) & 0xffff, offset);
return 4;
}
break;
}
case M6809_OP_DIRECT:
{
if (table_6809_16[n].bytes == 3)
{
sprintf(instruction, "%s >0x%02x", table_6809_16[n].instr, READ_RAM(address + 2));
return 3;
}
break;
}
case M6809_OP_INDEXED:
{
return get_indexed(memory, &table_6809_16[n], instruction, address + 2, cycles_min, cycles_max) + 3;
break;
}
default:
{
//print_error_internal(asm_context, __FILE__, __LINE__);
break;
}
}
}
n++;
}
}
else
{
n = 0;
while(table_6809[n].instr != NULL)
{
if (table_6809[n].opcode == opcode)
{
*cycles_min = table_6809[n].cycles_min;
*cycles_max = table_6809[n].cycles_min;
switch(table_6809[n].operand_type)
{
case M6809_OP_INHERENT:
{
strcpy(instruction, table_6809[n].instr);
return 1;
}
case M6809_OP_IMMEDIATE:
{
if (table_6809[n].bytes == 2)
{
sprintf(instruction, "%s #0x%02x", table_6809[n].instr, READ_RAM(address + 1));
return 2;
}
else
if (table_6809[n].bytes == 3)
{
sprintf(instruction, "%s #0x%02x", table_6809[n].instr, READ_RAM16(address + 1));
return 3;
}
break;
}
case M6809_OP_EXTENDED:
{
if (table_6809[n].bytes == 3)
{
sprintf(instruction, "%s 0x%04x", table_6809[n].instr, READ_RAM16(address + 1));
return 3;
}
break;
}
case M6809_OP_RELATIVE:
{
if (table_6809[n].bytes == 2)
{
int8_t offset = READ_RAM(address + 1);
sprintf(instruction, "%s 0x%04x (%d)", table_6809[n].instr, (address + 2 + offset) & 0xffff, offset);
return 2;
}
break;
}
case M6809_OP_LONG_RELATIVE:
{
if (table_6809[n].bytes == 3)
{
int16_t offset = (READ_RAM(address + 1) << 8) | READ_RAM(address + 2);
sprintf(instruction, "%s 0x%04x (%d)", table_6809[n].instr, (address + 3 + offset) & 0xffff, offset);
return 2;
}
break;
}
case M6809_OP_DIRECT:
{
if (table_6809[n].bytes == 2)
{
sprintf(instruction, "%s >0x%02x", table_6809[n].instr, READ_RAM(address + 1));
return 2;
}
break;
}
case M6809_OP_STACK:
{
if (table_6809[n].bytes == 2)
{
uint8_t reg_list = READ_RAM(address + 1);
const char *reg_names[] = { "pc","u","y","x","dp","b","a","cc" };
uint8_t index = 0x80;
uint8_t count = 0;
sprintf(instruction, "%s", table_6809[n].instr);
for (n = 0; n < 8; n++)
{
if ((reg_list & index) != 0)
{
if (count != 0) { strcat(instruction, ", "); }
else { strcat(instruction, " "); }
strcat(instruction, reg_names[n]);
count++;
// Each byte pushed adds 1 cycle to cycle counts
if (n >= 4) { *cycles_min += 1; *cycles_max += 1; }
else { *cycles_min += 2; *cycles_max += 2; }
}
index >>= 1;
}
return 2;
}
}
case M6809_OP_TWO_REG:
{
const char *reg_post_byte[] = {
"d", "x", "y", "u", "s", "pc", "?", "?",
"a", "b", "cc", "dp", "?", "?", "?", "?"
};
uint8_t post_byte = READ_RAM(address + 1);
const char *src = reg_post_byte[post_byte >> 4];
const char *dst = reg_post_byte[post_byte & 0xf];
sprintf(instruction, "%s %s, %s", table_6809[n].instr, src, dst);
return 2;
}
case M6809_OP_INDEXED:
{
return get_indexed(memory, &table_6809[n], instruction, address + 1, cycles_min, cycles_max) + 2;
break;
}
default:
{
//print_error_internal(asm_context, __FILE__, __LINE__);
break;
}
}
}
n++;
}
int disasm_805x(struct _memory *memory, int address, char *instruction, int *cycles_min, int *cycles_max)
{
int count=1;
int opcode;
char temp[32];
int value;
int n;
opcode=READ_RAM(address);
strcpy(instruction, table_805x[opcode].name);
for (n=0; n<3; n++)
{
if (table_805x[opcode].op[n]==OP_NONE) break;
if (n==0) { strcat(instruction, " "); }
else { strcat(instruction, ", "); }
switch(table_805x[opcode].op[n])
{
case OP_REG:
sprintf(temp, "R%d", table_805x[opcode].range);
strcat(instruction, temp);
break;
case OP_AT_REG:
sprintf(temp, "@R%d", table_805x[opcode].range);
strcat(instruction, temp);
break;
case OP_A:
strcat(instruction, "A");
break;
case OP_C:
strcat(instruction, "C");
break;
case OP_AB:
strcat(instruction, "AB");
break;
case OP_DPTR:
strcat(instruction, "DPTR");
break;
case OP_AT_A_PLUS_DPTR:
strcat(instruction, "@A+DPTR");
break;
case OP_AT_A_PLUS_PC:
strcat(instruction, "@A+PC");
break;
case OP_AT_DPTR:
strcat(instruction, "@DPTR");
break;
case OP_DATA:
sprintf(temp, "#0x%02x", READ_RAM(address+count));
strcat(instruction, temp);
count++;
break;
case OP_DATA_16:
sprintf(temp, "#0x%04x", READ_RAM(address+count)|(READ_RAM(address+count+1)<<8));
strcat(instruction, temp);
count=3;
break;
case OP_CODE_ADDR:
sprintf(temp, "0x%04x", READ_RAM(address+count)|(READ_RAM(address+count+1)<<8));
strcat(instruction, temp);
count=3;
break;
case OP_RELADDR:
value=READ_RAM(address+count);
sprintf(temp, "0x%04x", (address+count+1)+((char)value));
strcat(instruction, temp);
count++;
break;
case OP_SLASH_BIT_ADDR:
sprintf(temp, "/0x%02x", READ_RAM(address+count));
strcat(instruction, temp);
count++;
break;
case OP_PAGE:
sprintf(temp, "0x%04x", READ_RAM(address+count)|(table_805x[opcode].range<<8));
strcat(instruction, temp);
count++;
break;
case OP_BIT_ADDR:
value=READ_RAM(address+count);
sprintf(temp, "0x%02x.%d [0x%02x]", ((value&0x7f)>>3)|((value&128)==0?0x20:0x80), value&0x07, value);
strcat(instruction, temp);
count++;
break;
case OP_IRAM_ADDR:
sprintf(temp, "0x%02x", READ_RAM(address+count));
strcat(instruction, temp);
count++;
break;
}
}
//strcpy(instruction, "???");
return count;
}
int disasm_65xx(struct _memory *memory, int address, char *instruction, int *cycles_min, int *cycles_max)
{
unsigned int opcode;
//int n,r;
char temp[32];
char num[8];
int op;
int lo, hi;
int branch_address = 0;
*cycles_min=-1;
*cycles_max=-1;
opcode=READ_RAM(address);
sprintf(temp, " ");
if(table_65xx_opcodes[opcode].instr != -1)
{
strcpy(instruction, table_65xx[table_65xx_opcodes[opcode].instr].name);
op = table_65xx_opcodes[opcode].op;
if(op_bytes[op] > 1)
{
if(op_bytes[op] == 2)
{
lo = READ_RAM(address + 1);
// special case for branches
if(op == OP_RELATIVE)
{
branch_address = (address + 2) + (signed char)lo;
sprintf(num, "0x%04x", branch_address);
}
else
{
sprintf(num, "0x%02x", lo);
}
}
else if(op_bytes[op] == 3)
{
lo = READ_RAM(address + 1);
hi = READ_RAM(address + 2);
sprintf(num, "0x%04x", (hi << 8) | lo);
}
switch(op)
{
case OP_NONE:
sprintf(temp, " ");
break;
case OP_IMMEDIATE:
sprintf(temp, " #%s", num);
break;
case OP_ADDRESS8:
sprintf(temp, " %s", num);
break;
case OP_ADDRESS16:
sprintf(temp, " %s", num);
break;
case OP_INDEXED8_X:
sprintf(temp, " %s,x", num);
break;
case OP_INDEXED8_Y:
sprintf(temp, " %s,y", num);
break;
case OP_INDEXED16_X:
sprintf(temp, " %s,x", num);
break;
case OP_INDEXED16_Y:
sprintf(temp, " %s,y", num);
break;
case OP_INDIRECT16:
sprintf(temp, " (%s)", num);
break;
case OP_X_INDIRECT8:
sprintf(temp, " (%s,x)", num);
break;
case OP_INDIRECT8_Y:
sprintf(temp, " (%s),y", num);
break;
case OP_RELATIVE:
sprintf(temp, " %s", num);
break;
}
}
// get cycle mode
int min = table_65xx_opcodes[opcode].cycles_min;
int max = table_65xx_opcodes[opcode].cycles_max;
if(op == OP_RELATIVE)
{
// branch, see if we're in the same page
int page1 = (address + 2) / 256;
int page2 = branch_address / 256;
if(page1 != page2)
max += 2;
else
max += 1;
}
strcat(instruction, temp);
*cycles_min = min;
*cycles_max = max;
}
else
{
// Could not figure out this opcode so return instruction as ???
strcpy(instruction, "???");
sprintf(temp, " 0x%02x", opcode);
strcat(instruction, temp);
return 0;
}
// set this to the number of bytes the operation took up
return op_bytes[op];
}
static uint16_t get_data(struct _simulate *simulate, int reg, int As, int bw)
{
struct _simulate_msp430 *simulate_msp430 = (struct _simulate_msp430 *)simulate->context;
if (reg == 3) // CG
{
if (As == 0)
{ return 0; }
else
if (As == 1)
{ return 1; }
else
if (As == 2)
{ return 2; }
else
if (As == 3)
{
if (bw == 0)
{ return 0xffff; }
else
{ return 0xff; }
}
}
if (As == 0) // Rn
{
if (bw == 0)
{ return simulate_msp430->reg[reg]; }
else
{ return simulate_msp430->reg[reg] & 0xff; }
}
if (reg == 2)
{
if (As == 1) // &LABEL
{
int PC=simulate_msp430->reg[0];
uint16_t a=READ_RAM(PC) | (READ_RAM(PC+1) << 8);
simulate_msp430->reg[0] += 2;
if (bw == 0)
{ return READ_RAM(a) | (READ_RAM(a+1) << 8); }
else
{ return READ_RAM(a); }
}
else
if (As == 2)
{ return 4; }
else
if (As == 3)
{ return 8; }
}
if (reg == 0) // PC
{
// This is probably worthless.. some other condition should pick this up
if (As == 3) // #immediate
{
uint16_t a = READ_RAM(simulate_msp430->reg[0]) | (READ_RAM(simulate_msp430->reg[0] + 1) << 8);
simulate_msp430->reg[0] += 2;
if (bw == 0)
{ return a; }
else
{ return a & 0xff; }
}
}
if (As == 1) // x(Rn)
{
uint16_t a = READ_RAM(simulate_msp430->reg[0]) | (READ_RAM(simulate_msp430->reg[0] + 1) << 8);
uint16_t index = simulate_msp430->reg[reg] + ((int16_t)a);
simulate_msp430->reg[0] += 2;
if (bw == 0)
{ return READ_RAM(index) | (READ_RAM(index+1) << 8); }
else
{ return READ_RAM(index); }
}
else
if (As == 2) // @Rn
{
if (bw == 0)
{ return READ_RAM(simulate_msp430->reg[reg]) | (READ_RAM(simulate_msp430->reg[reg] + 1) << 8); }
else
{ return READ_RAM(simulate_msp430->reg[reg]); }
}
else
if (As == 3) // @Rn+
{
uint16_t index = simulate_msp430->reg[reg];
if (bw == 0)
{
simulate_msp430->reg[reg] += 2;
return READ_RAM(index) | (READ_RAM(index+1) << 8);
}
else
{
simulate_msp430->reg[reg] += 1;
return READ_RAM(index);
}
}
printf("Error: Unrecognized addressing mode\n");
return 0;
}
static void sc61860_instruction(sc61860_state *cpustate)
{
int oper=READ_OP(cpustate);
if ((oper&0xc0)==0x80) {
sc61860_load_imm_p(cpustate, oper&0x3f);cpustate->icount-=2;
} else if ((oper&0xe0)==0xe0) {
sc61860_call(cpustate, READ_OP(cpustate)|((oper&0x1f)<<8));cpustate->icount-=7;
} else {
switch(oper) {
case 0: sc61860_load_imm(cpustate, I, READ_OP(cpustate));cpustate->icount-=4;break;
case 1: sc61860_load_imm(cpustate, J, READ_OP(cpustate));cpustate->icount-=4;break;
case 2: sc61860_load_imm(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
case 3: sc61860_load_imm(cpustate, B, READ_OP(cpustate));cpustate->icount-=4;break;
case 4: sc61860_inc_load_dp(cpustate, XL);cpustate->icount-=6;break;
case 5: sc61860_dec_load_dp(cpustate, XL);cpustate->icount-=6;break;
case 6: sc61860_inc_load_dp(cpustate, YL);cpustate->icount-=6;break;
case 7: sc61860_dec_load_dp(cpustate, YL);cpustate->icount-=6;break;
case 8: sc61860_copy(cpustate, READ_RAM(cpustate, I));break;
case 9: sc61860_exchange(cpustate, READ_RAM(cpustate, I));break;
case 10: sc61860_copy(cpustate, READ_RAM(cpustate, J));break;
case 11: sc61860_exchange(cpustate, READ_RAM(cpustate, J));break;
case 12: sc61860_add_bcd_a(cpustate);cpustate->icount-=7;break;
case 13: sc61860_sub_bcd_a(cpustate);cpustate->icount-=7;break;
case 14: sc61860_add_bcd(cpustate);cpustate->icount-=7;break;
case 15: sc61860_sub_bcd(cpustate);cpustate->icount-=7;break;
case 16: sc61860_load_dp(cpustate);cpustate->icount-=8;break;
case 17: sc61860_load_dl(cpustate);cpustate->icount-=5;break;
case 18: sc61860_load_imm_p(cpustate, READ_OP(cpustate));cpustate->icount-=4;break;
case 19: sc61860_load_imm_q(cpustate, READ_OP(cpustate));cpustate->icount-=4;break;
case 20: sc61860_add_word(cpustate);cpustate->icount-=5;break;
case 21: sc61860_sub_word(cpustate);cpustate->icount-=5;break;
case 24: sc61860_copy_ext(cpustate, READ_RAM(cpustate, I));break;
case 25: sc61860_exchange_ext(cpustate, READ_RAM(cpustate, I));break;
case 26: sc61860_copy_ext(cpustate, READ_RAM(cpustate, J));break;
case 27: sc61860_exchange_ext(cpustate, READ_RAM(cpustate, J));break;
case 28: sc61860_shift_right_nibble(cpustate);cpustate->icount-=5;break;
case 29: sc61860_shift_left_nibble(cpustate);cpustate->icount-=5;break;
case 30: sc61860_fill(cpustate);cpustate->icount-=5;break;
case 31: sc61860_fill_ext(cpustate);cpustate->icount-=4;break;
case 32: sc61860_store_p(cpustate);cpustate->icount-=2;break;
case 33: sc61860_store_q(cpustate);cpustate->icount-=2;break;
case 34: sc61860_store_r(cpustate);cpustate->icount-=2;break;
case 36: sc61860_inc_load_dp_load(cpustate);cpustate->icount-=7;break;
case 37: sc61860_dec_load_dp_load(cpustate);cpustate->icount-=7;break;
case 38: sc61860_inc_load_dp_store(cpustate);cpustate->icount-=7;break;
case 39: sc61860_dec_load_dp_store(cpustate);cpustate->icount-=7;break;
case 40: sc61860_jump_rel_plus(cpustate, !cpustate->zero);cpustate->icount-=4;break;
case 41: sc61860_jump_rel_minus(cpustate, !cpustate->zero);cpustate->icount-=4;break;
case 42: sc61860_jump_rel_plus(cpustate, !cpustate->carry);cpustate->icount-=4;break;
case 43: sc61860_jump_rel_minus(cpustate, !cpustate->carry);cpustate->icount-=4;break;
case 44: sc61860_jump_rel_plus(cpustate, TRUE);cpustate->icount-=4;break;
case 45: sc61860_jump_rel_minus(cpustate, TRUE);cpustate->icount-=4;break;
case 47: sc61860_loop(cpustate);cpustate->icount-=7;break;
case 48: sc61860_load_imm_p(cpustate, READ_RAM(cpustate, A));cpustate->icount-=2;break;
case 49: sc61860_load_imm_q(cpustate, READ_RAM(cpustate, A));cpustate->icount-=2;break;
case 50: sc61860_load_r(cpustate);cpustate->icount-=2;break;
case 52: sc61860_push(cpustate);cpustate->icount-=3;break;
case 53: sc61860_copy_int(cpustate, READ_RAM(cpustate, I));break;
case 55: sc61860_return(cpustate);cpustate->icount-=4;break;
case 56: sc61860_jump_rel_plus(cpustate, cpustate->zero);cpustate->icount-=4;break;
case 57: sc61860_jump_rel_minus(cpustate, cpustate->zero);cpustate->icount-=4;break;
case 58: sc61860_jump_rel_plus(cpustate, cpustate->carry);cpustate->icount-=4;break;
case 59: sc61860_jump_rel_minus(cpustate, cpustate->carry);cpustate->icount-=4;break;
case 64: sc61860_inc(cpustate, I);cpustate->icount-=4;break;
case 65: sc61860_dec(cpustate, I);cpustate->icount-=4;break;
case 66: sc61860_inc(cpustate, A);cpustate->icount-=4;break;
case 67: sc61860_dec(cpustate, A);cpustate->icount-=4;break;
case 68: sc61860_add(cpustate, cpustate->p, READ_RAM(cpustate, A));cpustate->icount-=3;break;
case 69: sc61860_sub(cpustate, cpustate->p, READ_RAM(cpustate, A));cpustate->icount-=3;break;
case 70: sc61860_and(cpustate, cpustate->p, READ_RAM(cpustate, A));cpustate->icount-=3;break;
case 71: sc61860_or(cpustate, cpustate->p, READ_RAM(cpustate, A));cpustate->icount-=3;break;
case 72: sc61860_inc(cpustate, K);cpustate->icount-=4;break;
case 73: sc61860_dec(cpustate, K);cpustate->icount-=4;break;
case 74: sc61860_inc(cpustate, V);cpustate->icount-=4;break;
case 75: sc61860_dec(cpustate, V);cpustate->icount-=4;break;
case 76: sc61860_in_a(cpustate);cpustate->icount-=2;break;
case 77: /*nopw*/;cpustate->icount-=2;break;
case 78: sc61860_wait(cpustate);cpustate->icount-=6;break;
case 79: sc61860_wait_x(cpustate, FALSE);cpustate->icount-=1;break;
case 80: sc61860_inc_p(cpustate);cpustate->icount-=2;break;
case 81: sc61860_dec_p(cpustate);cpustate->icount-=2;break;
case 82: sc61860_store_ext(cpustate, A);cpustate->icount-=2;break;
case 83: sc61860_store_ext(cpustate, cpustate->p);cpustate->icount-=2;break;
case 84: sc61860_load_imm(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=3/*?*/;break; // undocumented
case 85: sc61860_load_ext(cpustate, cpustate->p);cpustate->icount-=3;break;
case 86: sc61860_load_imm(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=3/*?*/;break; // undocumented
case 87: sc61860_load_ext(cpustate, A);cpustate->icount-=3;break;
case 88: sc61860_swap(cpustate);cpustate->icount-=2;break;
case 89: sc61860_load(cpustate);cpustate->icount-=2;break;
case 90: sc61860_rotate_left(cpustate);cpustate->icount-=2;break;
case 91: sc61860_pop(cpustate);cpustate->icount-=2;break;
case 93: sc61860_out_a(cpustate);cpustate->icount-=3;break;
case 95: sc61860_out_f(cpustate);cpustate->icount-=3;break;
case 96: sc61860_and(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
case 97: sc61860_or(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
case 98: sc61860_test(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
case 99: sc61860_cmp(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
case 100: sc61860_and(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
case 101: sc61860_or(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
case 102: sc61860_test(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
case 103: sc61860_cmp(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
case 105: sc61860_execute_table_call(cpustate);cpustate->icount-=3;break;
case 107: sc61860_test_special(cpustate);cpustate->icount-=4;break;
case 111: sc61860_wait_x(cpustate, TRUE);cpustate->icount-=1;break;
case 112: sc61860_add(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
case 113: sc61860_sub(cpustate, cpustate->p, READ_OP(cpustate));cpustate->icount-=4;break;
case 116: sc61860_add(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
case 117: sc61860_sub(cpustate, A, READ_OP(cpustate));cpustate->icount-=4;break;
case 120: sc61860_call(cpustate, READ_OP_ARG_WORD(cpustate));cpustate->icount-=8;break;
case 121: sc61860_jump(cpustate, 1);cpustate->icount-=6;break;
case 122: sc61860_prepare_table_call(cpustate);cpustate->icount-=9;break;
case 124: sc61860_jump(cpustate, !cpustate->zero);cpustate->icount-=6;break;
case 125: sc61860_jump(cpustate, !cpustate->carry);cpustate->icount-=6;break;
case 126: sc61860_jump(cpustate, cpustate->zero);cpustate->icount-=6;break;
case 127: sc61860_jump(cpustate, cpustate->carry);cpustate->icount-=6;break;
case 192: sc61860_inc(cpustate, J);cpustate->icount-=4;break;
case 193: sc61860_dec(cpustate, J);cpustate->icount-=4;break;
case 194: sc61860_inc(cpustate, B);cpustate->icount-=4;break;
case 195: sc61860_dec(cpustate, B);cpustate->icount-=4;break;
case 196: sc61860_add_carry(cpustate);cpustate->icount-=3;break;
case 197: sc61860_sub_carry(cpustate);cpustate->icount-=3;break;
case 199: sc61860_cmp(cpustate, cpustate->p, READ_RAM(cpustate, A));cpustate->icount-=3;break;
case 200: sc61860_inc(cpustate, L);cpustate->icount-=4;break;
case 201: sc61860_dec(cpustate, L);cpustate->icount-=4;break;
case 202: sc61860_inc(cpustate, W);cpustate->icount-=4;break;
case 203: sc61860_dec(cpustate, W);cpustate->icount-=4;break;
case 204: sc61860_in_b(cpustate);cpustate->icount-=2;break;
case 206: /*nopt*/;cpustate->icount-=3;break;
case 208: sc61860_set_carry(cpustate);cpustate->icount-=2;break;
case 209: sc61860_reset_carry(cpustate);cpustate->icount-=4;break;
case 210: sc61860_rotate_right(cpustate);cpustate->icount-=2;break;
case 212: sc61860_and_ext(cpustate);cpustate->icount-=6;break;
case 213: sc61860_or_ext(cpustate);cpustate->icount-=6;break;
case 214: sc61860_test_ext(cpustate);cpustate->icount-=6;break;
case 216: sc61860_leave(cpustate);cpustate->icount-=2;break;
case 218: sc61860_exam(cpustate, A, B);cpustate->icount-=3;break;
case 219: sc61860_exam(cpustate, A, cpustate->p);cpustate->icount-=3;break;
case 221: sc61860_out_b(cpustate);cpustate->icount-=2;break;
case 223: sc61860_out_c(cpustate);cpustate->icount-=2;break;
default: logerror("sc61860 illegal opcode at %.4x %.2x\n",cpustate->pc-1, oper);
}
}
}
int disasm_68hc08(struct _memory *memory, int address, char *instruction, int *cycles_min, int *cycles_max)
{
//int bit_instr;
int opcode;
int size=1;
int n;
strcpy(instruction, "???");
*cycles_min=-1;
*cycles_max=-1;
opcode=READ_RAM(address);
if (m68hc08_table[opcode].instr==NULL)
{
opcode=READ_RAM16(address);
n=0;
while(m68hc08_16_table[n].instr!=NULL)
{
if (m68hc08_16_table[n].opcode==opcode)
{
switch(m68hc08_16_table[n].operand_type)
{
case CPU08_OP_OPR8_SP:
sprintf(instruction, "%s $%02x,SP", m68hc08_16_table[n].instr, READ_RAM(address+2));
size=3;
break;
case CPU08_OP_OPR8_SP_REL:
sprintf(instruction, "%s $%02x,SP,$%04x", m68hc08_16_table[n].instr, READ_RAM(address+2), (address+4)+((char)READ_RAM(address+3)));
size=4;
break;
case CPU08_OP_OPR16_SP:
sprintf(instruction, "%s $%04x,SP", m68hc08_16_table[n].instr, READ_RAM16(address+2));
size=4;
break;
}
*cycles_min=m68hc08_16_table[n].cycles;
*cycles_max=m68hc08_16_table[n].cycles;
break;
}
n++;
}
return size;
}
*cycles_min=m68hc08_table[opcode].cycles;
*cycles_max=m68hc08_table[opcode].cycles;
switch(m68hc08_table[opcode].operand_type)
{
case CPU08_OP_NONE:
sprintf(instruction, "%s", m68hc08_table[opcode].instr);
break;
case CPU08_OP_NUM16:
sprintf(instruction, "%s #$%04x", m68hc08_table[opcode].instr, READ_RAM16(address+1));
size=3;
break;
case CPU08_OP_NUM8:
sprintf(instruction, "%s #$%02x", m68hc08_table[opcode].instr, READ_RAM(address+1));
size=2;
break;
case CPU08_OP_NUM8_OPR8:
sprintf(instruction, "%s #$%02x,$%02x", m68hc08_table[opcode].instr, READ_RAM(address+1), READ_RAM(address+2));
size=3;
break;
case CPU08_OP_NUM8_REL:
sprintf(instruction, "%s #$%02x, $%04x (%d)", m68hc08_table[opcode].instr, READ_RAM(address+1), (address+3)+((char)READ_RAM(address+2)), (char)READ_RAM(address+2));
size=3;
break;
case CPU08_OP_OPR16:
sprintf(instruction, "%s $%04x", m68hc08_table[opcode].instr, READ_RAM16(address+1));
size=3;
break;
case CPU08_OP_OPR16_X:
sprintf(instruction, "%s $%04x,X", m68hc08_table[opcode].instr, READ_RAM16(address+1));
size=3;
break;
case CPU08_OP_OPR8:
sprintf(instruction, "%s $%02x", m68hc08_table[opcode].instr, READ_RAM(address+1));
size=2;
break;
case CPU08_OP_OPR8_OPR8:
sprintf(instruction, "%s $%02x,$%02x", m68hc08_table[opcode].instr, READ_RAM(address+1), READ_RAM(address+2));
size=3;
break;
case CPU08_OP_OPR8_REL:
sprintf(instruction, "%s $%02x,$%04x (%d)", m68hc08_table[opcode].instr, READ_RAM(address+1), ((address+3)+(char)READ_RAM(address+2)), (char)READ_RAM(address+2));
size=3;
break;
case CPU08_OP_OPR8_X:
sprintf(instruction, "%s %02x,X", m68hc08_table[opcode].instr, READ_RAM(address+1));
size=2;
break;
case CPU08_OP_OPR8_X_PLUS:
sprintf(instruction, "%s $%02x,X+", m68hc08_table[opcode].instr, READ_RAM(address+1));
size=2;
break;
case CPU08_OP_OPR8_X_PLUS_REL:
sprintf(instruction, "%s $%02x,X+,$%04x (%d)", m68hc08_table[opcode].instr, READ_RAM(address+1), (address+3)+((char)READ_RAM(address+2)), (char)READ_RAM(address+2));
size=3;
break;
case CPU08_OP_OPR8_X_REL:
sprintf(instruction, "%s $%02x,X,$%04x (%d)", m68hc08_table[opcode].instr, READ_RAM(address+1), (address+3)+((char)READ_RAM(address+2)), (char)READ_RAM(address+2));
size=3;
break;
case CPU08_OP_REL:
sprintf(instruction, "%s $%04x (%d)", m68hc08_table[opcode].instr, (address+2)+((char)READ_RAM(address+1)), (char)READ_RAM(address+1));
size=2;
break;
case CPU08_OP_COMMA_X:
sprintf(instruction, "%s ,X", m68hc08_table[opcode].instr);
break;
case CPU08_OP_X:
sprintf(instruction, "%s X", m68hc08_table[opcode].instr);
break;
case CPU08_OP_X_PLUS_OPR8:
sprintf(instruction, "%s ,X+,$%02x", m68hc08_table[opcode].instr, READ_RAM(address+1));
size=2;
break;
case CPU08_OP_X_PLUS_REL:
sprintf(instruction, "%s ,X+,$%04x (%d)", m68hc08_table[opcode].instr, (address+2)+((char)READ_RAM(address+1)), (char)READ_RAM(address+1));
size=2;
break;
case CPU08_OP_X_REL:
sprintf(instruction, "%s ,X,$%04x (%d)", m68hc08_table[opcode].instr, (address+2)+((char)READ_RAM(address+1)), (char)READ_RAM(address+1));
size=2;
break;
case CPU08_OP_0_COMMA_OPR:
case CPU08_OP_1_COMMA_OPR:
case CPU08_OP_2_COMMA_OPR:
case CPU08_OP_3_COMMA_OPR:
case CPU08_OP_4_COMMA_OPR:
case CPU08_OP_5_COMMA_OPR:
case CPU08_OP_6_COMMA_OPR:
case CPU08_OP_7_COMMA_OPR:
sprintf(instruction, "%s %d,$%02x", m68hc08_table[opcode].instr, m68hc08_table[opcode].operand_type-CPU08_OP_0_COMMA_OPR, READ_RAM(address+1));
size=2;
break;
case CPU08_OP_0_COMMA_OPR_REL:
case CPU08_OP_1_COMMA_OPR_REL:
case CPU08_OP_2_COMMA_OPR_REL:
case CPU08_OP_3_COMMA_OPR_REL:
case CPU08_OP_4_COMMA_OPR_REL:
case CPU08_OP_5_COMMA_OPR_REL:
case CPU08_OP_6_COMMA_OPR_REL:
case CPU08_OP_7_COMMA_OPR_REL:
sprintf(instruction, "%s %d,$%02x,$%04x (%d)", m68hc08_table[opcode].instr, m68hc08_table[opcode].operand_type-CPU08_OP_0_COMMA_OPR_REL, READ_RAM(address+1), (address+3)+(char)READ_RAM(address+2), (char)READ_RAM(address+2));
size=3;
break;
}
return size;
}
