static irqreturn_t rmtctl_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned int status, ir_data, scancode, vendor;
unsigned char *key;
int i;
/* Get IR status. */
status = REG32_VAL(IRSTS);
/* Check 'IR received data' flag. */
if ((status & 0x1) == 0x0) {
printk("IR IRQ was triggered without data received. (0x%x)\n",
status);
return IRQ_NONE;
}
/* Read IR data. */
ir_data = REG32_VAL(IRDATA(0)) ;
//printk("orig data 0x%08x \n",ir_data);
key = (char *) &ir_data;
/* clear INT status*/
REG32_VAL(IRSTS)=0x1 ;
if (RMTCTL_DEBUG){
printk("ir_data = 0x%08x, status = 0x%x \n", ir_data, status);
//printk("HZ %d jiffies 0x%08x \n ",HZ,jiffies);
}
/* Get vendor ID. */
vendor = (key[0] << 8) | (key[1]);
/* Check if key is valid. Key[3] is XORed t o key[2]. */
if (key[2] & key[3]) {
printk("Invalid IR key received. (0x%x, 0x%x)\n", key[2], key[3]);
return IRQ_NONE;
}
/* Keycode mapping. */
scancode = key[2]; //default
if (RMTCTL_DEBUG) printk(">> dev_tot_num %d\n",dev_tot_num);
for (i=0; i < dev_tot_num; i++)
{
if (vendor == rmt_dev_tbl[i].vender_id){
scancode = rmt_dev_tbl[i].key_codes[key[2]];
if (RMTCTL_DEBUG) printk(" vender_name %s id 0x%04x scan code %d \n", rmt_dev_tbl[i].vendor_name,vendor,i);
break;
}
}
if (RMTCTL_DEBUG)
printk("scancode = 0x%08x \n", scancode);
/* Check 'IR code repeat' flag. */
if ((status & 0x2) || (scancode == KEY_RESERVED)) {
/* Ignore repeated or reserved keys. */
} else {
if (RMTCTL_DEBUG) printk(KERN_ERR"%d ---------IR report key 0x%x\n" ,cirisrcnt++,scancode);
input_report_key(idev, scancode, 1);
input_report_key(idev, scancode, 0);
input_sync(idev);
}
return IRQ_HANDLED;
}
static void rmtctl_hw_suspend(void)
{
//REG32_VAL(WAKEUP_CMD1(0))=0xf10ebf40;
REG32_VAL(WAKEUP_CMD1(0))=0x23dc4cb3;
REG32_VAL(WAKEUP_CMD1(1))=0x0;
REG32_VAL(WAKEUP_CMD1(2))=0x0;
REG32_VAL(WAKEUP_CMD1(3))=0x0;
REG32_VAL(WAKEUP_CMD1(4))=0x0;
REG32_VAL(WAKEUP_CMD2(0))=0xa857fd02;//0xff00ff00;
REG32_VAL(WAKEUP_CMD2(1))=0x0;
REG32_VAL(WAKEUP_CMD2(2))=0x0;
REG32_VAL(WAKEUP_CMD2(3))=0x0;
REG32_VAL(WAKEUP_CMD2(4))=0x0;
#ifdef RMT_CFG_WAKUP_BY_ANY_KEY
REG32_VAL(WAKEUP_CTRL) = 0x001;
#else
REG32_VAL(WAKEUP_CTRL) = 0x101;
#endif
}
static void rmtctl_hw_init(void)
{
unsigned int st;
/* Turn off CIR SW reset. */
REG32_VAL(IRSWRST) = 1;
REG32_VAL(IRSWRST) = 0;
REG32_VAL(PARAMETER(0)) = 0x10a;
REG32_VAL(PARAMETER(1)) = 0x8E;
REG32_VAL(PARAMETER(2)) = 0x42;
REG32_VAL(PARAMETER(3)) = 0x55;
REG32_VAL(PARAMETER(4)) = 0x9;
REG32_VAL(PARAMETER(5)) = 0x13;
REG32_VAL(PARAMETER(6)) = 0x13;
#ifdef RMT_CFG_REPEAT_KEY
REG32_VAL(NEC_REPEAT_TIME_OUT_CTRL) = 0x1;
REG32_VAL(NEC_REPEAT_TIME_OUT_COUNT) = 17965000;//(107.9ms * 1000000)/(1000/166.5)
REG32_VAL(IRCTL) = 0X100;//NEC repeat key
#else
REG32_VAL(IRCTL) = 0;//NEC repeat key
#endif
#ifdef RMT_CFG_FACTORY_NEC
REG32_VAL(IRCTL) |= (0x20<<16) ; //BIT16-23->0x20, BIT 24,25 -> 0
#else //NEC
REG32_VAL(IRCTL) |= (0x0<<16) |(0x1<<25);
#endif
#ifdef RMT_CFG_INT_CNT
REG32_VAL(INT_MASK_CTRL) = 0x1;
REG32_VAL(INT_MASK_COUNT) =50*1000000*1/3;//0x47868C0/4;//count for 1 sec 0x47868C0
#endif
/* Set IR remoter vendor type */
/* BIT[0]: IR Circuit Enable. */
REG32_VAL(IRCTL) |= 0x1; /* IR_EN */
/* Read CIR status to clear IR interrupt. */
st = REG32_VAL(IRSTS);
}
int wmt_vid_open(vid_mode mode, cmos_uboot_env_t *uboot_env)
{
int value, int_ctrl;
TRACE("Enter\n");
vid_i2c_gpio_en = uboot_env->i2c_gpio_en;
DBG_INFO(" vid_i2c_gpio_en 0x%08x \n",vid_i2c_gpio_en);
if ((vid_i2c_gpio_en) && (uboot_env != NULL))
{
memset(&vid_i2c0_scl, 0, sizeof(vid_i2c0_scl));
memset(&vid_i2c0_sda, 0, sizeof(vid_i2c0_sda));
vid_i2c0_scl.bit_mask = 1 << uboot_env->i2c_gpio_scl_binum;
vid_i2c0_scl.pull_en_bit_mask = 1 << uboot_env->reg_i2c_gpio_scl_gpio_pe_bitnum;
vid_i2c0_scl.data_in = uboot_env->reg_i2c_gpio_scl_gpio_in ;
vid_i2c0_scl.gpio_en = uboot_env->reg_i2c_gpio_scl_gpio_en ;
vid_i2c0_scl.out_en = uboot_env->reg_i2c_gpio_scl_gpio_od ;
vid_i2c0_scl.data_out = uboot_env->reg_i2c_gpio_scl_gpio_oc ;
vid_i2c0_scl.pull_en = uboot_env->reg_i2c_gpio_scl_gpio_pe ;
vid_i2c0_sda.bit_mask = 1 << uboot_env->i2c_gpio_sda_binum;
vid_i2c0_sda.pull_en_bit_mask = 1 << uboot_env->reg_i2c_gpio_sda_gpio_pe_bitnum;
vid_i2c0_sda.data_in = uboot_env->reg_i2c_gpio_sda_gpio_in ;
vid_i2c0_sda.gpio_en = uboot_env->reg_i2c_gpio_sda_gpio_en ;
vid_i2c0_sda.out_en = uboot_env->reg_i2c_gpio_sda_gpio_od ;
vid_i2c0_sda.data_out = uboot_env->reg_i2c_gpio_sda_gpio_oc ;
vid_i2c0_sda.pull_en = uboot_env->reg_i2c_gpio_sda_gpio_pe ;
if (vid_i2c0_scl.data_in & 0x1)
{
vid_i2c0_scl.bit_mask <<= 8;
vid_i2c0_scl.pull_en_bit_mask <<= 8;
vid_i2c0_scl.data_in -= 1;
vid_i2c0_scl.gpio_en -= 1;
vid_i2c0_scl.out_en -= 1;
vid_i2c0_scl.data_out -= 1;
vid_i2c0_scl.pull_en -= 1;
}
if (vid_i2c0_sda.data_in & 0x1)
{
vid_i2c0_sda.bit_mask <<= 8;
vid_i2c0_sda.pull_en_bit_mask <<= 8;
vid_i2c0_sda.data_in -= 1;
vid_i2c0_sda.gpio_en -= 1;
vid_i2c0_sda.out_en -= 1;
vid_i2c0_sda.data_out -= 1;
vid_i2c0_sda.pull_en -= 1;
}
vid_swi2c.scl_reg = &vid_i2c0_scl;
vid_swi2c.sda_reg = &vid_i2c0_sda;
DBG_INFO("SCL 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \n",vid_i2c0_scl.bit_mask,vid_i2c0_scl.pull_en_bit_mask,vid_i2c0_scl.data_in,vid_i2c0_scl.gpio_en,vid_i2c0_scl.out_en,vid_i2c0_scl.data_out, vid_i2c0_scl.pull_en);
DBG_INFO("SDA 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \n",vid_i2c0_sda.bit_mask,vid_i2c0_sda.pull_en_bit_mask,vid_i2c0_sda.data_in,vid_i2c0_sda.gpio_en,vid_i2c0_sda.out_en,vid_i2c0_sda.data_out, vid_i2c0_sda.pull_en );
}
/*--------------------------------------------------------------------------
Step 1: Init GPIO for CMOS or TVDEC mode
--------------------------------------------------------------------------*/
vid_gpio_init(mode);
/*--------------------------------------------------------------------------
Step 2: Init CMOS or TVDEC module
--------------------------------------------------------------------------*/
value = REG32_VAL(REG_VID_TVDEC_CTRL);
VID_REG_SET32( REG_VID_MEMIF_EN, 0x1 );
VID_REG_SET32( REG_VID_OUTPUT_FORMAT, 0x0 ); // 0: 422 1: 444
int_ctrl = 0x00;
if(mode == VID_MODE_CMOS) {
VID_REG_SET32( REG_VID_TVDEC_CTRL, (value & 0xFFFFFFE)); /* disable TV decoder */
VID_REG_SET32( REG_VID_CMOS_PIXEL_SWAP, 0x2); /* 0x2 for YUYV */
#ifdef VID_INT_MODE
int_ctrl = 0x0808;
#endif
VID_REG_SET32( REG_VID_INT_CTRL, int_ctrl );
}
else {
VID_REG_SET32( REG_VID_TVDEC_CTRL, (value | 0x1) ); /* enable TV decoder */
#ifdef VID_INT_MODE
int_ctrl = 0x0404;
#endif
VID_REG_SET32( REG_VID_INT_CTRL, int_ctrl );
VID_REG_SET32( REG_VID_CMOS_EN, 0x0); /* disable CMOS */
wmt_vid_set_common_mode(VID_NTSC);
}
cur_y_addr = 0;
cur_c_addr = 0;
_cur_fb = 0;
_prev_fb = 0;
spin_lock_init(&vid_lock);
TRACE("Leave\n");
return 0;
} /* End of wmt_vid_open() */