static int
reload_cse_simplify_operands (rtx insn, rtx testreg)
{
int i, j;
/* For each operand, all registers that are equivalent to it. */
HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
const char *constraints[MAX_RECOG_OPERANDS];
/* Vector recording how bad an alternative is. */
int *alternative_reject;
/* Vector recording how many registers can be introduced by choosing
this alternative. */
int *alternative_nregs;
/* Array of vectors recording, for each operand and each alternative,
which hard register to substitute, or -1 if the operand should be
left as it is. */
int *op_alt_regno[MAX_RECOG_OPERANDS];
/* Array of alternatives, sorted in order of decreasing desirability. */
int *alternative_order;
extract_insn (insn);
if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
return 0;
/* Figure out which alternative currently matches. */
if (! constrain_operands (1))
fatal_insn_not_found (insn);
alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives);
alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives);
alternative_order = XALLOCAVEC (int, recog_data.n_alternatives);
memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
/* For each operand, find out which regs are equivalent. */
for (i = 0; i < recog_data.n_operands; i++)
{
cselib_val *v;
struct elt_loc_list *l;
rtx op;
enum machine_mode mode;
CLEAR_HARD_REG_SET (equiv_regs[i]);
/* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
right, so avoid the problem here. Likewise if we have a constant
and the insn pattern doesn't tell us the mode we need. */
if (LABEL_P (recog_data.operand[i])
|| (CONSTANT_P (recog_data.operand[i])
&& recog_data.operand_mode[i] == VOIDmode))
continue;
op = recog_data.operand[i];
mode = GET_MODE (op);
#ifdef LOAD_EXTEND_OP
if (MEM_P (op)
&& GET_MODE_BITSIZE (mode) < BITS_PER_WORD
&& LOAD_EXTEND_OP (mode) != UNKNOWN)
{
rtx set = single_set (insn);
/* We might have multiple sets, some of which do implicit
extension. Punt on this for now. */
if (! set)
continue;
/* If the destination is also a MEM or a STRICT_LOW_PART, no
extension applies.
Also, if there is an explicit extension, we don't have to
worry about an implicit one. */
else if (MEM_P (SET_DEST (set))
|| GET_CODE (SET_DEST (set)) == STRICT_LOW_PART
|| GET_CODE (SET_SRC (set)) == ZERO_EXTEND
|| GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
; /* Continue ordinary processing. */
#ifdef CANNOT_CHANGE_MODE_CLASS
/* If the register cannot change mode to word_mode, it follows that
it cannot have been used in word_mode. */
else if (REG_P (SET_DEST (set))
&& CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
word_mode,
REGNO_REG_CLASS (REGNO (SET_DEST (set)))))
; /* Continue ordinary processing. */
#endif
/* If this is a straight load, make the extension explicit. */
else if (REG_P (SET_DEST (set))
&& recog_data.n_operands == 2
&& SET_SRC (set) == op
&& SET_DEST (set) == recog_data.operand[1-i])
{
validate_change (insn, recog_data.operand_loc[i],
gen_rtx_fmt_e (LOAD_EXTEND_OP (mode),
word_mode, op),
1);
validate_change (insn, recog_data.operand_loc[1-i],
gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
1);
if (! apply_change_group ())
return 0;
return reload_cse_simplify_operands (insn, testreg);
}
else
/* ??? There might be arithmetic operations with memory that are
safe to optimize, but is it worth the trouble? */
continue;
}
#endif /* LOAD_EXTEND_OP */
v = cselib_lookup (op, recog_data.operand_mode[i], 0);
if (! v)
continue;
for (l = v->locs; l; l = l->next)
if (REG_P (l->loc))
SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
}
for (i = 0; i < recog_data.n_operands; i++)
{
enum machine_mode mode;
int regno;
const char *p;
op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives);
for (j = 0; j < recog_data.n_alternatives; j++)
op_alt_regno[i][j] = -1;
p = constraints[i] = recog_data.constraints[i];
mode = recog_data.operand_mode[i];
/* Add the reject values for each alternative given by the constraints
for this operand. */
j = 0;
while (*p != '\0')
{
char c = *p++;
if (c == ',')
j++;
else if (c == '?')
alternative_reject[j] += 3;
else if (c == '!')
alternative_reject[j] += 300;
}
/* We won't change operands which are already registers. We
also don't want to modify output operands. */
regno = true_regnum (recog_data.operand[i]);
if (regno >= 0
|| constraints[i][0] == '='
|| constraints[i][0] == '+')
continue;
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
{
int rclass = (int) NO_REGS;
if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
continue;
SET_REGNO (testreg, regno);
PUT_MODE (testreg, mode);
/* We found a register equal to this operand. Now look for all
alternatives that can accept this register and have not been
assigned a register they can use yet. */
j = 0;
p = constraints[i];
for (;;)
{
char c = *p;
switch (c)
{
case '=': case '+': case '?':
case '#': case '&': case '!':
case '*': case '%':
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
case '<': case '>': case 'V': case 'o':
case 'E': case 'F': case 'G': case 'H':
case 's': case 'i': case 'n':
case 'I': case 'J': case 'K': case 'L':
case 'M': case 'N': case 'O': case 'P':
case 'p': case 'X': case TARGET_MEM_CONSTRAINT:
/* These don't say anything we care about. */
break;
case 'g': case 'r':
rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS];
break;
default:
rclass
= (reg_class_subunion
[(int) rclass]
[(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
break;
case ',': case '\0':
/* See if REGNO fits this alternative, and set it up as the
replacement register if we don't have one for this
alternative yet and the operand being replaced is not
a cheap CONST_INT. */
if (op_alt_regno[i][j] == -1
&& reg_fits_class_p (testreg, rclass, 0, mode)
&& (GET_CODE (recog_data.operand[i]) != CONST_INT
|| (rtx_cost (recog_data.operand[i], SET,
optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
> rtx_cost (testreg, SET,
optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn))))))
{
alternative_nregs[j]++;
op_alt_regno[i][j] = regno;
}
j++;
rclass = (int) NO_REGS;
break;
}
p += CONSTRAINT_LEN (c, p);
if (c == '\0')
break;
}
}
}
/* Record all alternatives which are better or equal to the currently
matching one in the alternative_order array. */
for (i = j = 0; i < recog_data.n_alternatives; i++)
if (alternative_reject[i] <= alternative_reject[which_alternative])
alternative_order[j++] = i;
recog_data.n_alternatives = j;
/* Sort it. Given a small number of alternatives, a dumb algorithm
won't hurt too much. */
for (i = 0; i < recog_data.n_alternatives - 1; i++)
{
int best = i;
int best_reject = alternative_reject[alternative_order[i]];
int best_nregs = alternative_nregs[alternative_order[i]];
int tmp;
for (j = i + 1; j < recog_data.n_alternatives; j++)
{
int this_reject = alternative_reject[alternative_order[j]];
int this_nregs = alternative_nregs[alternative_order[j]];
if (this_reject < best_reject
|| (this_reject == best_reject && this_nregs > best_nregs))
{
best = j;
best_reject = this_reject;
best_nregs = this_nregs;
}
}
tmp = alternative_order[best];
alternative_order[best] = alternative_order[i];
alternative_order[i] = tmp;
}
/* Substitute the operands as determined by op_alt_regno for the best
alternative. */
j = alternative_order[0];
for (i = 0; i < recog_data.n_operands; i++)
{
enum machine_mode mode = recog_data.operand_mode[i];
if (op_alt_regno[i][j] == -1)
continue;
validate_change (insn, recog_data.operand_loc[i],
gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
}
for (i = recog_data.n_dups - 1; i >= 0; i--)
{
int op = recog_data.dup_num[i];
enum machine_mode mode = recog_data.operand_mode[op];
if (op_alt_regno[op][j] == -1)
continue;
validate_change (insn, recog_data.dup_loc[i],
gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
}
return apply_change_group ();
}
static bool
combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set)
{
rtx orig_src = SET_SRC (*orig_set);
rtx new_reg = gen_rtx_REG (cand->mode, REGNO (SET_DEST (*orig_set)));
rtx new_set;
/* Merge constants by directly moving the constant into the register under
some conditions. Recall that RTL constants are sign-extended. */
if (GET_CODE (orig_src) == CONST_INT
&& HOST_BITS_PER_WIDE_INT >= GET_MODE_BITSIZE (cand->mode))
{
if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND)
new_set = gen_rtx_SET (VOIDmode, new_reg, orig_src);
else
{
/* Zero-extend the negative constant by masking out the bits outside
the source mode. */
enum machine_mode src_mode = GET_MODE (SET_DEST (*orig_set));
rtx new_const_int
= gen_int_mode (INTVAL (orig_src) & GET_MODE_MASK (src_mode),
GET_MODE (new_reg));
new_set = gen_rtx_SET (VOIDmode, new_reg, new_const_int);
}
}
else if (GET_MODE (orig_src) == VOIDmode)
{
/* This is mostly due to a call insn that should not be optimized. */
return false;
}
else if (GET_CODE (orig_src) == cand->code)
{
/* Here is a sequence of two extensions. Try to merge them. */
rtx temp_extension
= gen_rtx_fmt_e (cand->code, cand->mode, XEXP (orig_src, 0));
rtx simplified_temp_extension = simplify_rtx (temp_extension);
if (simplified_temp_extension)
temp_extension = simplified_temp_extension;
new_set = gen_rtx_SET (VOIDmode, new_reg, temp_extension);
}
else if (GET_CODE (orig_src) == IF_THEN_ELSE)
{
/* Only IF_THEN_ELSE of phi-type copies are combined. Otherwise,
in general, IF_THEN_ELSE should not be combined. */
return false;
}
else
{
/* This is the normal case. */
rtx temp_extension
= gen_rtx_fmt_e (cand->code, cand->mode, orig_src);
rtx simplified_temp_extension = simplify_rtx (temp_extension);
if (simplified_temp_extension)
temp_extension = simplified_temp_extension;
new_set = gen_rtx_SET (VOIDmode, new_reg, temp_extension);
}
/* This change is a part of a group of changes. Hence,
validate_change will not try to commit the change. */
if (validate_change (curr_insn, orig_set, new_set, true))
{
if (dump_file)
{
fprintf (dump_file,
"Tentatively merged extension with definition:\n");
print_rtl_single (dump_file, curr_insn);
}
return true;
}
return false;
}
static int
reload_cse_simplify_set (rtx set, rtx insn)
{
int did_change = 0;
int dreg;
rtx src;
enum reg_class dclass;
int old_cost;
cselib_val *val;
struct elt_loc_list *l;
#ifdef LOAD_EXTEND_OP
enum rtx_code extend_op = UNKNOWN;
#endif
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
dreg = true_regnum (SET_DEST (set));
if (dreg < 0)
return 0;
src = SET_SRC (set);
if (side_effects_p (src) || true_regnum (src) >= 0)
return 0;
dclass = REGNO_REG_CLASS (dreg);
#ifdef LOAD_EXTEND_OP
/* When replacing a memory with a register, we need to honor assumptions
that combine made wrt the contents of sign bits. We'll do this by
generating an extend instruction instead of a reg->reg copy. Thus
the destination must be a register that we can widen. */
if (MEM_P (src)
&& GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
&& (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN
&& !REG_P (SET_DEST (set)))
return 0;
#endif
val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
if (! val)
return 0;
/* If memory loads are cheaper than register copies, don't change them. */
if (MEM_P (src))
old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
else if (REG_P (src))
old_cost = REGISTER_MOVE_COST (GET_MODE (src),
REGNO_REG_CLASS (REGNO (src)), dclass);
else
old_cost = rtx_cost (src, SET, speed);
for (l = val->locs; l; l = l->next)
{
rtx this_rtx = l->loc;
int this_cost;
if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
{
#ifdef LOAD_EXTEND_OP
if (extend_op != UNKNOWN)
{
HOST_WIDE_INT this_val;
/* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
constants, such as SYMBOL_REF, cannot be extended. */
if (GET_CODE (this_rtx) != CONST_INT)
continue;
this_val = INTVAL (this_rtx);
switch (extend_op)
{
case ZERO_EXTEND:
this_val &= GET_MODE_MASK (GET_MODE (src));
break;
case SIGN_EXTEND:
/* ??? In theory we're already extended. */
if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
break;
default:
gcc_unreachable ();
}
this_rtx = GEN_INT (this_val);
}
#endif
this_cost = rtx_cost (this_rtx, SET, speed);
}
else if (REG_P (this_rtx))
{
#ifdef LOAD_EXTEND_OP
if (extend_op != UNKNOWN)
{
this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
this_cost = rtx_cost (this_rtx, SET, speed);
}
else
#endif
this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
REGNO_REG_CLASS (REGNO (this_rtx)),
dclass);
}
else
continue;
/* If equal costs, prefer registers over anything else. That
tends to lead to smaller instructions on some machines. */
if (this_cost < old_cost
|| (this_cost == old_cost
&& REG_P (this_rtx)
&& !REG_P (SET_SRC (set))))
{
#ifdef LOAD_EXTEND_OP
if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
&& extend_op != UNKNOWN
#ifdef CANNOT_CHANGE_MODE_CLASS
&& !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
word_mode,
REGNO_REG_CLASS (REGNO (SET_DEST (set))))
#endif
)
{
rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
validate_change (insn, &SET_DEST (set), wide_dest, 1);
}
#endif
validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
old_cost = this_cost, did_change = 1;
}
}
return did_change;
}
