} static const struct reg_script pch_misc_init_script[] = { /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ REG_PCI_RMW16(GEN_PMCON_3, ~((3 << 4)|(1 << 10)), (1 << 3)|(1 << 11)|(1 << 12)), /* Prepare sleep mode */ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), /* Setup NMI on errors, disable SERR */ REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), /* Disable NMI sources */ REG_IO_OR8(0x70, (1 << 7)), /* Indicate DRAM init done for MRC */ REG_PCI_OR8(GEN_PMCON_2, (1 << 7)), /* Enable BIOS updates outside of SMM */ REG_PCI_RMW8(0xdc, ~(1 << 5), 0), /* Clear status bits to prevent unexpected wake */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f), REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), /* Enable PCIe Releaxed Order */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), /* Setup SERIRQ, enable continuous mode */ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), #if !CONFIG_SERIRQ_CONTINUOUS_MODE REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), #endif REG_SCRIPT_END }; /* Magic register settings for power management */
REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8164, 0x000000ff), /* BAR + 0x0010[10,9,5]=110b */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0010, ~0x00000020, 0x00000600), /* BAR + 0x8058[20,16,8]=110b */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), /* BAR + 0x8060[25]=1b */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), /* BAR + 0x80f0[20]=0b */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0), /* BAR + 0x8008[19]=1b (to enable LPM) */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8008, 0x00080000), /* BAR + 0x80fc[25]=1b */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x80fc, 0x02000000), /* 0x40/0x44 are written as bytes to avoid touching bit31 */ /* D20:F0:40[21,20,18,10,9,8]=111001b (don't write byte3) */ REG_PCI_RMW8(0x41, ~0x06, 0x01), /* Except [21,20,19,18]=0001b USB wake W/A is disable IIL1E */ REG_PCI_RMW8(0x42, 0x3c, 0x04), /* D20:F0:44[19:14,10,9,7,3:0]=1 (don't write byte3) */ REG_PCI_RMW8(0x44, 0x00, 0x8f), REG_PCI_RMW8(0x45, ~0xcf, 0xc6), REG_PCI_RMW8(0x46, ~0x0f, 0x0f), /* BAR + 0x8140 = 0xff00f03c */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8140, 0, 0xff00f03c), REG_SCRIPT_END }; const struct reg_script xhci_init_boot_script[] = { /* Setup USB3 phy */ REG_SCRIPT_NEXT(usb3_phy_script), /* Initialize host controller */
static const struct reg_script init_ops[] = { /* Enable no snoop traffic. */ REG_PCI_OR16(0x78, 1 << 11), /* Configure HDMI codec connection. */ REG_PCI_OR32(0xc4, 1 << 1), REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00), /* Configure internal settings. */ REG_PCI_OR32(0xc0, 0x7 << 21), REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)), REG_PCI_WRITE32(0xc8, 0x82a30000), REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0), /* Disable docking. */ REG_PCI_RMW8(0x4d, ~(1 << 7), 0), REG_SCRIPT_END, }; static const uint32_t hdmi_codec_verb_table[] = { /* coreboot specific header */ 0x80862882, /* vid did for hdmi codec */ 0x00000000, /* subsystem id */ 0x00000003, /* number of jacks */ /* pin widget 5 - port B */ 0x20471c10, 0x20471d00, 0x20471e56, 0x20471f18,
/* Controller primary interface reset */ REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, SOCCLKEN_CONFIG_BB_RST_B), /* Set the mixer load resistance */ REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, OCFGPIMIXLOAD_1_0_MASK), REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, OCFGPIMIXLOAD_1_0_MASK), REG_SCRIPT_END }; static const struct reg_script pcie_bus_init_script[] = { /* Setup Message Bus Idle Counter (SBIC) values */ REG_PCI_RMW8(R_QNC_PCIE_IOSFSBCTL, ~B_QNC_PCIE_IOSFSBCTL_SBIC_MASK, V_PCIE_ROOT_PORT_SBIC_VALUE), REG_PCI_READ8(R_QNC_PCIE_IOSFSBCTL), /* Set the IPF bit in MCR2 */ REG_PCI_OR32(R_QNC_PCIE_MPC2, B_QNC_PCIE_MPC2_IPF), REG_PCI_READ32(R_QNC_PCIE_MPC2), /* Set up the Posted and Non Posted Request sizes for PCIe */ REG_PCI_RMW32(R_QNC_PCIE_CCFG, ~B_QNC_PCIE_CCFG_UPSD, (B_QNC_PCIE_CCFG_UNRS | B_QNC_PCIE_CCFG_UPRS)), REG_PCI_READ32(R_QNC_PCIE_CCFG), REG_SCRIPT_END }; void pcie_init(void) {