/* Warm Reset a USB3 port */
static void xhci_reset_port_usb3(device_t dev, int port)
{
struct reg_script reset_port_usb3_script[] = {
/* Issue Warm Port Rest to the port */
REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port),
XHCI_USB3_PORTSC_WPR),
/* Wait up to 100ms for it to complete */
REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port),
XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC,
XHCI_RESET_TIMEOUT),
/* Clear change status bits, do not set PED */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port),
~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST),
REG_SCRIPT_END
};
reg_script_run_on_dev(dev, reset_port_usb3_script);
}
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000, GFX_TIMEOUT), /* Media Force-Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000, GFX_TIMEOUT), /* Workaround - X0:261954/A0:261955 */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1), /* * PowerMeter Weights */ /* SET1 */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307),
static const struct reg_script pch_pmc_misc_init_script[] = {
/* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */
REG_PCI_RMW16(GEN_PMCON_B,
~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK),
S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS |
DIS_SLP_X_STRCH_SUS_UP),
/* Enable SCI and clear SLP requests. */
REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
REG_SCRIPT_END
};
static const struct reg_script pmc_write1_to_clear_script[] = {
REG_PCI_OR32(GEN_PMCON_A, 0),
REG_PCI_OR32(GEN_PMCON_B, 0),
REG_PCI_OR32(GEN_PMCON_B, 0),
REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0),
REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0),
REG_SCRIPT_END
};
static void pch_pmc_add_mmio_resources(device_t dev)
{
struct resource *res;
/* Memory-mmapped I/O registers. */
res = new_resource(dev, PWRMBASE);
res->base = PCH_PWRM_BASE_ADDRESS;
res->size = PCH_PWRM_BASE_SIZE;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED | IORESOURCE_RESERVE;
}
#include <vendorcode/google/chromeos/chromeos.h>
#define GT_RETRY 1000
#define GT_CDCLK_337 0
#define GT_CDCLK_450 1
#define GT_CDCLK_540 2
#define GT_CDCLK_675 3
struct reg_script haswell_early_init_script[] = {
/* Enable Force Wake */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
/* Enable Counters */
REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016),
/* GFXPAUSE settings */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020),
/* ECO Settings */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000),
/* Enable DOP Clock Gating */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd),
/* Enable Unit Level Clock Gating */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000080),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001),
~0x00000070, 0x00000020),
REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_REE_DAC_CONTROL,
~0x00000002, 0x00000002),
REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_U1_POWER_STATE_DEF,
~0x00000000, 0x00040000),
REG_SCRIPT_END
};
const struct reg_script xhci_init_script[] = {
/* CommonXhciHcInit() */
/* BAR + 0x0c[31:16] = 0x0200 */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0x0000ffff, 0x02000000),
/* BAR + 0x0c[7:0] = 0x0a */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0xffffff00, 0x0000000a),
/* BAR + 0x8094[23,21,14]=111b */
REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8094, 0x00a04000),
/* BAR + 0x8110[20,11,8,2]=1100b */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8110, ~0x00000104, 0x00100800),
/* BAR + 0x8144[8,7,6]=111b */
REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8144, 0x000001c0),
/* BAR + 0x8154[21,13,3]=010b */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8154, ~0x00200008, 0x80002000),
/* BAR + 0x816c[19:0]=1110x100000000111100b */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x816c, 0xfff08000, 0x000e0030),
/* BAR + 0x8188[26,24]=11b */
REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8188, 0x05000000),
/* BAR + 0x8174=0x1000c0a*/
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8174, 0xfe000000, 0x01000c0a),
/* BAR + 0x854c[29]=0b */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x854c, ~0x20000000, 0),
/* BAR + 0x8178[12:0]=0b */
