static void
sn_end_irq(unsigned int irq)
{
#ifdef CONFIG_IA64_SGI_SN1
unsigned long long intpend_val, mask = 0x70L;
int subnode;
#endif
int nasid;
#ifdef CONFIG_IA64_SGI_SN2
unsigned long event_occurred;
#endif
irq = irq & 0xff;
#ifdef CONFIG_IA64_SGI_SN1
if (irq == SGI_UART_IRQ) {
nasid = smp_physical_node_id();
subnode = cpuid_to_subnode(smp_processor_id());
intpend_val = REMOTE_HUB_PI_L(nasid, subnode, PI_INT_PEND0);
if (intpend_val & mask) {
platform_send_ipi(smp_processor_id(), SGI_UART_IRQ, IA64_IPI_DM_INT, 0);
}
}
#endif
#ifdef CONFIG_IA64_SGI_SN2
if (irq == SGI_UART_VECTOR) {
nasid = smp_physical_node_id();
event_occurred = HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(nasid,SH_EVENT_OCCURRED) );
// If the UART bit is set here, we may have received an interrupt from the
// UART that the driver missed. To make sure, we IPI ourselves to force us
// to look again.
if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR, IA64_IPI_DM_INT, 0);
}
}
#endif
}
static void
sn_ack_irq(unsigned int irq)
{
#ifdef CONFIG_IA64_SGI_SN1
int bit = -1;
unsigned long long intpend_val;
int subnode;
#endif
#ifdef CONFIG_IA64_SGI_SN2
unsigned long event_occurred, mask = 0;
#endif
int nasid;
irq = irq & 0xff;
nasid = smp_physical_node_id();
#ifdef CONFIG_IA64_SGI_SN1
subnode = cpuid_to_subnode(smp_processor_id());
if (irq == SGI_UART_IRQ) {
intpend_val = REMOTE_HUB_PI_L(nasid, subnode, PI_INT_PEND0);
if (intpend_val & (1L<<GFX_INTR_A) ) {
bit = GFX_INTR_A;
REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
}
if ( intpend_val & (1L<<GFX_INTR_B) ) {
bit = GFX_INTR_B;
REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
}
if (intpend_val & (1L<<PG_MIG_INTR) ) {
bit = PG_MIG_INTR;
REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
}
if (intpend_val & (1L<<CC_PEND_A)) {
bit = CC_PEND_A;
REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
}
if (intpend_val & (1L<<CC_PEND_B)) {
bit = CC_PEND_B;
REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
}
return;
}
bit = irq_to_bit_pos(irq);
REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
#endif
#ifdef CONFIG_IA64_SGI_SN2
event_occurred = HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(nasid,SH_EVENT_OCCURRED) );
if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
mask |= (1 << SH_EVENT_OCCURRED_UART_INT_SHFT);
}
if (event_occurred & SH_EVENT_OCCURRED_IPI_INT_MASK) {
mask |= (1 << SH_EVENT_OCCURRED_IPI_INT_SHFT);
}
if (event_occurred & SH_EVENT_OCCURRED_II_INT0_MASK) {
mask |= (1 << SH_EVENT_OCCURRED_II_INT0_SHFT);
}
if (event_occurred & SH_EVENT_OCCURRED_II_INT1_MASK) {
mask |= (1 << SH_EVENT_OCCURRED_II_INT1_SHFT);
}
HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_EVENT_OCCURRED_ALIAS), mask );
#endif
}
void
hub_error_init(cnodeid_t cnode)
{
nasid_t nasid;
nasid = cnodeid_to_nasid(cnode);
hub_error_clear(nasid);
#ifdef ajm
if (cnode == 0) {
/*
* Allocate log for storing the node specific error info
*/
for (i = 0; i < numnodes; i++) {
kl_error_log[i] = kmem_zalloc_node(sizeof(sn0_error_log_t),
KM_NOSLEEP, i);
hub_err_count[i] = kmem_zalloc_node(sizeof(hub_errcnt_t),
VM_DIRECT | KM_NOSLEEP, i);
ASSERT_ALWAYS(kl_error_log[i] && hub_err_count[i]);
}
}
/*
* Assumption: There will be only one cpu who will initialize
* a hub. we need to setup the ii and each pi error interrupts.
* The SN1 hub (bedrock) has two PI, one for up to two processors.
*/
if (cpuid_to_cnodeid(smp_processor_id()) == cnode) {
int generic_intr_mask = PI_ERR_GENERIC; /* These interrupts are sent to only 1 CPU per NODE */
ASSERT_ALWAYS(kl_error_log[cnode]);
ASSERT_ALWAYS(hub_err_count[cnode]);
MD_ERR_LOG_INIT(kl_error_log[cnode]);
/* One for each CPU */
recover_error_init(RECOVER_ERROR_TABLE(cnode, 0));
recover_error_init(RECOVER_ERROR_TABLE(cnode, 1));
recover_error_init(RECOVER_ERROR_TABLE(cnode, 2));
recover_error_init(RECOVER_ERROR_TABLE(cnode, 3));
/*
* Setup error intr masks.
*/
for(sn=0; sn<NUM_SUBNODES; sn++) {
int cpuA_present = REMOTE_HUB_PI_L(nasid, sn, PI_CPU_ENABLE_A);
int cpuB_present = REMOTE_HUB_PI_L(nasid, sn, PI_CPU_ENABLE_B);
if (cpuA_present) {
if (cpuB_present) { /* A && B */
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A,
(PI_FATAL_ERR_CPU_B | PI_MISC_ERR_CPU_A|generic_intr_mask));
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B,
(PI_FATAL_ERR_CPU_A | PI_MISC_ERR_CPU_B));
} else { /* A && !B */
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A,
(PI_FATAL_ERR_CPU_A | PI_MISC_ERR_CPU_A|generic_intr_mask));
}
generic_intr_mask = 0;
} else {
if (cpuB_present) { /* !A && B */
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B,
(PI_FATAL_ERR_CPU_B | PI_MISC_ERR_CPU_B|generic_intr_mask));
generic_intr_mask = 0;
} else { /* !A && !B */
/* nothing to set up */
}
}
}
/*
* Turn off UNCAC_UNCORR interrupt in the masks. Anyone interested
* in these errors will peek at the int pend register to see if its
* set.
*/
for(sn=0; sn<NUM_SUBNODES; sn++) {
misc = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_INT_MASK_A);
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A, (misc & ~PI_ERR_UNCAC_UNCORR_A));
misc = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_INT_MASK_B);
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B, (misc & ~PI_ERR_UNCAC_UNCORR_B));
}
/*
* enable all error indicators to turn on, in case of errors.
*
* This is not good on single cpu node boards.
**** LOCAL_HUB_S(PI_SYSAD_ERRCHK_EN, PI_SYSAD_CHECK_ALL);
*/
for(sn=0; sn<NUM_SUBNODES; sn++) {
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS1_A_CLR, 0);
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS1_B_CLR, 0);
}
/* Set up stack for each present processor */
for(sn=0; sn<NUM_SUBNODES; sn++) {
if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_A)) {
SN0_ERROR_LOG(cnode)->el_spool_cur_addr[0] =
SN0_ERROR_LOG(cnode)->el_spool_last_addr[0] =
REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_A);
}
if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_B)) {
SN0_ERROR_LOG(cnode)->el_spool_cur_addr[1] =
SN0_ERROR_LOG(cnode)->el_spool_last_addr[1] =
REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
}
}
PI_SPOOL_SIZE_BYTES =
ERR_STACK_SIZE_BYTES(REMOTE_HUB_L(nasid, PI_ERR_STACK_SIZE));
#ifdef BRINGUP
/* BRINGUP: The following code looks like a check to make sure
the prom set up the error spool correctly for 2 processors. I
don't think it is needed. */
for(sn=0; sn<NUM_SUBNODES; sn++) {
if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_B)) {
__psunsigned_t addr_a = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_A);
__psunsigned_t addr_b = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
if ((addr_a & ~0xff) == (addr_b & ~0xff)) {
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STACK_ADDR_B,
addr_b + PI_SPOOL_SIZE_BYTES);
SN0_ERROR_LOG(cnode)->el_spool_cur_addr[1] =
SN0_ERROR_LOG(cnode)->el_spool_last_addr[1] =
REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
}
}
}
#endif /* BRINGUP */
/* programming our own hub. Enable error_int_pend intr.
* If both present, CPU A takes CPU b's error interrupts and any
* generic ones. CPU B takes CPU A error ints.
*/
if (cause_intr_connect (SRB_ERR_IDX,
(intr_func_t)(hubpi_eint_handler),
SR_ALL_MASK|SR_IE)) {
cmn_err(ERR_WARN,
"hub_error_init: cause_intr_connect failed on %d", cnode);
}
}
else {
/* programming remote hub. The only valid reason that this
* is called will be on headless hubs. No interrupts
*/
for(sn=0; sn<NUM_SUBNODES; sn++) {
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A, 0); /* not necessary */
REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B, 0); /* not necessary */
}
}
#endif /* ajm */
/*
* Now setup the hub ii and ni error interrupt handler.
*/
hubii_eint_init(cnode);
hubni_eint_init(cnode);
#ifdef ajm
/*** XXX FIXME XXX resolve the following***/
/* INT_PEND1 bits set up for one hub only:
* SHUTDOWN_INTR
* MD_COR_ERR_INTR
* COR_ERR_INTR_A and COR_ERR_INTR_B should be sent to the
* appropriate CPU only.
*/
if (cnode == 0) {
error_consistency_check.eps_state = 0;
error_consistency_check.eps_cpuid = -1;
spinlock_init(&error_consistency_check.eps_lock, "error_dump_lock");
}
#endif
nodepda->huberror_ticks = HUB_ERROR_PERIOD;
return;
}
