int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
uint32_t data_size)
{
if (hash_alg != VB2_HASH_SHA256) {
printk(BIOS_INFO, "RK3288 doesn't support hash_alg %d!\n",
hash_alg);
return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
}
write32(&crypto->ctrl, RK_SETBITS(1 << 6)); /* Assert HASH_FLUSH */
udelay(1); /* for 10+ cycles to */
write32(&crypto->ctrl, RK_CLRBITS(1 << 6)); /* clear out old hash */
/* Enable DMA byte swapping for little-endian bus (Byteswap_??FIFO) */
write32(&crypto->conf, 1 << 5 | 1 << 4 | 1 << 3);
write32(&crypto->intena, HRDMA_ERR | HRDMA_DONE); /* enable interrupt */
write32(&crypto->hash_msg_len, data_size); /* program total size */
write32(&crypto->hash_ctrl, 1 << 3 | 0x2); /* swap DOUT, SHA256 */
printk(BIOS_DEBUG, "Initialized RK3288 HW crypto for %u byte SHA256\n",
data_size);
return VB2_SUCCESS;
}
static void configure_sdmmc(void)
{
write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
/* use sdmmc0 io, disable JTAG function */
write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
sdmmc_power_on();
gpio_input(GPIO(7, A, 5)); /* SDMMC_DET_L */
}
static void configure_sdmmc(void)
{
writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
/* use sdmmc0 io, disable JTAG function */
writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
gpio_input(GPIO(7, A, 5)); /* SD_DET */
}
static void configure_sdmmc(void)
{
write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
/* use sdmmc0 io, disable JTAG function */
write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
/* Note: these power rail definitions are copied in romstage.c */
rk808_configure_ldo(4, 3300); /* VCCIO_SD */
rk808_configure_ldo(5, 3300); /* VCC33_SD */
gpio_input(GPIO(7, A, 5)); /* SD_DET */
}
static void configure_sdmmc(void)
{
writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
/* use sdmmc0 io, disable JTAG function */
writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
switch (board_id()) {
case 0:
rk808_configure_ldo(PMIC_BUS, 8, 3300); /* VCCIO_SD */
gpio_output(GPIO(7, C, 5), 1); /* SD_EN */
break;
default:
rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
break;
}
gpio_input(GPIO(7, A, 5)); /* SD_DET */
}
static void configure_sdmmc(void)
{
write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
/* use sdmmc0 io, disable JTAG function */
write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
/* Note: these power rail definitions are copied in romstage.c */
switch (board_id()) {
case 0:
rk808_configure_ldo(8, 3300); /* VCCIO_SD */
gpio_output(GPIO(7, C, 5), 1); /* SD_EN */
break;
default:
rk808_configure_ldo(4, 3300); /* VCCIO_SD */
rk808_configure_ldo(5, 3300); /* VCC33_SD */
break;
}
gpio_input(GPIO(7, A, 5)); /* SD_DET */
}
void rk_display_init(device_t dev, u32 lcdbase,
unsigned long fb_size)
{
struct edid edid;
uint32_t val;
struct soc_rockchip_rk3288_config *conf = dev->chip_info;
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase));
memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
dcache_clean_invalidate_by_mva((void *)lower, upper - lower);
mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);
switch (conf->vop_mode) {
case VOP_MODE_NONE:
return;
case VOP_MODE_AUTO_DETECT:
/* try EDP first, then HDMI */
case VOP_MODE_EDP:
printk(BIOS_DEBUG, "Attempting to setup EDP display.\n");
rkclk_configure_edp();
rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz);
/* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
write32(&rk3288_grf->soc_con12, RK_SETBITS(1 << 4));
/* select epd signal from vop0 or vop1 */
val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) :
RK_CLRBITS(1 << 5);
write32(&rk3288_grf->soc_con6, val);
rk_edp_init();
if (rk_edp_get_edid(&edid) == 0) {
detected_mode = VOP_MODE_EDP;
break;
} else {
printk(BIOS_WARNING, "Cannot get EDID from EDP.\n");
if (conf->vop_mode == VOP_MODE_EDP)
return;
}
/* fall thru */
case VOP_MODE_HDMI:
printk(BIOS_DEBUG, "Attempting to setup HDMI display.\n");
rkclk_configure_hdmi();
rkclk_configure_vop_aclk(conf->vop_id, 384 * MHz);
rk_hdmi_init(conf->vop_id);
if (rk_hdmi_get_edid(&edid) == 0) {
detected_mode = VOP_MODE_HDMI;
break;
} else {
printk(BIOS_WARNING, "Cannot get EDID from HDMI.\n");
if (conf->vop_mode == VOP_MODE_HDMI)
return;
}
/* fall thru */
default:
printk(BIOS_WARNING, "Cannot read any edid info, aborting.\n");
return;
}
if (rkclk_configure_vop_dclk(conf->vop_id, edid.mode.pixel_clock * KHz)) {
printk(BIOS_WARNING, "config vop err\n");
return;
}
edid_set_framebuffer_bits_per_pixel(&edid,
conf->framebuffer_bits_per_pixel, 0);
rkvop_mode_set(conf->vop_id, &edid, detected_mode);
rkvop_prepare(conf->vop_id, &edid);
rkvop_enable(conf->vop_id, lcdbase);
switch (detected_mode) {
case VOP_MODE_HDMI:
if (rk_hdmi_enable(&edid)) {
printk(BIOS_WARNING, "hdmi enable err\n");
return;
}
/*
* HACK: if we do remove this delay, HDMI TV may not show
* anythings. So we make an delay here, ensure TV have
* enough time to respond.
*/
mdelay(2000);
break;
case VOP_MODE_EDP:
default:
if (rk_edp_prepare()) {
printk(BIOS_WARNING, "edp prepare err\n");
return;
}
if (rk_edp_enable()) {
printk(BIOS_WARNING, "edp enable err\n");
return;
}
mainboard_power_on_backlight();
break;
}
set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase);
}