void Mapper202_init(void)
{
ROM_BANK16(0x8000,0);
ROM_BANK16(0xc000,0);
VROM_BANK8(0);
SetWriteHandler(0x8000,0xFFFF,Mapper202_write);
}
void Mapper230_init(void)
{
ROM_BANK16(0x8000,0);
ROM_BANK16(0xc000,7);
SetWriteHandler(0x8000, 0xffff, Mapper230_write);
MapperReset = Mapper230_Reset;
rom_sw = 1;
}
static DECLFW(Mapper202_write)
{
int tmp=(A>>1)&0x7;
MIRROR_SET(A&1);
ROM_BANK16(0x8000,tmp);
ROM_BANK16(0xc000,tmp+(((tmp&0x6)==0x6)?1:0));
VROM_BANK8(tmp);
}
void Mapper230_Reset(void)
{
rom_sw ^= 1; //1 - rom_sw;
if( rom_sw ) {
ROM_BANK16(0x8000,0);
ROM_BANK16(0xc000,7);
} else {
ROM_BANK16(0x8000,8);
ROM_BANK16(0xc000,39);
}
MIRROR_SET2(1);
}
static DECLFW(Mapper230_write)
{
if( rom_sw ) {
ROM_BANK16( 0x8000, V&0x07 );
} else {
if( V & 0x20 ) {
ROM_BANK16( 0x8000, (V&0x1F)+8 );
ROM_BANK16( 0xc000, (V&0x1F)+8 );
} else {
ROM_BANK32( ((V&0x1E) >> 1) + 4 );
}
MIRROR_SET2( ((V & 0x40) >> 6) );
}
}
static DECLFW(Mapper16_write)
{
A&=0xF;
if(A<=0x7)
VROM_BANK1(A<<10,V);
else if(A==0x8)
ROM_BANK16(0x8000,V);
else switch(A) {
case 0x9: switch(V&3) {
case 0x00:MIRROR_SET2(1);break;
case 0x01:MIRROR_SET2(0);break;
case 0x02:onemir(0);break;
case 0x03:onemir(1);break;
}
break;
case 0xA:X6502_IRQEnd(FCEU_IQEXT);
IRQa=V&1;
IRQCount=IRQLatch;
break;
case 0xB:IRQLatch&=0xFF00; IRQLatch|=V;
break;
case 0xC:IRQLatch&=0xFF; IRQLatch|=V<<8;
break;
case 0xD: break;/* Serial EEPROM control port */
}
}
static DECLFW(Mapper24_write)
{
if(swaparoo)
A=(A&0xFFFC)|((A>>1)&1)|((A<<1)&2);
if(A>=0x9000 && A<=0xb002)
{
VRC6SW(A,V);
return;
}
A&=0xF003;
// if(A>=0xF000) printf("%d, %d, $%04x:$%02x\n",scanline,timestamp,A,V);
switch(A&0xF003)
{
case 0x8000:ROM_BANK16(0x8000,V);break;
case 0xB003:
switch(V&0xF)
{
case 0x0:MIRROR_SET2(1);break;
case 0x4:MIRROR_SET2(0);break;
case 0x8:onemir(0);break;
case 0xC:onemir(1);break;
}
break;
case 0xC000:ROM_BANK8(0xC000,V);break;
case 0xD000:VROM_BANK1(0x0000,V);break;
case 0xD001:VROM_BANK1(0x0400,V);break;
case 0xD002:VROM_BANK1(0x0800,V);break;
case 0xD003:VROM_BANK1(0x0c00,V);break;
case 0xE000:VROM_BANK1(0x1000,V);break;
case 0xE001:VROM_BANK1(0x1400,V);break;
case 0xE002:VROM_BANK1(0x1800,V);break;
case 0xE003:VROM_BANK1(0x1c00,V);break;
case 0xF000:IRQLatch=V;
//acount=0;
break;
case 0xF001:IRQa=V&2;
vrctemp=V&1;
if(V&2)
{
IRQCount=IRQLatch;
acount=0;
}
X6502_IRQEnd(FCEU_IQEXT);
break;
case 0xf002:IRQa=vrctemp;
X6502_IRQEnd(FCEU_IQEXT);break;
case 0xF003:break;
}
}
static DECLFW(Mapper73_write)
{
//printf("$%04x:$%02x\n",A,V);
switch(A&0xF000)
{
case 0x8000:
IRQr&=0xFFF0;IRQr|=(V&0xF);
break;
case 0x9000:
IRQr&=0xFF0F;IRQr|=(V&0xF)<<4;
break;
case 0xa000:
IRQr&=0xF0FF;IRQr|=(V&0xF)<<8;
break;
case 0xb000:
IRQr&=0x0FFF;IRQr|=(V&0xF)<<12;
break;
case 0xc000:
IRQm=V&4;
IRQx=V&1;
IRQa=V&2;
if(IRQa)
{
if(IRQm)
{
IRQCount&=0xFFFF;
IRQCount|=(IRQr&0xFF);
}
else
{
IRQCount=IRQr;
}
}
X6502_IRQEnd(FCEU_IQEXT);
break;
case 0xd000:
X6502_IRQEnd(FCEU_IQEXT);
IRQa=IRQx;
break;
case 0xf000:ROM_BANK16(0x8000,V);break;
}
}
void Mapper32_init(void)
{
ROM_BANK16(0x8000,0);
ROM_BANK16(0xc000,~0);
SetWriteHandler(0x8000,0xffff,Mapper32_write);
}
static void PRGO(void)
{
uint32 base=(mapbyte1[0]&1)<<4;
ROM_BANK16(0x8000,(mapbyte2[0]&0xF)|base);
ROM_BANK16(0xC000,base|0xF);
}
static void m83prg(void)
{
ROM_BANK16(0x8000,(mapbyte1[0]&0x3F));
ROM_BANK16(0xC000,(mapbyte1[0]&0x30)|0xF);
}
