int wolfSSL_TI_CCMInit(void)
{
if (ccm_init)
return true;
ccm_init = true;
#ifndef TI_DUMMY_BUILD
SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_480), 120000000);
if (!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_CCM0))
return false;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_CCM0);
WAIT(ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_CCM0));
ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_CCM0);
WAIT(ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_CCM0));
#ifndef SINGLE_THREADED
if (wc_InitMutex(&TI_CCM_Mutex))
return false;
#endif
#endif /* !TI_DUMMY_BUILD */
return true;
}
void TwoWire::forceStop(void) {
//force a stop to release the bus
ROM_GPIOPinTypeGPIOOutput(g_uli2cBase[i2cModule],
g_uli2cSCLPins[i2cModule] | g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule], g_uli2cSDAPins[i2cModule], 0);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule],
g_uli2cSCLPins[i2cModule], g_uli2cSCLPins[i2cModule]);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule],
g_uli2cSDAPins[i2cModule], g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinTypeI2C(g_uli2cBase[i2cModule], g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinTypeI2CSCL(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]);
//reset I2C controller
//without resetting the I2C controller, the I2C module will
//bring the bus back to it's erroneous state
ROM_SysCtlPeripheralReset(g_uli2cPeriph[i2cModule]);
while(!ROM_SysCtlPeripheralReady(g_uli2cPeriph[i2cModule]));
ROM_I2CMasterInitExpClk(MASTER_BASE, F_CPU, speedMode);//Bus speed
if(speedMode==I2C_SPEED_FASTMODE_PLUS)//Force 1Mhz
{
uint32_t ui32TPR = ((F_CPU + (2 * 10 * 1000000l) - 1) / (2 * 10 * 1000000l)) - 1;
HWREG(MASTER_BASE + I2C_O_MTPR) = ui32TPR;
}
}
void TwoWire::forceStop(void) {
//force a stop to release the bus
ROM_GPIOPinTypeGPIOOutput(g_uli2cBase[i2cModule],
g_uli2cSCLPins[i2cModule] | g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule], g_uli2cSDAPins[i2cModule], 0);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule],
g_uli2cSCLPins[i2cModule], g_uli2cSCLPins[i2cModule]);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule],
g_uli2cSDAPins[i2cModule], g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinTypeI2C(g_uli2cBase[i2cModule], g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinTypeI2CSCL(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]);
//reset I2C controller
//without resetting the I2C controller, the I2C module will
//bring the bus back to it's erroneous state
ROM_SysCtlPeripheralReset(g_uli2cPeriph[i2cModule]);
while(!ROM_SysCtlPeripheralReady(g_uli2cPeriph[i2cModule]));
ROM_I2CMasterInitExpClk(MASTER_BASE, F_CPU, false);
}
//*****************************************************************************
//
// Initialize the AES and CCM modules.
//
//*****************************************************************************
bool
AESInit(void)
{
uint32_t ui32Loop;
//
// Check that the CCM peripheral is present.
//
if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_CCM0))
{
UARTprintf("No CCM peripheral found!\n");
//
// Return failure.
//
return(false);
}
//
// The hardware is available, enable it.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_CCM0);
//
// Wait for the peripheral to be ready.
//
ui32Loop = 0;
while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_CCM0))
{
//
// Increment our poll counter.
//
ui32Loop++;
if(ui32Loop > CCM_LOOP_TIMEOUT)
{
//
// Timed out, notify and spin.
//
UARTprintf("Time out on CCM ready after enable.\n");
//
// Return failure.
//
return(false);
}
}
//
// Reset the peripheral to ensure we are starting from a known condition.
//
ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_CCM0);
//
// Wait for the peripheral to be ready again.
//
ui32Loop = 0;
while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_CCM0))
{
//
// Increment our poll counter.
//
ui32Loop++;
if(ui32Loop > CCM_LOOP_TIMEOUT)
{
//
// Timed out, spin.
//
UARTprintf("Time out on CCM ready after reset.\n");
//
// Return failure.
//
return(false);
}
}
//
// Return initialization success.
//
return(true);
}
//*****************************************************************************
//
// Process data to produce a CRC-32 checksum.
//
//*****************************************************************************
uint32_t
CRC32DataProcess(uint32_t *pui32Data, uint32_t ui32Length, uint32_t ui32Seed,
bool bUseDMA)
{
uint32_t ui32Result;
//
// Perform a soft reset.
//
ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_CCM0);
while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_CCM0))
{
}
//
// Configure the CRC engine.
//
ROM_CRCConfigSet(CCM0_BASE, (CRC_CFG_INIT_SEED | CRC_CFG_TYPE_P4C11DB7 |
CRC_CFG_SIZE_32BIT));
//
// Write the seed.
//
ROM_CRCSeedSet(CCM0_BASE, ui32Seed);
//
// Generate CRC using uDMA to copy data.
//
if(bUseDMA)
{
//
// Setup the DMA module to copy data in.
//
ROM_uDMAChannelAssign(UDMA_CH30_SW);
ROM_uDMAChannelAttributeDisable(UDMA_CH30_SW,
UDMA_ATTR_ALTSELECT |
UDMA_ATTR_USEBURST |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
ROM_uDMAChannelControlSet(UDMA_CH30_SW | UDMA_PRI_SELECT,
UDMA_SIZE_32 | UDMA_SRC_INC_32 |
UDMA_DST_INC_NONE | UDMA_ARB_1 |
UDMA_DST_PROT_PRIV);
ROM_uDMAChannelTransferSet(UDMA_CH30_SW | UDMA_PRI_SELECT,
UDMA_MODE_AUTO, (void *)g_pui32RandomData,
(void *)(CCM0_BASE + CCM_O_CRCDIN),
ui32Length);
ROM_uDMAChannelEnable(UDMA_CH30_SW);
UARTprintf(" Data in DMA request enabled.\n");
//
// Start the uDMA.
//
ROM_uDMAChannelRequest(UDMA_CH30_SW | UDMA_PRI_SELECT);
//
// Wait for the transfer to finish.
//
while(ROM_uDMAChannelIsEnabled(UDMA_CH30_SW))
{
}
//
// Read the result.
//
ui32Result = ROM_CRCResultRead(CCM0_BASE, false);
}
//
// Generate CRC using CPU to copy data.
//
else
{
ui32Result = ROM_CRCDataProcess(CCM0_BASE, g_pui32RandomData,
ui32Length, false);
}
return(ui32Result);
}
