/* execute instructions on this CPU until icount expires */
static CPU_EXECUTE( m6809 ) /* NS 970908 */
{
m68_state_t *m68_state = get_safe_token(device);
m68_state->icount -= m68_state->extra_cycles;
m68_state->extra_cycles = 0;
check_irq_lines(m68_state);
if (m68_state->int_state & (M6809_CWAI | M6809_SYNC))
{
debugger_instruction_hook(device, PCD);
m68_state->icount = 0;
}
else
{
do
{
pPPC = pPC;
debugger_instruction_hook(device, PCD);
m68_state->ireg = ROP(PCD);
PC++;
(*m6809_main[m68_state->ireg])(m68_state);
m68_state->icount -= cycles1[m68_state->ireg];
} while( m68_state->icount > 0 );
m68_state->icount -= m68_state->extra_cycles;
m68_state->extra_cycles = 0;
}
}
/* execute instructions on this CPU until icount expires */
static int konami_execute(int cycles)
{
konami_ICount = cycles - konami.extra_cycles;
konami.extra_cycles = 0;
if( konami.int_state & (KONAMI_CWAI | KONAMI_SYNC) )
{
konami_ICount = 0;
}
else
{
do
{
pPPC = pPC;
CALL_MAME_DEBUG;
konami.ireg = ROP(PCD);
PC++;
(*konami_main[konami.ireg])();
konami_ICount -= cycles1[konami.ireg];
} while( konami_ICount > 0 );
konami_ICount -= konami.extra_cycles;
konami.extra_cycles = 0;
}
return cycles - konami_ICount;
}
/*******************************************************************************************
NOTE: All registers are accessed directly, instead of using the SFR_R() function for speed
Direct register access is availabe from the R_(register name) macros.. ex: R_ACC for the ACC
with the exception of the PC
********************************************************************************************/
//ACALL code addr /* 1: aaa1 0001 */
INLINE void acall(void)
{
UINT8 op = ROP(PC-1); //Grab the opcode for ACALL
UINT8 addr = ROP_ARG(PC++); //Grab code address byte
PUSH_PC //Save PC to the stack
//Thanks Gerrit for help with this! :)
PC = (PC & 0xf800) | ((op & 0xe0) << 3) | addr;
}
//ADD A, #data /* 1: 0010 0100 */
INLINE void add_a_byte(void)
{
UINT8 data = ROP_ARG(PC++); //Grab data
UINT8 result = R_ACC + data; //Add data to accumulator
DO_ADD_FLAGS(R_ACC,data,0) //Set Flags
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
}
//ADD A, data addr /* 1: 0010 0101 */
INLINE void add_a_mem(void)
{
UINT8 addr = ROP_ARG(PC++); //Grab data address
UINT8 data = IRAM_R(addr); //Grab data from data address
UINT8 result = R_ACC + data; //Add data to accumulator
DO_ADD_FLAGS(R_ACC,data,0); //Set Flags
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
}
//ADD A, @R0/@R1 /* 1: 0010 011i */
INLINE void add_a_ir(int r)
{
UINT8 data = IRAM_IR(R_R(r)); //Grab data from memory pointed to by R0 or R1
UINT8 result = R_ACC + data; //Add data to accumulator
DO_ADD_FLAGS(R_ACC,data,0); //Set Flags
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
}
//ADD A, R0 to R7 /* 1: 0010 1rrr */
INLINE void add_a_r(int r)
{
UINT8 data = R_R(r); //Grab data from R0 - R7
UINT8 result = R_ACC + data; //Add data to accumulator
DO_ADD_FLAGS(R_ACC,data,0); //Set Flags
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
}
//ADDC A, #data /* 1: 0011 0100 */
INLINE void addc_a_byte(void)
{
UINT8 data = ROP_ARG(PC++); //Grab data
UINT8 result = R_ACC + data + GET_CY; //Add data + carry flag to accumulator
DO_ADD_FLAGS(R_ACC,data,GET_CY); //Set Flags
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
}
//ADDC A, data addr /* 1: 0011 0101 */
INLINE void addc_a_mem(void)
{
UINT8 addr = ROP_ARG(PC++); //Grab data address
UINT8 data = IRAM_R(addr); //Grab data from data address
UINT8 result = R_ACC + data + GET_CY; //Add data + carry flag to accumulator
DO_ADD_FLAGS(R_ACC,data,GET_CY); //Set Flags
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
}
//ADDC A, @R0/@R1 /* 1: 0011 011i */
INLINE void addc_a_ir(int r)
{
UINT8 data = IRAM_IR(R_R(r)); //Grab data from memory pointed to by R0 or R1
UINT8 result = R_ACC + data + GET_CY; //Add data + carry flag to accumulator
DO_ADD_FLAGS(R_ACC,data,GET_CY); //Set Flags
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
}
//ADDC A, R0 to R7 /* 1: 0011 1rrr */
INLINE void addc_a_r(int r)
{
UINT8 data = R_R(r); //Grab data from R0 - R7
UINT8 result = R_ACC + data + GET_CY; //Add data + carry flag to accumulator
DO_ADD_FLAGS(R_ACC,data,GET_CY); //Set Flags
SFR_W(ACC,result); //Store 8 bit result of addtion in ACC
}
//AJMP code addr /* 1: aaa0 0001 */
INLINE void ajmp(void)
{
UINT8 op = ROP(PC-1); //Grab the opcode for AJMP
UINT8 addr = ROP_ARG(PC++); //Grab code address byte
//Thanks Gerrit for help with this! :)
PC = (PC & 0xf800) | ((op & 0xe0) << 3) | addr;
}
/* execute instructions on this CPU until icount expires */
static CPU_EXECUTE( konami )
{
konami_state *cpustate = get_safe_token(device);
check_irq_lines(cpustate);
if( cpustate->int_state & (KONAMI_CWAI | KONAMI_SYNC) )
{
cpustate->icount = 0;
}
else
{
do
{
UINT8 ireg;
pPPC = pPC;
debugger_instruction_hook(device, PCD);
cpustate->ireg = ireg = ROP(cpustate, PCD);
PC++;
(*konami_main[ireg])(cpustate);
cpustate->icount -= cycles1[ireg];
} while( cpustate->icount > 0 );
}
}
void m6809_base_device::execute_run()
{
m_icount -= m_extra_cycles;
m_extra_cycles = 0;
check_irq_lines();
if (m_int_state & (M6809_CWAI | M6809_SYNC))
{
debugger_instruction_hook(this, PCD);
m_icount = 0;
}
else
{
do
{
pPPC = pPC;
debugger_instruction_hook(this, PCD);
m_ireg = ROP(PCD);
PC++;
(this->*m_opcode[m_ireg])();
m_icount -= m_cycles1[m_ireg];
} while( m_icount > 0 );
m_icount -= m_extra_cycles;
m_extra_cycles = 0;
}
}
/*******************************************************************************************
NOTE: All registers are accessed directly, instead of using the SFR_R() function for speed
Direct register access is availabe from the R_(register name) macros.. ex: R_ACC for the ACC
with the exception of the PC
********************************************************************************************/
//ACALL code addr /* 1: aaa1 0001 */
INLINE void acall(void)
{
UINT8 op = ROP(PC-1); //Grab the opcode for ACALL
UINT8 addr = ROP_ARG(PC++); //Grab code address byte
PUSH_PC //Save PC to the stack
//Thanks Gerrit for help with this! :)
PC = (PC & 0xf800) | ((op & 0xe0) << 3) | addr;
}
/* execute instructions on this CPU until icount expires */
int konamiRun(int cycles)
{
#if defined FBA_DEBUG
if (!DebugCPU_KonamiInitted) bprintf(PRINT_ERROR, _T("konamiRun called without init\n"));
#endif
konami_ICount = cycles - konami.extra_cycles;
nCyclesToDo = konami_ICount;
konami.extra_cycles = 0;
if( konami.int_state & (KONAMI_CWAI | KONAMI_SYNC) )
{
konami_ICount = 0;
}
else
{
do
{
pPPC = pPC;
konami.ireg = ROP(PCD);
PC++;
(*konami_main[konami.ireg])();
konami_ICount -= cycles1[konami.ireg];
} while( konami_ICount > 0 );
konami_ICount -= konami.extra_cycles;
konami.extra_cycles = 0;
}
konami.nTotalCycles += cycles - konami_ICount;
return cycles - konami_ICount;
}
/* execute instructions on this CPU until icount expires */
static int hd6309_execute(int cycles) /* NS 970908 */
{
hd6309_ICount = cycles - hd6309.extra_cycles;
hd6309.extra_cycles = 0;
if (hd6309.int_state & (HD6309_CWAI | HD6309_SYNC))
{
CALL_MAME_DEBUG;
hd6309_ICount = 0;
}
else
{
do
{
pPPC = pPC;
CALL_MAME_DEBUG;
hd6309.ireg = ROP(PCD);
PC++;
#ifdef BIG_SWITCH
switch( hd6309.ireg )
{
case 0x00: neg_di(); break;
case 0x01: oim_di(); break;
case 0x02: aim_di(); break;
case 0x03: com_di(); break;
case 0x04: lsr_di(); break;
case 0x05: eim_di(); break;
case 0x06: ror_di(); break;
case 0x07: asr_di(); break;
case 0x08: asl_di(); break;
case 0x09: rol_di(); break;
case 0x0a: dec_di(); break;
case 0x0b: tim_di(); break;
case 0x0c: inc_di(); break;
case 0x0d: tst_di(); break;
case 0x0e: jmp_di(); break;
case 0x0f: clr_di(); break;
case 0x10: pref10(); break;
case 0x11: pref11(); break;
case 0x12: nop(); break;
case 0x13: sync(); break;
case 0x14: sexw(); break;
case 0x15: IIError(); break;
case 0x16: lbra(); break;
case 0x17: lbsr(); break;
case 0x18: IIError(); break;
case 0x19: daa(); break;
case 0x1a: orcc(); break;
case 0x1b: IIError(); break;
case 0x1c: andcc(); break;
case 0x1d: sex(); break;
case 0x1e: exg(); break;
case 0x1f: tfr(); break;
case 0x20: bra(); break;
case 0x21: brn(); break;
case 0x22: bhi(); break;
case 0x23: bls(); break;
case 0x24: bcc(); break;
case 0x25: bcs(); break;
case 0x26: bne(); break;
case 0x27: beq(); break;
case 0x28: bvc(); break;
case 0x29: bvs(); break;
case 0x2a: bpl(); break;
case 0x2b: bmi(); break;
case 0x2c: bge(); break;
case 0x2d: blt(); break;
case 0x2e: bgt(); break;
case 0x2f: ble(); break;
case 0x30: leax(); break;
case 0x31: leay(); break;
case 0x32: leas(); break;
case 0x33: leau(); break;
case 0x34: pshs(); break;
case 0x35: puls(); break;
case 0x36: pshu(); break;
case 0x37: pulu(); break;
case 0x38: IIError(); break;
case 0x39: rts(); break;
case 0x3a: abx(); break;
case 0x3b: rti(); break;
case 0x3c: cwai(); break;
case 0x3d: mul(); break;
case 0x3e: IIError(); break;
case 0x3f: swi(); break;
case 0x40: nega(); break;
case 0x41: IIError(); break;
case 0x42: IIError(); break;
case 0x43: coma(); break;
case 0x44: lsra(); break;
case 0x45: IIError(); break;
case 0x46: rora(); break;
case 0x47: asra(); break;
case 0x48: asla(); break;
case 0x49: rola(); break;
case 0x4a: deca(); break;
case 0x4b: IIError(); break;
case 0x4c: inca(); break;
case 0x4d: tsta(); break;
case 0x4e: IIError(); break;
case 0x4f: clra(); break;
case 0x50: negb(); break;
case 0x51: IIError(); break;
case 0x52: IIError(); break;
case 0x53: comb(); break;
case 0x54: lsrb(); break;
case 0x55: IIError(); break;
case 0x56: rorb(); break;
case 0x57: asrb(); break;
case 0x58: aslb(); break;
case 0x59: rolb(); break;
case 0x5a: decb(); break;
case 0x5b: IIError(); break;
case 0x5c: incb(); break;
case 0x5d: tstb(); break;
case 0x5e: IIError(); break;
case 0x5f: clrb(); break;
case 0x60: neg_ix(); break;
case 0x61: oim_ix(); break;
case 0x62: aim_ix(); break;
case 0x63: com_ix(); break;
case 0x64: lsr_ix(); break;
case 0x65: eim_ix(); break;
case 0x66: ror_ix(); break;
case 0x67: asr_ix(); break;
case 0x68: asl_ix(); break;
case 0x69: rol_ix(); break;
case 0x6a: dec_ix(); break;
case 0x6b: tim_ix(); break;
case 0x6c: inc_ix(); break;
case 0x6d: tst_ix(); break;
case 0x6e: jmp_ix(); break;
case 0x6f: clr_ix(); break;
case 0x70: neg_ex(); break;
case 0x71: oim_ex(); break;
case 0x72: aim_ex(); break;
case 0x73: com_ex(); break;
case 0x74: lsr_ex(); break;
case 0x75: eim_ex(); break;
case 0x76: ror_ex(); break;
case 0x77: asr_ex(); break;
case 0x78: asl_ex(); break;
case 0x79: rol_ex(); break;
case 0x7a: dec_ex(); break;
case 0x7b: tim_ex(); break;
case 0x7c: inc_ex(); break;
case 0x7d: tst_ex(); break;
case 0x7e: jmp_ex(); break;
case 0x7f: clr_ex(); break;
case 0x80: suba_im(); break;
case 0x81: cmpa_im(); break;
case 0x82: sbca_im(); break;
case 0x83: subd_im(); break;
case 0x84: anda_im(); break;
case 0x85: bita_im(); break;
case 0x86: lda_im(); break;
case 0x87: IIError(); break;
case 0x88: eora_im(); break;
case 0x89: adca_im(); break;
case 0x8a: ora_im(); break;
case 0x8b: adda_im(); break;
case 0x8c: cmpx_im(); break;
case 0x8d: bsr(); break;
case 0x8e: ldx_im(); break;
case 0x8f: IIError(); break;
case 0x90: suba_di(); break;
case 0x91: cmpa_di(); break;
case 0x92: sbca_di(); break;
case 0x93: subd_di(); break;
case 0x94: anda_di(); break;
case 0x95: bita_di(); break;
case 0x96: lda_di(); break;
case 0x97: sta_di(); break;
case 0x98: eora_di(); break;
case 0x99: adca_di(); break;
case 0x9a: ora_di(); break;
case 0x9b: adda_di(); break;
case 0x9c: cmpx_di(); break;
case 0x9d: jsr_di(); break;
case 0x9e: ldx_di(); break;
case 0x9f: stx_di(); break;
case 0xa0: suba_ix(); break;
case 0xa1: cmpa_ix(); break;
case 0xa2: sbca_ix(); break;
case 0xa3: subd_ix(); break;
case 0xa4: anda_ix(); break;
case 0xa5: bita_ix(); break;
case 0xa6: lda_ix(); break;
case 0xa7: sta_ix(); break;
case 0xa8: eora_ix(); break;
case 0xa9: adca_ix(); break;
case 0xaa: ora_ix(); break;
case 0xab: adda_ix(); break;
case 0xac: cmpx_ix(); break;
case 0xad: jsr_ix(); break;
case 0xae: ldx_ix(); break;
case 0xaf: stx_ix(); break;
case 0xb0: suba_ex(); break;
case 0xb1: cmpa_ex(); break;
case 0xb2: sbca_ex(); break;
case 0xb3: subd_ex(); break;
case 0xb4: anda_ex(); break;
case 0xb5: bita_ex(); break;
case 0xb6: lda_ex(); break;
case 0xb7: sta_ex(); break;
case 0xb8: eora_ex(); break;
case 0xb9: adca_ex(); break;
case 0xba: ora_ex(); break;
case 0xbb: adda_ex(); break;
case 0xbc: cmpx_ex(); break;
case 0xbd: jsr_ex(); break;
case 0xbe: ldx_ex(); break;
case 0xbf: stx_ex(); break;
case 0xc0: subb_im(); break;
case 0xc1: cmpb_im(); break;
case 0xc2: sbcb_im(); break;
case 0xc3: addd_im(); break;
case 0xc4: andb_im(); break;
case 0xc5: bitb_im(); break;
case 0xc6: ldb_im(); break;
case 0xc7: IIError(); break;
case 0xc8: eorb_im(); break;
case 0xc9: adcb_im(); break;
case 0xca: orb_im(); break;
case 0xcb: addb_im(); break;
case 0xcc: ldd_im(); break;
case 0xcd: ldq_im(); break; /* in m6809 was std_im */
case 0xce: ldu_im(); break;
case 0xcf: IIError(); break;
case 0xd0: subb_di(); break;
case 0xd1: cmpb_di(); break;
case 0xd2: sbcb_di(); break;
case 0xd3: addd_di(); break;
case 0xd4: andb_di(); break;
case 0xd5: bitb_di(); break;
case 0xd6: ldb_di(); break;
case 0xd7: stb_di(); break;
case 0xd8: eorb_di(); break;
case 0xd9: adcb_di(); break;
case 0xda: orb_di(); break;
case 0xdb: addb_di(); break;
case 0xdc: ldd_di(); break;
case 0xdd: std_di(); break;
case 0xde: ldu_di(); break;
case 0xdf: stu_di(); break;
case 0xe0: subb_ix(); break;
case 0xe1: cmpb_ix(); break;
case 0xe2: sbcb_ix(); break;
case 0xe3: addd_ix(); break;
case 0xe4: andb_ix(); break;
case 0xe5: bitb_ix(); break;
case 0xe6: ldb_ix(); break;
case 0xe7: stb_ix(); break;
case 0xe8: eorb_ix(); break;
case 0xe9: adcb_ix(); break;
case 0xea: orb_ix(); break;
case 0xeb: addb_ix(); break;
case 0xec: ldd_ix(); break;
case 0xed: std_ix(); break;
case 0xee: ldu_ix(); break;
case 0xef: stu_ix(); break;
case 0xf0: subb_ex(); break;
case 0xf1: cmpb_ex(); break;
case 0xf2: sbcb_ex(); break;
case 0xf3: addd_ex(); break;
case 0xf4: andb_ex(); break;
case 0xf5: bitb_ex(); break;
case 0xf6: ldb_ex(); break;
case 0xf7: stb_ex(); break;
case 0xf8: eorb_ex(); break;
case 0xf9: adcb_ex(); break;
case 0xfa: orb_ex(); break;
case 0xfb: addb_ex(); break;
case 0xfc: ldd_ex(); break;
case 0xfd: std_ex(); break;
case 0xfe: ldu_ex(); break;
case 0xff: stu_ex(); break;
}
#else
(*hd6309_main[hd6309.ireg])();
#endif /* BIG_SWITCH */
hd6309_ICount -= cycle_counts_page0[hd6309.ireg];
} while( hd6309_ICount > 0 );
hd6309_ICount -= hd6309.extra_cycles;
hd6309.extra_cycles = 0;
}
return cycles - hd6309_ICount; /* NS 970908 */
}
int s2650_execute(int cycles)
{
s2650_ICount = cycles;
do
{
S.ppc = S.page + S.iar;
S.ir = ROP();
s2650_ICount -= S2650_Cycles[S.ir];
S.r = S.ir & 3; /* register / value */
switch (S.ir) {
case 0x00: /* LODZ,0 */
case 0x01: /* LODZ,1 */
case 0x02: /* LODZ,2 */
case 0x03: /* LODZ,3 */
M_LOD( R0, S.reg[S.r] );
break;
case 0x04: /* LODI,0 v */
case 0x05: /* LODI,1 v */
case 0x06: /* LODI,2 v */
case 0x07: /* LODI,3 v */
M_LOD( S.reg[S.r], ARG() );
break;
case 0x08: /* LODR,0 (*)a */
case 0x09: /* LODR,1 (*)a */
case 0x0a: /* LODR,2 (*)a */
case 0x0b: /* LODR,3 (*)a */
REL_EA( S.page );
M_LOD( S.reg[S.r], RDMEM(S.ea) );
break;
case 0x0c: /* LODA,0 (*)a(,X) */
case 0x0d: /* LODA,1 (*)a(,X) */
case 0x0e: /* LODA,2 (*)a(,X) */
case 0x0f: /* LODA,3 (*)a(,X) */
ABS_EA();
M_LOD( S.reg[S.r], RDMEM(S.ea) );
break;
case 0x10: /* illegal */
case 0x11: /* illegal */
break;
case 0x12: /* SPSU */
M_SPSU();
break;
case 0x13: /* SPSL */
M_SPSL();
break;
case 0x14: /* RETC,0 (zero) */
case 0x15: /* RETC,1 (plus) */
case 0x16: /* RETC,2 (minus) */
M_RET( (S.psl >> 6) == S.r );
break;
case 0x17: /* RETC,3 (always) */
M_RET( 1 );
break;
case 0x18: /* BCTR,0 (*)a */
case 0x19: /* BCTR,1 (*)a */
case 0x1a: /* BCTR,2 (*)a */
M_BRR( (S.psl >> 6) == S.r );
break;
case 0x1b: /* BCTR,3 (*)a */
M_BRR( 1 );
break;
case 0x1c: /* BCTA,0 (*)a */
case 0x1d: /* BCTA,1 (*)a */
case 0x1e: /* BCTA,2 (*)a */
M_BRA( (S.psl >> 6) == S.r );
break;
case 0x1f: /* BCTA,3 (*)a */
M_BRA( 1 );
break;
case 0x20: /* EORZ,0 */
case 0x21: /* EORZ,1 */
case 0x22: /* EORZ,2 */
case 0x23: /* EORZ,3 */
M_EOR( R0, S.reg[S.r] );
break;
case 0x24: /* EORI,0 v */
case 0x25: /* EORI,1 v */
case 0x26: /* EORI,2 v */
case 0x27: /* EORI,3 v */
M_EOR( S.reg[S.r], ARG() );
break;
case 0x28: /* EORR,0 (*)a */
case 0x29: /* EORR,1 (*)a */
case 0x2a: /* EORR,2 (*)a */
case 0x2b: /* EORR,3 (*)a */
REL_EA( S.page );
M_EOR( S.reg[S.r], RDMEM(S.ea) );
break;
case 0x2c: /* EORA,0 (*)a(,X) */
case 0x2d: /* EORA,1 (*)a(,X) */
case 0x2e: /* EORA,2 (*)a(,X) */
case 0x2f: /* EORA,3 (*)a(,X) */
ABS_EA();
M_EOR( S.reg[S.r], RDMEM(S.ea) );
break;
case 0x30: /* REDC,0 */
case 0x31: /* REDC,1 */
case 0x32: /* REDC,2 */
case 0x33: /* REDC,3 */
S.reg[S.r] = cpu_readport(S2650_CTRL_PORT);
SET_CC( S.reg[S.r] );
break;
case 0x34: /* RETE,0 */
case 0x35: /* RETE,1 */
case 0x36: /* RETE,2 */
M_RETE( (S.psl >> 6) == S.r );
break;
case 0x37: /* RETE,3 */
M_RETE( 1 );
break;
case 0x38: /* BSTR,0 (*)a */
case 0x39: /* BSTR,1 (*)a */
case 0x3a: /* BSTR,2 (*)a */
M_BSR( (S.psl >> 6) == S.r );
break;
case 0x3b: /* BSTR,R3 (*)a */
M_BSR( 1 );
break;
case 0x3c: /* BSTA,0 (*)a */
case 0x3d: /* BSTA,1 (*)a */
case 0x3e: /* BSTA,2 (*)a */
M_BSA( (S.psl >> 6) == S.r );
break;
case 0x3f: /* BSTA,3 (*)a */
M_BSA( 1 );
break;
case 0x40: /* HALT */
S.iar = (S.iar - 1) & PMSK;
S.halt = 1;
if (s2650_ICount > 0)
s2650_ICount = 0;
break;
case 0x41: /* ANDZ,1 */
case 0x42: /* ANDZ,2 */
case 0x43: /* ANDZ,3 */
M_AND( R0, S.reg[S.r] );
break;
case 0x44: /* ANDI,0 v */
case 0x45: /* ANDI,1 v */
case 0x46: /* ANDI,2 v */
case 0x47: /* ANDI,3 v */
M_AND( S.reg[S.r], ARG() );
break;
case 0x48: /* ANDR,0 (*)a */
case 0x49: /* ANDR,1 (*)a */
case 0x4a: /* ANDR,2 (*)a */
case 0x4b: /* ANDR,3 (*)a */
REL_EA( S.page );
M_AND( S.reg[S.r], RDMEM(S.ea) );
break;
case 0x4c: /* ANDA,0 (*)a(,X) */
case 0x4d: /* ANDA,1 (*)a(,X) */
case 0x4e: /* ANDA,2 (*)a(,X) */
case 0x4f: /* ANDA,3 (*)a(,X) */
ABS_EA();
M_AND( S.reg[S.r], RDMEM(S.ea) );
break;
case 0x50: /* RRR,0 */
case 0x51: /* RRR,1 */
case 0x52: /* RRR,2 */
case 0x53: /* RRR,3 */
M_RRR( S.reg[S.r] );
break;
case 0x54: /* REDE,0 v */
case 0x55: /* REDE,1 v */
case 0x56: /* REDE,2 v */
case 0x57: /* REDE,3 v */
S.reg[S.r] = cpu_readport( ARG() );
SET_CC(S.reg[S.r]);
break;
case 0x58: /* BRNR,0 (*)a */
case 0x59: /* BRNR,1 (*)a */
case 0x5a: /* BRNR,2 (*)a */
case 0x5b: /* BRNR,3 (*)a */
M_BRR( S.reg[S.r] );
break;
case 0x5c: /* BRNA,0 (*)a */
case 0x5d: /* BRNA,1 (*)a */
case 0x5e: /* BRNA,2 (*)a */
case 0x5f: /* BRNA,3 (*)a */
M_BRA( S.reg[S.r] );
break;
case 0x60: /* IORZ,0 */
case 0x61: /* IORZ,1 */
case 0x62: /* IORZ,2 */
case 0x63: /* IORZ,3 */
M_IOR( R0, S.reg[S.r] );
break;
case 0x64: /* IORI,0 v */
case 0x65: /* IORI,1 v */
case 0x66: /* IORI,2 v */
case 0x67: /* IORI,3 v */
M_IOR( S.reg[S.r], ARG() );
break;
case 0x68: /* IORR,0 (*)a */
case 0x69: /* IORR,1 (*)a */
case 0x6a: /* IORR,2 (*)a */
case 0x6b: /* IORR,3 (*)a */
REL_EA( S.page );
M_IOR( S.reg[S. r],RDMEM(S.ea) );
break;
case 0x6c: /* IORA,0 (*)a(,X) */
case 0x6d: /* IORA,1 (*)a(,X) */
case 0x6e: /* IORA,2 (*)a(,X) */
case 0x6f: /* IORA,3 (*)a(,X) */
ABS_EA();
M_IOR( S.reg[S.r], RDMEM(S.ea) );
break;
case 0x70: /* REDD,0 */
case 0x71: /* REDD,1 */
case 0x72: /* REDD,2 */
case 0x73: /* REDD,3 */
S.reg[S.r] = cpu_readport(S2650_DATA_PORT);
SET_CC(S.reg[S.r]);
break;
case 0x74: /* CPSU */
M_CPSU();
break;
case 0x75: /* CPSL */
M_CPSL();
break;
case 0x76: /* PPSU */
M_PPSU();
break;
case 0x77: /* PPSL */
M_PPSL();
break;
case 0x78: /* BSNR,0 (*)a */
case 0x79: /* BSNR,1 (*)a */
case 0x7a: /* BSNR,2 (*)a */
case 0x7b: /* BSNR,3 (*)a */
M_BSR( S.reg[S.r] );
break;
case 0x7c: /* BSNA,0 (*)a */
case 0x7d: /* BSNA,1 (*)a */
case 0x7e: /* BSNA,2 (*)a */
case 0x7f: /* BSNA,3 (*)a */
M_BSA( S.reg[S.r] );
break;
case 0x80: /* ADDZ,0 */
case 0x81: /* ADDZ,1 */
case 0x82: /* ADDZ,2 */
case 0x83: /* ADDZ,3 */
M_ADD( R0,S.reg[S.r] );
break;
case 0x84: /* ADDI,0 v */
case 0x85: /* ADDI,1 v */
case 0x86: /* ADDI,2 v */
case 0x87: /* ADDI,3 v */
M_ADD( S.reg[S.r], ARG() );
break;
case 0x88: /* ADDR,0 (*)a */
case 0x89: /* ADDR,1 (*)a */
case 0x8a: /* ADDR,2 (*)a */
case 0x8b: /* ADDR,3 (*)a */
REL_EA(S.page);
M_ADD( S.reg[S.r], RDMEM(S.ea) );
break;
case 0x8c: /* ADDA,0 (*)a(,X) */
case 0x8d: /* ADDA,1 (*)a(,X) */
case 0x8e: /* ADDA,2 (*)a(,X) */
case 0x8f: /* ADDA,3 (*)a(,X) */
ABS_EA();
M_ADD( S.reg[S.r], RDMEM(S.ea) );
break;
case 0x90: /* illegal */
case 0x91: /* illegal */
break;
case 0x92: /* LPSU */
S.psu = R0 & ~PSU34;
break;
case 0x93: /* LPSL */
/* change register set ? */
if ((S.psl ^ R0) & RS)
SWAP_REGS;
S.psl = R0;
break;
case 0x94: /* DAR,0 */
case 0x95: /* DAR,1 */
case 0x96: /* DAR,2 */
case 0x97: /* DAR,3 */
M_DAR( S.reg[S.r] );
break;
case 0x98: /* BCFR,0 (*)a */
case 0x99: /* BCFR,1 (*)a */
case 0x9a: /* BCFR,2 (*)a */
M_BRR( (S.psl >> 6) != S.r );
break;
case 0x9b: /* ZBRR (*)a */
M_ZBRR();
break;
case 0x9c: /* BCFA,0 (*)a */
case 0x9d: /* BCFA,1 (*)a */
case 0x9e: /* BCFA,2 (*)a */
M_BRA( (S.psl >> 6) != S.r );
break;
case 0x9f: /* BXA (*)a */
M_BXA();
break;
case 0xa0: /* SUBZ,0 */
case 0xa1: /* SUBZ,1 */
case 0xa2: /* SUBZ,2 */
case 0xa3: /* SUBZ,3 */
M_SUB( R0, S.reg[S.r] );
break;
case 0xa4: /* SUBI,0 v */
case 0xa5: /* SUBI,1 v */
case 0xa6: /* SUBI,2 v */
case 0xa7: /* SUBI,3 v */
M_SUB( S.reg[S.r], ARG() );
break;
case 0xa8: /* SUBR,0 (*)a */
case 0xa9: /* SUBR,1 (*)a */
case 0xaa: /* SUBR,2 (*)a */
case 0xab: /* SUBR,3 (*)a */
REL_EA(S.page);
M_SUB( S.reg[S.r], RDMEM(S.ea) );
break;
case 0xac: /* SUBA,0 (*)a(,X) */
case 0xad: /* SUBA,1 (*)a(,X) */
case 0xae: /* SUBA,2 (*)a(,X) */
case 0xaf: /* SUBA,3 (*)a(,X) */
ABS_EA();
M_SUB( S.reg[S.r], RDMEM(S.ea) );
break;
case 0xb0: /* WRTC,0 */
case 0xb1: /* WRTC,1 */
case 0xb2: /* WRTC,2 */
case 0xb3: /* WRTC,3 */
cpu_writeport(S2650_CTRL_PORT,S.reg[S.r]);
break;
case 0xb4: /* TPSU */
M_TPSU();
break;
case 0xb5: /* TPSL */
M_TPSL();
break;
case 0xb6: /* illegal */
case 0xb7: /* illegal */
break;
case 0xb8: /* BSFR,0 (*)a */
case 0xb9: /* BSFR,1 (*)a */
case 0xba: /* BSFR,2 (*)a */
M_BSR( (S.psl >> 6) != S.r );
break;
case 0xbb: /* ZBSR (*)a */
M_ZBSR();
break;
case 0xbc: /* BSFA,0 (*)a */
case 0xbd: /* BSFA,1 (*)a */
case 0xbe: /* BSFA,2 (*)a */
M_BSA( (S.psl >> 6) != S.r );
break;
case 0xbf: /* BSXA (*)a */
M_BSXA();
break;
case 0xc0: /* NOP */
break;
case 0xc1: /* STRZ,1 */
case 0xc2: /* STRZ,2 */
case 0xc3: /* STRZ,3 */
M_LOD( S.reg[S.r], R0 );
break;
case 0xc4: /* illegal */
case 0xc5: /* illegal */
case 0xc6: /* illegal */
case 0xc7: /* illegal */
break;
case 0xc8: /* STRR,0 (*)a */
case 0xc9: /* STRR,1 (*)a */
case 0xca: /* STRR,2 (*)a */
case 0xcb: /* STRR,3 (*)a */
REL_EA(S.page);
M_STR( S.ea, S.reg[S.r] );
break;
case 0xcc: /* STRA,0 (*)a(,X) */
case 0xcd: /* STRA,1 (*)a(,X) */
case 0xce: /* STRA,2 (*)a(,X) */
case 0xcf: /* STRA,3 (*)a(,X) */
ABS_EA();
M_STR( S.ea, S.reg[S.r] );
break;
case 0xd0: /* RRL,0 */
case 0xd1: /* RRL,1 */
case 0xd2: /* RRL,2 */
case 0xd3: /* RRL,3 */
M_RRL( S.reg[S.r] );
break;
case 0xd4: /* WRTE,0 v */
case 0xd5: /* WRTE,1 v */
case 0xd6: /* WRTE,2 v */
case 0xd7: /* WRTE,3 v */
cpu_writeport( ARG(), S.reg[S.r] );
break;
case 0xd8: /* BIRR,0 (*)a */
case 0xd9: /* BIRR,1 (*)a */
case 0xda: /* BIRR,2 (*)a */
case 0xdb: /* BIRR,3 (*)a */
M_BRR( ++S.reg[S.r] );
break;
case 0xdc: /* BIRA,0 (*)a */
case 0xdd: /* BIRA,1 (*)a */
case 0xde: /* BIRA,2 (*)a */
case 0xdf: /* BIRA,3 (*)a */
M_BRA( ++S.reg[S.r] );
break;
case 0xe0: /* COMZ,0 */
case 0xe1: /* COMZ,1 */
case 0xe2: /* COMZ,2 */
case 0xe3: /* COMZ,3 */
M_COM( R0, S.reg[S.r] );
break;
case 0xe4: /* COMI,0 v */
case 0xe5: /* COMI,1 v */
case 0xe6: /* COMI,2 v */
case 0xe7: /* COMI,3 v */
M_COM( S.reg[S.r], ARG() );
break;
case 0xe8: /* COMR,0 (*)a */
case 0xe9: /* COMR,1 (*)a */
case 0xea: /* COMR,2 (*)a */
case 0xeb: /* COMR,3 (*)a */
REL_EA(S.page);
M_COM( S.reg[S.r], RDMEM(S.ea) );
break;
case 0xec: /* COMA,0 (*)a(,X) */
case 0xed: /* COMA,1 (*)a(,X) */
case 0xee: /* COMA,2 (*)a(,X) */
case 0xef: /* COMA,3 (*)a(,X) */
ABS_EA();
M_COM( S.reg[S.r], RDMEM(S.ea) );
break;
case 0xf0: /* WRTD,0 */
case 0xf1: /* WRTD,1 */
case 0xf2: /* WRTD,2 */
case 0xf3: /* WRTD,3 */
cpu_writeport(S2650_DATA_PORT, S.reg[S.r]);
break;
case 0xf4: /* TMI,0 v */
case 0xf5: /* TMI,1 v */
case 0xf6: /* TMI,2 v */
case 0xf7: /* TMI,3 v */
M_TMI( S.reg[S.r] );
break;
case 0xf8: /* BDRR,0 (*)a */
case 0xf9: /* BDRR,1 (*)a */
case 0xfa: /* BDRR,2 (*)a */
case 0xfb: /* BDRR,3 (*)a */
M_BRR( --S.reg[S.r] );
break;
case 0xfc: /* BDRA,0 (*)a */
case 0xfd: /* BDRA,1 (*)a */
case 0xfe: /* BDRA,2 (*)a */
case 0xff: /* BDRA,3 (*)a */
M_BRA( --S.reg[S.r] );
break;
}
} while( s2650_ICount > 0 );
return cycles - s2650_ICount;
}
//illegal opcodes
INLINE void illegal(void)
{
LOG(("i8051 #%d: illegal opcode at 0x%03x: %02x\n", cpu_getactivecpu(), PC, ROP(PC)));
}
/* execute instructions on this CPU until icount expires */
static CPU_EXECUTE( m6809 ) /* NS 970908 */
{
m68_state_t *m68_state = get_safe_token(device);
m68_state->icount = cycles - m68_state->extra_cycles;
m68_state->extra_cycles = 0;
check_irq_lines(m68_state);
if (m68_state->int_state & (M6809_CWAI | M6809_SYNC))
{
debugger_instruction_hook(device, PCD);
m68_state->icount = 0;
}
else
{
do
{
pPPC = pPC;
debugger_instruction_hook(device, PCD);
m68_state->ireg = ROP(PCD);
PC++;
#if BIG_SWITCH
switch( m68_state->ireg )
{
case 0x00: neg_di(m68_state); break;
case 0x01: neg_di(m68_state); break; /* undocumented */
case 0x02: IIError(m68_state); break;
case 0x03: com_di(m68_state); break;
case 0x04: lsr_di(m68_state); break;
case 0x05: IIError(m68_state); break;
case 0x06: ror_di(m68_state); break;
case 0x07: asr_di(m68_state); break;
case 0x08: asl_di(m68_state); break;
case 0x09: rol_di(m68_state); break;
case 0x0a: dec_di(m68_state); break;
case 0x0b: IIError(m68_state); break;
case 0x0c: inc_di(m68_state); break;
case 0x0d: tst_di(m68_state); break;
case 0x0e: jmp_di(m68_state); break;
case 0x0f: clr_di(m68_state); break;
case 0x10: pref10(m68_state); break;
case 0x11: pref11(m68_state); break;
case 0x12: nop(m68_state); break;
case 0x13: sync(m68_state); break;
case 0x14: IIError(m68_state); break;
case 0x15: IIError(m68_state); break;
case 0x16: lbra(m68_state); break;
case 0x17: lbsr(m68_state); break;
case 0x18: IIError(m68_state); break;
case 0x19: daa(m68_state); break;
case 0x1a: orcc(m68_state); break;
case 0x1b: IIError(m68_state); break;
case 0x1c: andcc(m68_state); break;
case 0x1d: sex(m68_state); break;
case 0x1e: exg(m68_state); break;
case 0x1f: tfr(m68_state); break;
case 0x20: bra(m68_state); break;
case 0x21: brn(m68_state); break;
case 0x22: bhi(m68_state); break;
case 0x23: bls(m68_state); break;
case 0x24: bcc(m68_state); break;
case 0x25: bcs(m68_state); break;
case 0x26: bne(m68_state); break;
case 0x27: beq(m68_state); break;
case 0x28: bvc(m68_state); break;
case 0x29: bvs(m68_state); break;
case 0x2a: bpl(m68_state); break;
case 0x2b: bmi(m68_state); break;
case 0x2c: bge(m68_state); break;
case 0x2d: blt(m68_state); break;
case 0x2e: bgt(m68_state); break;
case 0x2f: ble(m68_state); break;
case 0x30: leax(m68_state); break;
case 0x31: leay(m68_state); break;
case 0x32: leas(m68_state); break;
case 0x33: leau(m68_state); break;
case 0x34: pshs(m68_state); break;
case 0x35: puls(m68_state); break;
case 0x36: pshu(m68_state); break;
case 0x37: pulu(m68_state); break;
case 0x38: IIError(m68_state); break;
case 0x39: rts(m68_state); break;
case 0x3a: abx(m68_state); break;
case 0x3b: rti(m68_state); break;
case 0x3c: cwai(m68_state); break;
case 0x3d: mul(m68_state); break;
case 0x3e: IIError(m68_state); break;
case 0x3f: swi(m68_state); break;
case 0x40: nega(m68_state); break;
case 0x41: IIError(m68_state); break;
case 0x42: IIError(m68_state); break;
case 0x43: coma(m68_state); break;
case 0x44: lsra(m68_state); break;
case 0x45: IIError(m68_state); break;
case 0x46: rora(m68_state); break;
case 0x47: asra(m68_state); break;
case 0x48: asla(m68_state); break;
case 0x49: rola(m68_state); break;
case 0x4a: deca(m68_state); break;
case 0x4b: IIError(m68_state); break;
case 0x4c: inca(m68_state); break;
case 0x4d: tsta(m68_state); break;
case 0x4e: IIError(m68_state); break;
case 0x4f: clra(m68_state); break;
case 0x50: negb(m68_state); break;
case 0x51: IIError(m68_state); break;
case 0x52: IIError(m68_state); break;
case 0x53: comb(m68_state); break;
case 0x54: lsrb(m68_state); break;
case 0x55: IIError(m68_state); break;
case 0x56: rorb(m68_state); break;
case 0x57: asrb(m68_state); break;
case 0x58: aslb(m68_state); break;
case 0x59: rolb(m68_state); break;
case 0x5a: decb(m68_state); break;
case 0x5b: IIError(m68_state); break;
case 0x5c: incb(m68_state); break;
case 0x5d: tstb(m68_state); break;
case 0x5e: IIError(m68_state); break;
case 0x5f: clrb(m68_state); break;
case 0x60: neg_ix(m68_state); break;
case 0x61: IIError(m68_state); break;
case 0x62: IIError(m68_state); break;
case 0x63: com_ix(m68_state); break;
case 0x64: lsr_ix(m68_state); break;
case 0x65: IIError(m68_state); break;
case 0x66: ror_ix(m68_state); break;
case 0x67: asr_ix(m68_state); break;
case 0x68: asl_ix(m68_state); break;
case 0x69: rol_ix(m68_state); break;
case 0x6a: dec_ix(m68_state); break;
case 0x6b: IIError(m68_state); break;
case 0x6c: inc_ix(m68_state); break;
case 0x6d: tst_ix(m68_state); break;
case 0x6e: jmp_ix(m68_state); break;
case 0x6f: clr_ix(m68_state); break;
case 0x70: neg_ex(m68_state); break;
case 0x71: IIError(m68_state); break;
case 0x72: IIError(m68_state); break;
case 0x73: com_ex(m68_state); break;
case 0x74: lsr_ex(m68_state); break;
case 0x75: IIError(m68_state); break;
case 0x76: ror_ex(m68_state); break;
case 0x77: asr_ex(m68_state); break;
case 0x78: asl_ex(m68_state); break;
case 0x79: rol_ex(m68_state); break;
case 0x7a: dec_ex(m68_state); break;
case 0x7b: IIError(m68_state); break;
case 0x7c: inc_ex(m68_state); break;
case 0x7d: tst_ex(m68_state); break;
case 0x7e: jmp_ex(m68_state); break;
case 0x7f: clr_ex(m68_state); break;
case 0x80: suba_im(m68_state); break;
case 0x81: cmpa_im(m68_state); break;
case 0x82: sbca_im(m68_state); break;
case 0x83: subd_im(m68_state); break;
case 0x84: anda_im(m68_state); break;
case 0x85: bita_im(m68_state); break;
case 0x86: lda_im(m68_state); break;
case 0x87: sta_im(m68_state); break;
case 0x88: eora_im(m68_state); break;
case 0x89: adca_im(m68_state); break;
case 0x8a: ora_im(m68_state); break;
case 0x8b: adda_im(m68_state); break;
case 0x8c: cmpx_im(m68_state); break;
case 0x8d: bsr(m68_state); break;
case 0x8e: ldx_im(m68_state); break;
case 0x8f: stx_im(m68_state); break;
case 0x90: suba_di(m68_state); break;
case 0x91: cmpa_di(m68_state); break;
case 0x92: sbca_di(m68_state); break;
case 0x93: subd_di(m68_state); break;
case 0x94: anda_di(m68_state); break;
case 0x95: bita_di(m68_state); break;
case 0x96: lda_di(m68_state); break;
case 0x97: sta_di(m68_state); break;
case 0x98: eora_di(m68_state); break;
case 0x99: adca_di(m68_state); break;
case 0x9a: ora_di(m68_state); break;
case 0x9b: adda_di(m68_state); break;
case 0x9c: cmpx_di(m68_state); break;
case 0x9d: jsr_di(m68_state); break;
case 0x9e: ldx_di(m68_state); break;
case 0x9f: stx_di(m68_state); break;
case 0xa0: suba_ix(m68_state); break;
case 0xa1: cmpa_ix(m68_state); break;
case 0xa2: sbca_ix(m68_state); break;
case 0xa3: subd_ix(m68_state); break;
case 0xa4: anda_ix(m68_state); break;
case 0xa5: bita_ix(m68_state); break;
case 0xa6: lda_ix(m68_state); break;
case 0xa7: sta_ix(m68_state); break;
case 0xa8: eora_ix(m68_state); break;
case 0xa9: adca_ix(m68_state); break;
case 0xaa: ora_ix(m68_state); break;
case 0xab: adda_ix(m68_state); break;
case 0xac: cmpx_ix(m68_state); break;
case 0xad: jsr_ix(m68_state); break;
case 0xae: ldx_ix(m68_state); break;
case 0xaf: stx_ix(m68_state); break;
case 0xb0: suba_ex(m68_state); break;
case 0xb1: cmpa_ex(m68_state); break;
case 0xb2: sbca_ex(m68_state); break;
case 0xb3: subd_ex(m68_state); break;
case 0xb4: anda_ex(m68_state); break;
case 0xb5: bita_ex(m68_state); break;
case 0xb6: lda_ex(m68_state); break;
case 0xb7: sta_ex(m68_state); break;
case 0xb8: eora_ex(m68_state); break;
case 0xb9: adca_ex(m68_state); break;
case 0xba: ora_ex(m68_state); break;
case 0xbb: adda_ex(m68_state); break;
case 0xbc: cmpx_ex(m68_state); break;
case 0xbd: jsr_ex(m68_state); break;
case 0xbe: ldx_ex(m68_state); break;
case 0xbf: stx_ex(m68_state); break;
case 0xc0: subb_im(m68_state); break;
case 0xc1: cmpb_im(m68_state); break;
case 0xc2: sbcb_im(m68_state); break;
case 0xc3: addd_im(m68_state); break;
case 0xc4: andb_im(m68_state); break;
case 0xc5: bitb_im(m68_state); break;
case 0xc6: ldb_im(m68_state); break;
case 0xc7: stb_im(m68_state); break;
case 0xc8: eorb_im(m68_state); break;
case 0xc9: adcb_im(m68_state); break;
case 0xca: orb_im(m68_state); break;
case 0xcb: addb_im(m68_state); break;
case 0xcc: ldd_im(m68_state); break;
case 0xcd: std_im(m68_state); break;
case 0xce: ldu_im(m68_state); break;
case 0xcf: stu_im(m68_state); break;
case 0xd0: subb_di(m68_state); break;
case 0xd1: cmpb_di(m68_state); break;
case 0xd2: sbcb_di(m68_state); break;
case 0xd3: addd_di(m68_state); break;
case 0xd4: andb_di(m68_state); break;
case 0xd5: bitb_di(m68_state); break;
case 0xd6: ldb_di(m68_state); break;
case 0xd7: stb_di(m68_state); break;
case 0xd8: eorb_di(m68_state); break;
case 0xd9: adcb_di(m68_state); break;
case 0xda: orb_di(m68_state); break;
case 0xdb: addb_di(m68_state); break;
case 0xdc: ldd_di(m68_state); break;
case 0xdd: std_di(m68_state); break;
case 0xde: ldu_di(m68_state); break;
case 0xdf: stu_di(m68_state); break;
case 0xe0: subb_ix(m68_state); break;
case 0xe1: cmpb_ix(m68_state); break;
case 0xe2: sbcb_ix(m68_state); break;
case 0xe3: addd_ix(m68_state); break;
case 0xe4: andb_ix(m68_state); break;
case 0xe5: bitb_ix(m68_state); break;
case 0xe6: ldb_ix(m68_state); break;
case 0xe7: stb_ix(m68_state); break;
case 0xe8: eorb_ix(m68_state); break;
case 0xe9: adcb_ix(m68_state); break;
case 0xea: orb_ix(m68_state); break;
case 0xeb: addb_ix(m68_state); break;
case 0xec: ldd_ix(m68_state); break;
case 0xed: std_ix(m68_state); break;
case 0xee: ldu_ix(m68_state); break;
case 0xef: stu_ix(m68_state); break;
case 0xf0: subb_ex(m68_state); break;
case 0xf1: cmpb_ex(m68_state); break;
case 0xf2: sbcb_ex(m68_state); break;
case 0xf3: addd_ex(m68_state); break;
case 0xf4: andb_ex(m68_state); break;
case 0xf5: bitb_ex(m68_state); break;
case 0xf6: ldb_ex(m68_state); break;
case 0xf7: stb_ex(m68_state); break;
case 0xf8: eorb_ex(m68_state); break;
case 0xf9: adcb_ex(m68_state); break;
case 0xfa: orb_ex(m68_state); break;
case 0xfb: addb_ex(m68_state); break;
case 0xfc: ldd_ex(m68_state); break;
case 0xfd: std_ex(m68_state); break;
case 0xfe: ldu_ex(m68_state); break;
case 0xff: stu_ex(m68_state); break;
}
#else
(*m6809_main[m68_state->ireg])(m68_state);
#endif /* BIG_SWITCH */
m68_state->icount -= cycles1[m68_state->ireg];
} while( m68_state->icount > 0 );
m68_state->icount -= m68_state->extra_cycles;
m68_state->extra_cycles = 0;
}
return cycles - m68_state->icount; /* NS 970908 */
}
